Started : "Synthesize - XST". Running xst... Command Line: xst -intstyle ise -ifn "D:/Base Danni Metal_Mill LTD/Mesa_Project_Analog_Encoder_PWM/hostmod/7i98/configs/hostmot2/source/hostmot2/TopEthernetHostMot2.xst" -ofn "D:/Base Danni Metal_Mill LTD/Mesa_Project_Analog_Encoder_PWM/hostmod/7i98/configs/hostmot2/source/hostmot2/TopEthernetHostMot2.syr" Reading design: TopEthernetHostMot2.prj ========================================================================= * HDL Parsing * ========================================================================= Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\log2.vhd" into library work Parsing package . Parsing package body . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\dpram.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\adpram.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\waveram.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\uartx8b.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\uartx8.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\uartr8b.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\uartr8.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\twidrom.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\syncwavegen.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\sslbprom46.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\sslbprom43.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\sslbpram.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\sine16.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\resrom.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\resolverdaq2.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\parity.vhd" into library work Parsing package . Parsing package body . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\OutputInteg.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\oneofndecode.vhd" into library work Parsing package . Parsing package body . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\IDROMConst.vhd" into library work Parsing package . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\ibound.vhd" into library work Parsing package . Parsing package body . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\decodedstrobe.vhd" into library work Parsing package . Parsing package body . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\d8o8sqwsb.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\d8o8sqws.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\b32qcondmac2ws.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\xy2mod.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\xfrmrout.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\wordrb.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\wordpr.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\wavegen.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\watchdog.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\ubrategend.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\ubrategen.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\uartx.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\uartr.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\twiddle.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\timestampd.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\timestamp.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\threephasepwm.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\sserialwab.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\sserialwa.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\srl16delay.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\simplessi.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\simplespix.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\simpledsad.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\scalertimer.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\scalercounter.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\resolver.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\rcpwmrate.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\rcpwmgen.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\qcountersfpd.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\qcountersfp.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\qcountersfd.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\qcountersf.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\qcounterateskd.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\qcounteratesk.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\qcounterated.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\qcounterate.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\pwmrefh.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\pwmpdmgenh.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\pktuartx.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\pktuartr.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\PinExists.vhd" into library work Parsing package . Parsing package body . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\OutputPinsPerModule.vhd" into library work Parsing package . Parsing package body . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\outm.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\oneshot.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\NumberOfModules.vhd" into library work Parsing package . Parsing package body . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\ModuleExists.vhd" into library work Parsing package . Parsing package body . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\MaxPinsPerModule.vhd" into library work Parsing package . Parsing package body . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\MaxOutputPinsPerModule.vhd" into library work Parsing package . Parsing package body . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\MaxIOPinsPerModule.vhd" into library work Parsing package . Parsing package body . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\MaxInputPinsPerModule.vhd" into library work Parsing package . Parsing package body . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\kubstepgenzid.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\kubstepgenzi.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\kubstepgenzd.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\kubstepgenz.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\irqlogics.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\InputPinsPerModule.vhd" into library work Parsing package . Parsing package body . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\inmuxm.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\inm.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\idrom.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\hostmotid.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\hmtimers.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\GetModuleHint.vhd" into library work Parsing package . Parsing package body . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\fanucabs.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\drqlogic.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\dpainter.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\daqfifo16.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\cpdrive.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\CountPinsInRange.vhd" into library work Parsing package . Parsing package body . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\bufferedspi.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\boutreg.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\biss_loop.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\binosc.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\simplespi8x.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\PIN_5ABOBx3D_51Copy.vhd" into library work Parsing package . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\i98_x9card.vhd" into library work Parsing package . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\hostmot2.vhd" into library work Parsing entity . Parsing architecture of entity . WARNING:HDLCompiler:1369 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\hostmot2.vhd" Line 2582: Possible infinite loop; process does not have a wait statement WARNING:HDLCompiler:1369 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\hostmot2.vhd" Line 2609: Possible infinite loop; process does not have a wait statement Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\fixicap.vhd" into library work Parsing package . Parsing package body . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\etherhm2.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\d16w.vhd" into library work Parsing entity . Parsing architecture of entity . Parsing VHDL file "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\TopEthernet16HostMot2.vhd" into library work Parsing entity . Parsing architecture of entity . ========================================================================= * HDL Elaboration * ========================================================================= WARNING:HDLCompiler:746 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\TopEthernet16HostMot2.vhd" Line 389: Range is empty (null range) Elaborating entity (architecture ) with generics from library . WARNING:HDLCompiler:746 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\hostmot2.vhd" Line 137: Range is empty (null range) Elaborating entity (architecture ) with generics from library . WARNING:HDLCompiler:746 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\hostmot2.vhd" Line 156: Range is empty (null range) WARNING:HDLCompiler:746 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\hostmot2.vhd" Line 302: Range is empty (null range) Elaborating entity (architecture ) with generics from library . INFO:HDLCompiler:679 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\hostmotid.vhd" Line 98. Case statement is complete. others clause is never selected Elaborating entity (architecture ) with generics from library . Elaborating entity (architecture ) with generics from library . Elaborating entity (architecture ) with generics from library . Elaborating entity (architecture ) with generics from library . Elaborating entity (architecture ) from library . Elaborating entity (architecture ) from library . Elaborating entity (architecture ) with generics from library . WARNING:HDLCompiler:89 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\kubstepgenzid.vhd" Line 167: remains a black-box since it has no binding entity. WARNING:HDLCompiler:92 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\kubstepgenzid.vhd" Line 377: timer should be on the sensitivity list of the process WARNING:HDLCompiler:92 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\kubstepgenzid.vhd" Line 390: steplatch should be on the sensitivity list of the process WARNING:HDLCompiler:92 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\kubstepgenzid.vhd" Line 393: readstepmode should be on the sensitivity list of the process WARNING:HDLCompiler:92 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\kubstepgenzid.vhd" Line 395: countlatch should be on the sensitivity list of the process INFO:HDLCompiler:679 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\kubstepgenzid.vhd" Line 430. Case statement is complete. others clause is never selected Note: "Making shared index from I/O: 1" Note: "and instance: 1" Note: "Making shared index from I/O: 10" Note: "and instance: 0" Elaborating entity (architecture ) with generics from library . Note: "Encoder rate divisor: 4.0" Elaborating entity (architecture ) from library . WARNING:HDLCompiler:92 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\timestampd.vhd" Line 113: timerenable should be on the sensitivity list of the process Elaborating entity (architecture ) with generics from library . WARNING:HDLCompiler:634 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\qcountersfd.vhd" Line 101: Net does not have a driver. Elaborating entity (architecture ) with generics from library . Elaborating entity (architecture ) with generics from library . INFO:HDLCompiler:679 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\pwmpdmgenh.vhd" Line 159. Case statement is complete. others clause is never selected INFO:HDLCompiler:679 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\pwmpdmgenh.vhd" Line 188. Case statement is complete. others clause is never selected INFO:HDLCompiler:679 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\pwmpdmgenh.vhd" Line 229. Case statement is complete. others clause is never selected WARNING:HDLCompiler:746 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\hostmot2.vhd" Line 1808: Range is empty (null range) Elaborating entity (architecture ) with generics from library . WARNING:HDLCompiler:634 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\inmuxm.vhd" Line 96: Net does not have a driver. WARNING:HDLCompiler:746 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\sserialwa.vhd" Line 91: Range is empty (null range) WARNING:HDLCompiler:746 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\hostmot2.vhd" Line 4404: Range is empty (null range) Elaborating entity (architecture ) with generics from library . Elaborating entity (architecture ) with generics from library . Elaborating entity (architecture ) with generics from library . INFO:HDLCompiler:679 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\d8o8sqws.vhd" Line 351. Case statement is complete. others clause is never selected Elaborating entity (architecture ) from library . Elaborating entity (architecture ) from library . WARNING:HDLCompiler:746 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\adpram.vhd" Line 77: Range is empty (null range) WARNING:HDLCompiler:746 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\adpram.vhd" Line 78: Range is empty (null range) WARNING:HDLCompiler:746 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\sserialwa.vhd" Line 315: Range is empty (null range) Elaborating entity (architecture ) with generics from library . WARNING:HDLCompiler:220 - "N:/P.20131013/rtf/vhdl/xst/src/syn_unsi.vhd" Line 318: Assignment ignored WARNING:HDLCompiler:746 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\sserialwa.vhd" Line 331: Range is empty (null range) WARNING:HDLCompiler:746 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\sserialwa.vhd" Line 345: Range is empty (null range) WARNING:HDLCompiler:746 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\sserialwa.vhd" Line 361: Range is empty (null range) WARNING:HDLCompiler:746 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\sserialwa.vhd" Line 375: Range is empty (null range) WARNING:HDLCompiler:746 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\sserialwa.vhd" Line 391: Range is empty (null range) WARNING:HDLCompiler:746 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\sserialwa.vhd" Line 405: Range is empty (null range) WARNING:HDLCompiler:746 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\sserialwa.vhd" Line 421: Range is empty (null range) Elaborating entity (architecture ) with generics from library . WARNING:HDLCompiler:89 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\uartr8.vhd" Line 138: remains a black-box since it has no binding entity. Note: "Default FilterReg = 20" Elaborating entity (architecture ) from library . WARNING:HDLCompiler:89 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\uartx8.vhd" Line 132: remains a black-box since it has no binding entity. INFO:HDLCompiler:679 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\sserialwa.vhd" Line 625. Case statement is complete. others clause is never selected INFO:HDLCompiler:679 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\sserialwa.vhd" Line 645. Case statement is complete. others clause is never selected INFO:HDLCompiler:679 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\sserialwa.vhd" Line 710. Case statement is complete. others clause is never selected WARNING:HDLCompiler:746 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\sserialwa.vhd" Line 811: Range is empty (null range) WARNING:HDLCompiler:746 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\sserialwa.vhd" Line 812: Range is empty (null range) WARNING:HDLCompiler:746 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\sserialwa.vhd" Line 813: Range is empty (null range) WARNING:HDLCompiler:746 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\sserialwa.vhd" Line 814: Range is empty (null range) WARNING:HDLCompiler:746 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\sserialwa.vhd" Line 815: Range is empty (null range) WARNING:HDLCompiler:746 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\sserialwa.vhd" Line 816: Range is empty (null range) WARNING:HDLCompiler:746 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\sserialwa.vhd" Line 817: Range is empty (null range) WARNING:HDLCompiler:746 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\sserialwa.vhd" Line 818: Range is empty (null range) WARNING:HDLCompiler:746 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\sserialwa.vhd" Line 819: Range is empty (null range) WARNING:HDLCompiler:746 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\sserialwa.vhd" Line 835: Range is empty (null range) WARNING:HDLCompiler:746 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\sserialwa.vhd" Line 836: Range is empty (null range) WARNING:HDLCompiler:746 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\sserialwa.vhd" Line 837: Range is empty (null range) WARNING:HDLCompiler:746 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\sserialwa.vhd" Line 838: Range is empty (null range) WARNING:HDLCompiler:746 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\sserialwa.vhd" Line 842: Range is empty (null range) WARNING:HDLCompiler:746 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\sserialwa.vhd" Line 843: Range is empty (null range) WARNING:HDLCompiler:746 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\sserialwa.vhd" Line 844: Range is empty (null range) WARNING:HDLCompiler:746 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\sserialwa.vhd" Line 845: Range is empty (null range) Note: "Max UARTS per sserial 1" Note: "UARTS per sserial 0 1" Note: "UARTS per sserial 1 0" Note: "UARTS per sserial 2 0" Note: "UARTS per sserial 3 0" WARNING:HDLCompiler:746 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\hostmot2.vhd" Line 4500: Range is empty (null range) Elaborating entity (architecture ) with generics from library . WARNING:HDLCompiler:746 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\boutreg.vhd" Line 107: Range is empty (null range) WARNING:HDLCompiler:220 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\boutreg.vhd" Line 107: Assignment ignored Elaborating entity (architecture ) with generics from library . Elaborating entity (architecture ) with generics from library . WARNING:HDLCompiler:634 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\hostmot2.vhd" Line 267: Net does not have a driver. WARNING:HDLCompiler:634 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\hostmot2.vhd" Line 283: Net does not have a driver. WARNING:HDLCompiler:634 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\hostmot2.vhd" Line 469: Net does not have a driver. WARNING:HDLCompiler:634 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\hostmot2.vhd" Line 625: Net does not have a driver. WARNING:HDLCompiler:634 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\hostmot2.vhd" Line 992: Net does not have a driver. Elaborating entity (architecture ) with generics from library . Elaborating entity (architecture ) with generics from library . Elaborating entity (architecture ) with generics from library . INFO:HDLCompiler:679 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\d16w.vhd" Line 360. Case statement is complete. others clause is never selected Elaborating entity (architecture ) from library . Elaborating entity (architecture ) with generics from library . INFO:HDLCompiler:679 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\TopEthernet16HostMot2.vhd" Line 975. Case statement is complete. others clause is never selected INFO:HDLCompiler:679 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\TopEthernet16HostMot2.vhd" Line 1002. Case statement is complete. others clause is never selected WARNING:HDLCompiler:92 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\TopEthernet16HostMot2.vhd" Line 1006: readrates should be on the sensitivity list of the process WARNING:HDLCompiler:92 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\TopEthernet16HostMot2.vhd" Line 1007: rates should be on the sensitivity list of the process WARNING:HDLCompiler:92 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\TopEthernet16HostMot2.vhd" Line 1099: icapo should be on the sensitivity list of the process ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\TopEthernet16HostMot2.vhd". ThePinDesc = ("00000011000000010000010000000001","00000011000000010000010000000110","00000011000000010000010000000010","00000011000001000000010000000011","00000011000000001100000100000001","00000011000001000000010000000010","00000011000000001100000110000001","00000011000001000000010000000001","00000011000000000000010000000001","00000011000000000000010000000010","00000011000000000000010000000110","00000011000000110000010000000011","00000011000000110000010000000010","00000011000000110000010000000001","000000110 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(("00011010","00000000","00000001","00000001","0111000000000000","00000111","00000000","00000000000000000000000000000000"),("00000010","00000000","00000001","00000001","0000110000000000","00000011","00000000","00000000000000000000000000000000"),("00000011","00000000","00000001","00000011","0001000000000000","00000101","00000000","00000000000000000000000000011111"),("00011110","00000000","00000001","00000001","1000000000000000","00000101","00000000","00000000000000000000000000011111"),("00000100", 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16 InstStride0 = 4 InstStride1 = 64 RegStride0 = 256 RegStride1 = 256 FallBack = false INFO:Xst:3210 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\TopEthernet16HostMot2.vhd" line 521: Output port of the instance is unconnected or connected to loadless signal. INFO:Xst:3210 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\TopEthernet16HostMot2.vhd" line 521: Output port of the instance is unconnected or connected to loadless signal. INFO:Xst:3210 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\TopEthernet16HostMot2.vhd" line 521: Output port of the instance is unconnected or connected to loadless signal. INFO:Xst:3210 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\TopEthernet16HostMot2.vhd" line 682: Output port of the instance is unconnected or connected to loadless signal. INFO:Xst:3210 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\TopEthernet16HostMot2.vhd" line 710: Output port of the instance is unconnected or connected to loadless signal. Found 1-bit register for signal . Found 4-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 32-bit register for signal . Found 16-bit register for signal . Found 32-bit register for signal . Found 5-bit register for signal . Found 16-bit register for signal . Found 1-bit register for signal . Found 2-bit register for signal . Found 8-bit register for signal . Found 16-bit register for signal . Found 16-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 2-bit register for signal . Found 12-bit register for signal . Found 16-bit adder for signal created at line 989. Found 2-bit adder for signal created at line 1057. Found 16-bit adder for signal created at line 1078. Found 8-bit subtractor for signal > created at line 1075. Found 1-bit tristate buffer for signal > created at line 952 Found 1-bit tristate buffer for signal > created at line 952 Found 1-bit tristate buffer for signal > created at line 952 Found 1-bit tristate buffer for signal > created at line 952 Found 1-bit tristate buffer for signal > created at line 952 Found 1-bit tristate buffer for signal > created at line 952 Found 1-bit tristate buffer for signal > created at line 952 Found 1-bit tristate buffer for signal > created at line 952 Found 1-bit tristate buffer for signal > created at line 952 Found 1-bit tristate buffer for signal > created at line 952 Found 1-bit tristate buffer for signal > created at line 952 Found 1-bit tristate buffer for signal > created at line 952 Found 1-bit tristate buffer for signal > created at line 952 Found 1-bit tristate buffer for signal > created at line 952 Found 1-bit tristate buffer for signal > created at line 952 Found 1-bit tristate buffer for signal > created at line 952 Found 1-bit tristate buffer for signal > created at line 1022 Found 1-bit tristate buffer for signal > created at line 1022 Found 1-bit tristate buffer for signal > created at line 1022 Found 1-bit tristate buffer for signal > created at line 1022 Found 1-bit tristate buffer for signal > created at line 1022 Found 1-bit tristate buffer for signal > created at line 1022 Found 1-bit tristate buffer for signal > created at line 1022 Found 1-bit tristate buffer for signal > created at line 1022 Found 1-bit tristate buffer for signal > created at line 1022 Found 1-bit tristate buffer for signal > created at line 1022 Found 1-bit tristate buffer for signal > created at line 1022 Found 1-bit tristate buffer for signal > created at line 1022 Found 1-bit tristate buffer for signal > created at line 1022 Found 1-bit tristate buffer for signal > created at line 1022 Found 1-bit tristate buffer for signal > created at line 1022 Found 1-bit tristate buffer for signal > created at line 1022 Found 1-bit tristate buffer for signal > created at line 1022 Found 1-bit tristate buffer for signal > created at line 1022 Found 1-bit tristate buffer for signal > created at line 1022 Found 1-bit tristate buffer for signal > created at line 1022 Found 1-bit tristate buffer for signal > created at line 1022 Found 1-bit tristate buffer for signal > created at line 1022 Found 1-bit tristate buffer for signal > created at line 1022 Found 1-bit tristate buffer for signal > created at line 1022 Found 1-bit tristate buffer for signal > created at line 1022 Found 1-bit tristate buffer for signal > created at line 1022 Found 1-bit tristate buffer for signal > created at line 1022 Found 1-bit tristate buffer for signal > created at line 1022 Found 1-bit tristate buffer for signal > created at line 1022 Found 1-bit tristate buffer for signal > created at line 1022 Found 1-bit tristate buffer for signal > created at line 1022 Found 1-bit tristate buffer for signal > created at line 1022 Found 1-bit tristate buffer for signal > created at line 1068 Found 1-bit tristate buffer for signal > created at line 1068 Found 1-bit tristate buffer for signal > created at line 1068 Found 1-bit tristate buffer for signal > created at line 1068 Found 1-bit tristate buffer for signal > created at line 1068 Found 1-bit tristate buffer for signal > created at line 1068 Found 1-bit tristate buffer for signal > created at line 1068 Found 1-bit tristate buffer for signal > created at line 1068 Found 1-bit tristate buffer for signal > created at line 1068 Found 1-bit tristate buffer for signal > created at line 1068 Found 1-bit tristate buffer for signal > created at line 1068 Found 1-bit tristate buffer for signal > created at line 1068 Found 1-bit tristate buffer for signal > created at line 1068 Found 1-bit tristate buffer for signal > created at line 1068 Found 1-bit tristate buffer for signal > created at line 1068 Found 1-bit tristate buffer for signal > created at line 1068 Found 1-bit tristate buffer for signal > created at line 1083 Found 1-bit tristate buffer for signal > created at line 1083 Found 1-bit tristate buffer for signal > created at line 1083 Found 1-bit tristate buffer for signal > created at line 1083 Found 1-bit tristate buffer for signal > created at line 1083 Found 1-bit tristate buffer for signal > created at line 1083 Found 1-bit tristate buffer for signal > created at line 1083 Found 1-bit tristate buffer for signal > created at line 1083 Found 1-bit tristate buffer for signal > created at line 1083 Found 1-bit tristate buffer for signal > created at line 1083 Found 1-bit tristate buffer for signal > created at line 1083 Found 1-bit tristate buffer for signal > created at line 1083 Found 1-bit tristate buffer for signal > created at line 1083 Found 1-bit tristate buffer for signal > created at line 1083 Found 1-bit tristate buffer for signal > created at line 1083 Found 1-bit tristate buffer for signal > created at line 1083 Found 1-bit tristate buffer for signal > created at line 1105 Found 1-bit tristate buffer for signal > created at line 1105 Summary: inferred 4 Adder/Subtractor(s). inferred 167 D-type flip-flop(s). inferred 62 Multiplexer(s). inferred 82 Tristate(s). Unit synthesized. Synthesizing Unit . Related source file is "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\hostmot2.vhd". ThePinDesc = ("00000011000000010000010000000001","00000011000000010000010000000110","00000011000000010000010000000010","00000011000001000000010000000011","00000011000000001100000100000001","00000011000001000000010000000010","00000011000000001100000110000001","00000011000001000000010000000001","00000011000000000000010000000001","00000011000000000000010000000010","00000011000000000000010000000110","00000011000000110000010000000011","00000011000000110000010000000010","00000011000000110000010000000001","000000110 00000100000010000000011","00000011000000100000010000000010","00000011000000100000010000000001","00000011000000000000011010000001","00000011000000000000011010000010","00000011000000000000010110000001","00000011000000000000010110000010","00000011000000010000010110000001","00000011000000010000010110000010","00000011000000100000010110000001","00000011000000100000010110000010","00000011000000110000010110000001","00000011000000110000010110000010","00000011000000000001111010000001","00000011000000000001 111010000010","0000001 1000000000001111010000011","00000011000000000001111010000100","00000011000000000001111010000101","00000011000000000001111000000001","00000011000000000000000000000000","00000011000000000000000000000000","00000011000000000000000000000000","00000011000000000000000000000000","00000011000000000000000000000000","00000011000000000000000000000000","00000011000000000000000000000000","00000011000000000000000000000000","00000011000000000000000000000000","00000011000000000000000000000000","000000110000000000 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(("00011010","00000000","00000001","00000001","0111000000000000","00000111","00000000","00000000000000000000000000000000"),("00000010","00000000","00000001","00000001","0000110000000000","00000011","00000000","00000000000000000000000000000000"),("00000011","00000000","00000001","00000011","0001000000000000","00000101","00000000","00000000000000000000000000011111"),("00011110","00000000","00000001","00000001","1000000000000000","00000101","00000000","00000000000000000000000000011111"),("00000100", "00000010","00000001","00000101","0011000000000000","00000101","00000000","00000000000000000000000000000011"),("00000101","11000010","00000001","00000100","0010000000000000","00001010","00000000","00000000000000000000000111111111"),("00000110","00000000","00000010","00000001","0100000100000000","00000101","00000000","00000000000000000000000000000011"),("11000001","00000000","00000001","00000001","0101101100000000","00000110","00010000","00000000000000000000000000111100"),("10000000","00000000","0 0000001","00000001","0 000001000000000","00000001","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","00000000000000 00","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000 ","00000000","00000000 000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","000000000000000000000 00000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000") ,("00000000","00000000 ","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000", "00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00011111","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000011000")) IDROMType = 3 SepClocks = true OneWS = true UseIRQLogic = true PWMRefWidth = 13 UseWatchDog = true OffsetToModules = 64 OffsetToPinDesc = 448 ClockHigh = 200000000 ClockMed = 100000000 ClockLow = 100000000 BoardNameLow = "01000001010100110100010101001101" BoardNameHigh = "00111000001110010100100100110111" FPGASize = 9 FPGAPins = 144 IOPorts = 3 IOWidth = 51 LIOWidth = 0 PortWidth = 17 BusWidth = 32 AddrWidth = 16 InstStride0 = 4 InstStride1 = 64 RegStride0 = 256 RegStride1 = 256 LEDCount = 4 INFO:Xst:3210 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\hostmot2.vhd" line 4388: Output port of the instance is unconnected or connected to loadless signal. INFO:Xst:3210 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\hostmot2.vhd" line 4388: Output port of the instance is unconnected or connected to loadless signal. INFO:Xst:3210 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\hostmot2.vhd" line 4388: Output port of the instance is unconnected or connected to loadless signal. WARNING:Xst:2935 - Signal 'AltData<50:32>', unconnected in block 'HostMot2', is tied to its initial value (0000000000000000000). WARNING:Xst:2935 - Signal 'AltData<16:7>', unconnected in block 'HostMot2', is tied to its initial value (0000000000). WARNING:Xst:2935 - Signal 'AltData<5:0>', unconnected in block 'HostMot2', is tied to its initial value (000000). WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. Found 14-bit register for signal . Summary: inferred 14 D-type flip-flop(s). inferred 51 Multiplexer(s). Unit synthesized. Synthesizing Unit . Related source file is "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\hostmotid.vhd". buswidth = 32 cookie = "01010101101010101100101011111110" namelow = "01010100010100110100111101001000" namehigh = "00110010010101000100111101001101" idromoffset = "00000000000000000000010000000000" Found 1-bit tristate buffer for signal > created at line 89 Found 1-bit tristate buffer for signal > created at line 89 Found 1-bit tristate buffer for signal > created at line 89 Found 1-bit tristate buffer for signal > created at line 89 Found 1-bit tristate buffer for signal > created at line 89 Found 1-bit tristate buffer for signal > created at line 89 Found 1-bit tristate buffer for signal > created at line 89 Found 1-bit tristate buffer for signal > created at line 89 Found 1-bit tristate buffer for signal > created at line 89 Found 1-bit tristate buffer for signal > created at line 89 Found 1-bit tristate buffer for signal > created at line 89 Found 1-bit tristate buffer for signal > created at line 89 Found 1-bit tristate buffer for signal > created at line 89 Found 1-bit tristate buffer for signal > created at line 89 Found 1-bit tristate buffer for signal > created at line 89 Found 1-bit tristate buffer for signal > created at line 89 Found 1-bit tristate buffer for signal > created at line 89 Found 1-bit tristate buffer for signal > created at line 89 Found 1-bit tristate buffer for signal > created at line 89 Found 1-bit tristate buffer for signal > created at line 89 Found 1-bit tristate buffer for signal > created at line 89 Found 1-bit tristate buffer for signal > created at line 89 Found 1-bit tristate buffer for signal > created at line 89 Found 1-bit tristate buffer for signal > created at line 89 Found 1-bit tristate buffer for signal > created at line 89 Found 1-bit tristate buffer for signal > created at line 89 Found 1-bit tristate buffer for signal > created at line 89 Found 1-bit tristate buffer for signal > created at line 89 Found 1-bit tristate buffer for signal > created at line 89 Found 1-bit tristate buffer for signal > created at line 89 Found 1-bit tristate buffer for signal > created at line 89 Found 1-bit tristate buffer for signal > created at line 89 Summary: inferred 32 Tristate(s). Unit synthesized. Synthesizing Unit . Related source file is "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\wordpr.vhd". size = 17 buswidth = 32 WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Found 17-bit register for signal . Found 17-bit register for signal . Found 17-bit register for signal . Found 17-bit register for signal . Found 17-bit register for signal . Found 1-bit tristate buffer for signal > created at line 103 Found 1-bit tristate buffer for signal > created at line 103 Found 1-bit tristate buffer for signal > created at line 103 Found 1-bit tristate buffer for signal > created at line 103 Found 1-bit tristate buffer for signal > created at line 103 Found 1-bit tristate buffer for signal > created at line 103 Found 1-bit tristate buffer for signal > created at line 103 Found 1-bit tristate buffer for signal > created at line 103 Found 1-bit tristate buffer for signal > created at line 103 Found 1-bit tristate buffer for signal > created at line 103 Found 1-bit tristate buffer for signal > created at line 103 Found 1-bit tristate buffer for signal > created at line 103 Found 1-bit tristate buffer for signal > created at line 103 Found 1-bit tristate buffer for signal > created at line 103 Found 1-bit tristate buffer for signal > created at line 103 Found 1-bit tristate buffer for signal > created at line 103 Found 1-bit tristate buffer for signal > created at line 103 Found 1-bit tristate buffer for signal > created at line 103 Found 1-bit tristate buffer for signal > created at line 103 Found 1-bit tristate buffer for signal > created at line 103 Found 1-bit tristate buffer for signal > created at line 103 Found 1-bit tristate buffer for signal > created at line 103 Found 1-bit tristate buffer for signal > created at line 103 Found 1-bit tristate buffer for signal > created at line 103 Found 1-bit tristate buffer for signal > created at line 103 Found 1-bit tristate buffer for signal > created at line 103 Found 1-bit tristate buffer for signal > created at line 103 Found 1-bit tristate buffer for signal > created at line 103 Found 1-bit tristate buffer for signal > created at line 103 Found 1-bit tristate buffer for signal > created at line 103 Found 1-bit tristate buffer for signal > created at line 103 Found 1-bit tristate buffer for signal > created at line 103 Found 1-bit tristate buffer for signal > created at line 103 Found 1-bit tristate buffer for signal > created at line 103 Found 1-bit tristate buffer for signal > created at line 103 Found 1-bit tristate buffer for signal > created at line 103 Found 1-bit tristate buffer for signal > created at line 103 Found 1-bit tristate buffer for signal > created at line 103 Found 1-bit tristate buffer for signal > created at line 103 Found 1-bit tristate buffer for signal > created at line 103 Found 1-bit tristate buffer for signal > created at line 103 Found 1-bit tristate buffer for signal > created at line 103 Found 1-bit tristate buffer for signal > created at line 103 Found 1-bit tristate buffer for signal > created at line 103 Found 1-bit tristate buffer for signal > created at line 103 Found 1-bit tristate buffer for signal > created at line 103 Found 1-bit tristate buffer for signal > created at line 103 Found 1-bit tristate buffer for signal > created at line 103 Found 1-bit tristate buffer for signal > created at line 103 Summary: inferred 85 D-type flip-flop(s). inferred 85 Multiplexer(s). inferred 49 Tristate(s). Unit synthesized. Synthesizing Unit . Related source file is "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\wordrb.vhd". size = 17 buswidth = 32 Found 1-bit tristate buffer for signal > created at line 82 Found 1-bit tristate buffer for signal > created at line 82 Found 1-bit tristate buffer for signal > created at line 82 Found 1-bit tristate buffer for signal > created at line 82 Found 1-bit tristate buffer for signal > created at line 82 Found 1-bit tristate buffer for signal > created at line 82 Found 1-bit tristate buffer for signal > created at line 82 Found 1-bit tristate buffer for signal > created at line 82 Found 1-bit tristate buffer for signal > created at line 82 Found 1-bit tristate buffer for signal > created at line 82 Found 1-bit tristate buffer for signal > created at line 82 Found 1-bit tristate buffer for signal > created at line 82 Found 1-bit tristate buffer for signal > created at line 82 Found 1-bit tristate buffer for signal > created at line 82 Found 1-bit tristate buffer for signal > created at line 82 Found 1-bit tristate buffer for signal > created at line 82 Found 1-bit tristate buffer for signal > created at line 82 Found 1-bit tristate buffer for signal > created at line 82 Found 1-bit tristate buffer for signal > created at line 82 Found 1-bit tristate buffer for signal > created at line 82 Found 1-bit tristate buffer for signal > created at line 82 Found 1-bit tristate buffer for signal > created at line 82 Found 1-bit tristate buffer for signal > created at line 82 Found 1-bit tristate buffer for signal > created at line 82 Found 1-bit tristate buffer for signal > created at line 82 Found 1-bit tristate buffer for signal > created at line 82 Found 1-bit tristate buffer for signal > created at line 82 Found 1-bit tristate buffer for signal > created at line 82 Found 1-bit tristate buffer for signal > created at line 82 Found 1-bit tristate buffer for signal > created at line 82 Found 1-bit tristate buffer for signal > created at line 82 Found 1-bit tristate buffer for signal > created at line 82 Summary: inferred 32 Tristate(s). Unit synthesized. Synthesizing Unit . Related source file is "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\watchdog.vhd". buswidth = 32 Found 32-bit register for signal . Found 32-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 32-bit subtractor for signal > created at line 106. Found 1-bit tristate buffer for signal > created at line 97 Found 1-bit tristate buffer for signal > created at line 97 Found 1-bit tristate buffer for signal > created at line 97 Found 1-bit tristate buffer for signal > created at line 97 Found 1-bit tristate buffer for signal > created at line 97 Found 1-bit tristate buffer for signal > created at line 97 Found 1-bit tristate buffer for signal > created at line 97 Found 1-bit tristate buffer for signal > created at line 97 Found 1-bit tristate buffer for signal > created at line 97 Found 1-bit tristate buffer for signal > created at line 97 Found 1-bit tristate buffer for signal > created at line 97 Found 1-bit tristate buffer for signal > created at line 97 Found 1-bit tristate buffer for signal > created at line 97 Found 1-bit tristate buffer for signal > created at line 97 Found 1-bit tristate buffer for signal > created at line 97 Found 1-bit tristate buffer for signal > created at line 97 Found 1-bit tristate buffer for signal > created at line 97 Found 1-bit tristate buffer for signal > created at line 97 Found 1-bit tristate buffer for signal > created at line 97 Found 1-bit tristate buffer for signal > created at line 97 Found 1-bit tristate buffer for signal > created at line 97 Found 1-bit tristate buffer for signal > created at line 97 Found 1-bit tristate buffer for signal > created at line 97 Found 1-bit tristate buffer for signal > created at line 97 Found 1-bit tristate buffer for signal > created at line 97 Found 1-bit tristate buffer for signal > created at line 97 Found 1-bit tristate buffer for signal > created at line 97 Found 1-bit tristate buffer for signal > created at line 97 Found 1-bit tristate buffer for signal > created at line 97 Found 1-bit tristate buffer for signal > created at line 97 Found 1-bit tristate buffer for signal > created at line 97 Found 1-bit tristate buffer for signal > created at line 97 Summary: inferred 1 Adder/Subtractor(s). inferred 67 D-type flip-flop(s). inferred 36 Multiplexer(s). inferred 32 Tristate(s). Unit synthesized. Synthesizing Unit . Related source file is "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\irqlogics.vhd". buswidth = 32 WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Found 5-bit register for signal . Found 2-bit register for signal . Found 1-bit 5-to-1 multiplexer for signal created at line 116. Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Summary: inferred 7 D-type flip-flop(s). inferred 4 Multiplexer(s). inferred 32 Tristate(s). Unit synthesized. Synthesizing Unit . Related source file is "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\hmtimers.vhd". Found 4-bit register for signal . Found 2-bit register for signal . Found 8-bit register for signal . Found 42-bit register for signal . Found 24-bit register for signal . Found 16-bit register for signal . Found 24-bit register for signal . Found 24-bit register for signal . Found 24-bit register for signal . Found 32-bit register for signal . Found 32-bit register for signal . Found 24-bit register for signal . Found 8-bit register for signal . Found 16-bit register for signal . Found 16-bit register for signal . Found 16-bit register for signal . Found 16-bit register for signal . Found 16-bit register for signal . Found 4-bit register for signal . Found 25-bit subtractor for signal created at line 156. Found 42-bit adder for signal created at line 152. Found 24-bit adder for signal created at line 162. Found 24-bit adder for signal created at line 169. Found 24-bit adder for signal created at line 178. Found 24-bit adder for signal created at line 178. Found 16-bit adder for signal created at line 256. Found 16-bit adder for signal created at line 257. Found 16-bit adder for signal created at line 258. Found 16-bit adder for signal created at line 259. Found 4-bit subtractor for signal > created at line 1308. Found 42-bit subtractor for signal > created at line 152. Found 24-bit subtractor for signal created at line 0. Found 16-bit subtractor for signal > created at line 1308. Found 8-bit subtractor for signal > created at line 1308. Found 1-bit tristate buffer for signal > created at line 125 Found 1-bit tristate buffer for signal > created at line 125 Found 1-bit tristate buffer for signal > created at line 125 Found 1-bit tristate buffer for signal > created at line 125 Found 1-bit tristate buffer for signal > created at line 125 Found 1-bit tristate buffer for signal > created at line 125 Found 1-bit tristate buffer for signal > created at line 125 Found 1-bit tristate buffer for signal > created at line 125 Found 1-bit tristate buffer for signal > created at line 125 Found 1-bit tristate buffer for signal > created at line 125 Found 1-bit tristate buffer for signal > created at line 125 Found 1-bit tristate buffer for signal > created at line 125 Found 1-bit tristate buffer for signal > created at line 125 Found 1-bit tristate buffer for signal > created at line 125 Found 1-bit tristate buffer for signal > created at line 125 Found 1-bit tristate buffer for signal > created at line 125 Found 1-bit tristate buffer for signal > created at line 125 Found 1-bit tristate buffer for signal > created at line 125 Found 1-bit tristate buffer for signal > created at line 125 Found 1-bit tristate buffer for signal > created at line 125 Found 1-bit tristate buffer for signal > created at line 125 Found 1-bit tristate buffer for signal > created at line 125 Found 1-bit tristate buffer for signal > created at line 125 Found 1-bit tristate buffer for signal > created at line 125 Found 1-bit tristate buffer for signal > created at line 125 Found 1-bit tristate buffer for signal > created at line 125 Found 1-bit tristate buffer for signal > created at line 125 Found 1-bit tristate buffer for signal > created at line 125 Found 1-bit tristate buffer for signal > created at line 125 Found 1-bit tristate buffer for signal > created at line 125 Found 1-bit tristate buffer for signal > created at line 125 Found 1-bit tristate buffer for signal > created at line 125 Found 24-bit comparator greater for signal created at line 153 Found 24-bit comparator greater for signal created at line 155 WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . HDL ADVISOR - Describing an operational reset or an explicit power-up state for register would allow inference of a finite state machine and as consequence better performance and smaller area. Summary: inferred 15 Adder/Subtractor(s). inferred 348 D-type flip-flop(s). inferred 2 Comparator(s). inferred 198 Multiplexer(s). inferred 32 Tristate(s). Unit synthesized. Synthesizing Unit . Related source file is "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\ubrategend.vhd". Found 1-bit register for signal . Found 1-bit register for signal . Found 32-bit register for signal . Found 4-bit register for signal . Found 33-bit register for signal . Found 33-bit adder for signal created at line 100. Found 1-bit 7-to-1 multiplexer for signal created at line 129. Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Summary: inferred 1 Adder/Subtractor(s). inferred 71 D-type flip-flop(s). inferred 33 Multiplexer(s). inferred 32 Tristate(s). Unit synthesized. Synthesizing Unit . Related source file is "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\kubstepgenzid.vhd". buswidth = 32 timersize = 14 tablewidth = 2 asize = 48 rsize = 32 lsize = 24 WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Found 1-bit register for signal . Found 14-bit register for signal . Found 1-bit register for signal . Found 14-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 4-bit register for signal . Found 8-bit register for signal . Found 32-bit register for signal . Found 1-bit register for signal . Found 14-bit register for signal . Found 14-bit register for signal . Found 14-bit register for signal . Found 14-bit register for signal . Found 4-bit register for signal . Found 32-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 8-bit register for signal . Found 2-bit register for signal . Found 8-bit register for signal . Found 2-bit register for signal . Found 24-bit register for signal . Found 48-bit register for signal . Found 4-bit adder for signal created at line 245. Found 8-bit adder for signal created at line 293. Found 8-bit adder for signal created at line 310. Found 48-bit adder for signal created at line 351. Found 14-bit subtractor for signal > created at line 212. Found 14-bit subtractor for signal > created at line 221. Found 4-bit subtractor for signal > created at line 252. Found 8-bit subtractor for signal > created at line 297. Found 8-bit subtractor for signal > created at line 314. Found 4x2-bit Read Only RAM for signal Found 2-bit 4-to-1 multiplexer for signal created at line 417. Found 1-bit tristate buffer for signal > created at line 199 Found 1-bit tristate buffer for signal > created at line 199 Found 1-bit tristate buffer for signal > created at line 199 Found 1-bit tristate buffer for signal > created at line 199 Found 1-bit tristate buffer for signal > created at line 199 Found 1-bit tristate buffer for signal > created at line 199 Found 1-bit tristate buffer for signal > created at line 199 Found 1-bit tristate buffer for signal > created at line 199 Found 1-bit tristate buffer for signal > created at line 199 Found 1-bit tristate buffer for signal > created at line 199 Found 1-bit tristate buffer for signal > created at line 199 Found 1-bit tristate buffer for signal > created at line 199 Found 1-bit tristate buffer for signal > created at line 199 Found 1-bit tristate buffer for signal > created at line 199 Found 1-bit tristate buffer for signal > created at line 199 Found 1-bit tristate buffer for signal > created at line 199 Found 1-bit tristate buffer for signal > created at line 199 Found 1-bit tristate buffer for signal > created at line 199 Found 1-bit tristate buffer for signal > created at line 199 Found 1-bit tristate buffer for signal > created at line 199 Found 1-bit tristate buffer for signal > created at line 199 Found 1-bit tristate buffer for signal > created at line 199 Found 1-bit tristate buffer for signal > created at line 199 Found 1-bit tristate buffer for signal > created at line 199 Found 1-bit tristate buffer for signal > created at line 199 Found 1-bit tristate buffer for signal > created at line 199 Found 1-bit tristate buffer for signal > created at line 199 Found 1-bit tristate buffer for signal > created at line 199 Found 1-bit tristate buffer for signal > created at line 199 Found 1-bit tristate buffer for signal > created at line 199 Found 1-bit tristate buffer for signal > created at line 199 Found 1-bit tristate buffer for signal > created at line 199 Found 4-bit comparator equal for signal created at line 242 Summary: inferred 1 RAM(s). inferred 6 Adder/Subtractor(s). inferred 263 D-type flip-flop(s). inferred 1 Comparator(s). inferred 83 Multiplexer(s). inferred 32 Tristate(s). Unit synthesized. Synthesizing Unit . Related source file is "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\qcounterated.vhd". clock = 100000000 WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Found 12-bit register for signal . Found 4-bit register for signal . Found 12-bit register for signal . Found 12-bit subtractor for signal > created at line 99. Found 1-bit 7-to-1 multiplexer for signal created at line 119. Found 1-bit tristate buffer for signal > created at line 94 Found 1-bit tristate buffer for signal > created at line 94 Found 1-bit tristate buffer for signal > created at line 94 Found 1-bit tristate buffer for signal > created at line 94 Found 1-bit tristate buffer for signal > created at line 94 Found 1-bit tristate buffer for signal > created at line 94 Found 1-bit tristate buffer for signal > created at line 94 Found 1-bit tristate buffer for signal > created at line 94 Found 1-bit tristate buffer for signal > created at line 94 Found 1-bit tristate buffer for signal > created at line 94 Found 1-bit tristate buffer for signal > created at line 94 Found 1-bit tristate buffer for signal > created at line 94 Found 1-bit tristate buffer for signal > created at line 94 Found 1-bit tristate buffer for signal > created at line 94 Found 1-bit tristate buffer for signal > created at line 94 Found 1-bit tristate buffer for signal > created at line 94 Found 1-bit tristate buffer for signal > created at line 94 Found 1-bit tristate buffer for signal > created at line 94 Found 1-bit tristate buffer for signal > created at line 94 Found 1-bit tristate buffer for signal > created at line 94 Found 1-bit tristate buffer for signal > created at line 94 Found 1-bit tristate buffer for signal > created at line 94 Found 1-bit tristate buffer for signal > created at line 94 Found 1-bit tristate buffer for signal > created at line 94 Found 1-bit tristate buffer for signal > created at line 94 Found 1-bit tristate buffer for signal > created at line 94 Found 1-bit tristate buffer for signal > created at line 94 Found 1-bit tristate buffer for signal > created at line 94 Found 1-bit tristate buffer for signal > created at line 94 Found 1-bit tristate buffer for signal > created at line 94 Found 1-bit tristate buffer for signal > created at line 94 Found 1-bit tristate buffer for signal > created at line 94 Summary: inferred 1 Adder/Subtractor(s). inferred 28 D-type flip-flop(s). inferred 2 Multiplexer(s). inferred 32 Tristate(s). Unit synthesized. Synthesizing Unit . Related source file is "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\timestampd.vhd". Found 16-bit register for signal . Found 16-bit register for signal . Found 16-bit register for signal . Found 1-bit register for signal . Found 16-bit register for signal
. Found 16-bit adder for signal created at line 102. Found 16-bit subtractor for signal > created at line 99. Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Found 1-bit tristate buffer for signal > created at line 96 Summary: inferred 2 Adder/Subtractor(s). inferred 65 D-type flip-flop(s). inferred 17 Multiplexer(s). inferred 16 Tristate(s). Unit synthesized. Synthesizing Unit . Related source file is "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\qcountersfd.vhd". buswidth = 32 WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 4-bit register for signal . Found 1-bit register for signal . Found 4-bit register for signal . Found 1-bit register for signal . Found 4-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 16-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 16-bit register for signal . Found 16-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 32-bit register for signal . Found 1-bit register for signal >. Found 1-bit register for signal >. Found 1-bit register for signal >. Found 1-bit register for signal >. Found 1-bit register for signal >. Found 1-bit register for signal >. Found 1-bit register for signal >. Found 1-bit register for signal >. Found 1-bit register for signal >. Found 1-bit register for signal >. Found 1-bit register for signal >. Found 1-bit register for signal >. Found 1-bit register for signal >. Found 1-bit register for signal >. Found 1-bit register for signal >. Found 1-bit register for signal >. Found 1-bit register for signal >. Found 1-bit register for signal >. Found 1-bit register for signal >. Found 1-bit register for signal >. Found 1-bit register for signal >. Found 1-bit register for signal >. Found 1-bit register for signal >. Found 1-bit register for signal >. Found 1-bit register for signal >. Found 1-bit register for signal >. Found 1-bit register for signal >. Found 1-bit register for signal >. Found 1-bit register for signal >. Found 1-bit register for signal >. Found 1-bit register for signal . Found 1-bit register for signal . Found 4-bit adder for signal created at line 241. Found 4-bit adder for signal created at line 255. Found 4-bit adder for signal created at line 269. Found 16-bit adder for signal created at line 311. Found 4-bit subtractor for signal > created at line 244. Found 4-bit subtractor for signal > created at line 258. Found 4-bit subtractor for signal > created at line 272. Found 16-bit subtractor for signal > created at line 313. Found 1-bit tristate buffer for signal > created at line 142 Found 1-bit tristate buffer for signal > created at line 142 Found 1-bit tristate buffer for signal > created at line 142 Found 1-bit tristate buffer for signal > created at line 142 Found 1-bit tristate buffer for signal > created at line 142 Found 1-bit tristate buffer for signal > created at line 142 Found 1-bit tristate buffer for signal > created at line 142 Found 1-bit tristate buffer for signal > created at line 142 Found 1-bit tristate buffer for signal > created at line 142 Found 1-bit tristate buffer for signal > created at line 142 Found 1-bit tristate buffer for signal > created at line 142 Found 1-bit tristate buffer for signal > created at line 142 Found 1-bit tristate buffer for signal > created at line 142 Found 1-bit tristate buffer for signal > created at line 142 Found 1-bit tristate buffer for signal > created at line 142 Found 1-bit tristate buffer for signal > created at line 142 Found 1-bit tristate buffer for signal > created at line 142 Found 1-bit tristate buffer for signal > created at line 142 Found 1-bit tristate buffer for signal > created at line 142 Found 1-bit tristate buffer for signal > created at line 142 Found 1-bit tristate buffer for signal > created at line 142 Found 1-bit tristate buffer for signal > created at line 142 Found 1-bit tristate buffer for signal > created at line 142 Found 1-bit tristate buffer for signal > created at line 142 Found 1-bit tristate buffer for signal > created at line 142 Found 1-bit tristate buffer for signal > created at line 142 Found 1-bit tristate buffer for signal > created at line 142 Found 1-bit tristate buffer for signal > created at line 142 Found 1-bit tristate buffer for signal > created at line 142 Found 1-bit tristate buffer for signal > created at line 142 Found 1-bit tristate buffer for signal > created at line 142 Found 1-bit tristate buffer for signal > created at line 142 Found 4-bit comparator greater for signal created at line 240 Found 4-bit comparator greater for signal created at line 254 Found 4-bit comparator greater for signal created at line 268 Summary: inferred 4 Adder/Subtractor(s). inferred 147 D-type flip-flop(s). inferred 3 Comparator(s). inferred 40 Multiplexer(s). inferred 32 Tristate(s). Unit synthesized. Synthesizing Unit . Related source file is "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\pwmrefh.vhd". buswidth = 16 refwidth = 13 Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 17-bit register for signal . Found 1-bit register for signal . Found 13-bit register for signal . Found 16-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 17-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 16-bit register for signal . Found 16-bit register for signal . Found 16-bit register for signal . Found 17-bit adder for signal created at line 124. Found 13-bit adder for signal created at line 127. Found 17-bit adder for signal created at line 136. Summary: inferred 3 Adder/Subtractor(s). inferred 120 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\pwmpdmgenh.vhd". buswidth = 32 refwidth = 13 WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Found 1-bit register for signal . Found 1-bit register for signal . Found 12-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 6-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 12-bit register for signal . Found 1-bit register for signal . Found 12-bit register for signal . Found 1-bit register for signal . Found 6-bit register for signal . Found 13-bit register for signal . Found 13-bit adder for signal created at line 126. Found 4x12-bit Read Only RAM for signal Found 1-bit 4-to-1 multiplexer for signal created at line 172. Found 1-bit 4-to-1 multiplexer for signal created at line 211. Found 1-bit 4-to-1 multiplexer for signal created at line 211. Found 12-bit comparator greater for signal created at line 146 Summary: inferred 1 RAM(s). inferred 1 Adder/Subtractor(s). inferred 71 D-type flip-flop(s). inferred 1 Comparator(s). inferred 8 Multiplexer(s). Unit synthesized. Synthesizing Unit . Related source file is "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\inmuxm.vhd". buswidth = 32 muxwidth = 24 WARNING:Xst:2935 - Signal 'controlreg<4:0>', unconnected in block 'inmuxm', is tied to its initial value (10111). Found 1-bit register for signal . Found 3-bit register for signal . Found 1-bit register for signal . Found 10-bit register for signal . Found 32-bit register for signal . Found 1-bit register for signal . Found 24-bit register for signal . Found 24-bit register for signal . Found 5-bit register for signal . Found 1-bit register for signal >. Found 1-bit register for signal >. Found 1-bit register for signal >. Found 1-bit register for signal >. Found 1-bit register for signal >. Found 1-bit register for signal >. Found 1-bit register for signal >. Found 1-bit register for signal >. Found 1-bit register for signal >. Found 1-bit register for signal >. Found 1-bit register for signal >. Found 1-bit register for signal >. Found 1-bit register for signal >. Found 1-bit register for signal >. Found 1-bit register for signal >. Found 1-bit register for signal >. Found 1-bit register for signal >. Found 1-bit register for signal >. Found 1-bit register for signal >. Found 1-bit register for signal >. Found 1-bit register for signal >. Found 1-bit register for signal >. Found 1-bit register for signal >. Found 1-bit register for signal >. Found 1-bit register for signal >. Found 1-bit register for signal >. Found 1-bit register for signal >. Found 24-bit register for signal . Found 4-bit register for signal . Found 8-bit register for signal . Found 8-bit register for signal >. Found 8-bit register for signal >. Found 8-bit register for signal >. Found 8-bit register for signal >. Found 2-bit register for signal . Found 2-bit adder for signal created at line 130. Found 3-bit adder for signal created at line 134. Found 10-bit adder for signal created at line 159. Found 8-bit adder for signal created at line 217. Found 8-bit adder for signal created at line 217. Found 8-bit adder for signal created at line 217. Found 8-bit adder for signal created at line 217. Found 3-bit subtractor for signal > created at line 138. Found 10-bit subtractor for signal > created at line 150. Found 10-bit subtractor for signal > created at line 174. Found 5-bit subtractor for signal > created at line 183. Found 8-bit subtractor for signal > created at line 223. Found 8-bit subtractor for signal > created at line 223. Found 8-bit subtractor for signal > created at line 223. Found 8-bit subtractor for signal > created at line 223. WARNING:Xst:3035 - Index value(s) does not match array range for signal , simulation mismatch. Found 24x10-bit single-port RAM for signal . Found 1-bit 24-to-1 multiplexer for signal created at line 156. Found 1-bit 24-to-1 multiplexer for signal created at line 157. Found 1-bit tristate buffer for signal > created at line 125 Found 1-bit tristate buffer for signal > created at line 125 Found 1-bit tristate buffer for signal > created at line 125 Found 1-bit tristate buffer for signal > created at line 125 Found 1-bit tristate buffer for signal > created at line 125 Found 1-bit tristate buffer for signal > created at line 125 Found 1-bit tristate buffer for signal > created at line 125 Found 1-bit tristate buffer for signal > created at line 125 Found 1-bit tristate buffer for signal > created at line 125 Found 1-bit tristate buffer for signal > created at line 125 Found 1-bit tristate buffer for signal > created at line 125 Found 1-bit tristate buffer for signal > created at line 125 Found 1-bit tristate buffer for signal > created at line 125 Found 1-bit tristate buffer for signal > created at line 125 Found 1-bit tristate buffer for signal > created at line 125 Found 1-bit tristate buffer for signal > created at line 125 Found 1-bit tristate buffer for signal > created at line 125 Found 1-bit tristate buffer for signal > created at line 125 Found 1-bit tristate buffer for signal > created at line 125 Found 1-bit tristate buffer for signal > created at line 125 Found 1-bit tristate buffer for signal > created at line 125 Found 1-bit tristate buffer for signal > created at line 125 Found 1-bit tristate buffer for signal > created at line 125 Found 1-bit tristate buffer for signal > created at line 125 Found 1-bit tristate buffer for signal > created at line 125 Found 1-bit tristate buffer for signal > created at line 125 Found 1-bit tristate buffer for signal > created at line 125 Found 1-bit tristate buffer for signal > created at line 125 Found 1-bit tristate buffer for signal > created at line 125 Found 1-bit tristate buffer for signal > created at line 125 Found 1-bit tristate buffer for signal > created at line 125 Found 1-bit tristate buffer for signal > created at line 125 Found 3-bit comparator lessequal for signal created at line 133 Found 10-bit comparator greater for signal created at line 158 Found 10-bit comparator not equal for signal created at line 161 Found 10-bit comparator greater for signal created at line 165 Found 10-bit comparator greater for signal created at line 173 Summary: inferred 1 RAM(s). inferred 14 Adder/Subtractor(s). inferred 198 D-type flip-flop(s). inferred 5 Comparator(s). inferred 228 Multiplexer(s). inferred 32 Tristate(s). Unit synthesized. Synthesizing Unit . Related source file is "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\sserialwa.vhd". Ports = 1 InterfaceRegs = 1 BaseClock = 100000000 NeedCRC8 = true INFO:Xst:3210 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\sserialwa.vhd" line 266: Output port of the instance is unconnected or connected to loadless signal. INFO:Xst:3210 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\sserialwa.vhd" line 293: Output port of the instance is unconnected or connected to loadless signal. INFO:Xst:3210 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\sserialwa.vhd" line 309: Output port of the instance is unconnected or connected to loadless signal. INFO:Xst:3210 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\sserialwa.vhd" line 324: Output port of the instance is unconnected or connected to loadless signal. INFO:Xst:3210 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\sserialwa.vhd" line 339: Output port of the instance is unconnected or connected to loadless signal. INFO:Xst:3210 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\sserialwa.vhd" line 354: Output port of the instance is unconnected or connected to loadless signal. INFO:Xst:3210 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\sserialwa.vhd" line 369: Output port of the instance is unconnected or connected to loadless signal. INFO:Xst:3210 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\sserialwa.vhd" line 384: Output port of the instance is unconnected or connected to loadless signal. INFO:Xst:3210 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\sserialwa.vhd" line 399: Output port of the instance is unconnected or connected to loadless signal. INFO:Xst:3210 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\sserialwa.vhd" line 414: Output port of the instance is unconnected or connected to loadless signal. INFO:Xst:3210 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\sserialwa.vhd" line 430: Output port of the instance is unconnected or connected to loadless signal. INFO:Xst:3210 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\sserialwa.vhd" line 457: Output port of the instance is unconnected or connected to loadless signal. Found 1-bit register for signal . Found 1-bit register for signal . Found 16-bit register for signal . Found 1-bit register for signal . Found 16-bit register for signal . Found 8-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 8-bit register for signal . Found 1-bit register for signal . Found 24-bit register for signal . Found 24-bit register for signal . Found 16-bit register for signal . Found 16-bit register for signal . Found 8-bit register for signal . Found 16-bit register for signal . Found 8-bit register for signal . Found 12-bit register for signal . Found 16-bit adder for signal created at line 686. Found 16-bit subtractor for signal > created at line 681. Found 4x8-bit Read Only RAM for signal Found 24-bit 4-to-1 multiplexer for signal created at line 612. Found 24-bit 4-to-1 multiplexer for signal created at line 620. Found 1-bit 4-to-1 multiplexer for signal created at line 649. Found 1-bit 4-to-1 multiplexer for signal created at line 649. Found 1-bit 4-to-1 multiplexer for signal created at line 649. Found 1-bit 4-to-1 multiplexer for signal created at line 649. Found 1-bit 4-to-1 multiplexer for signal created at line 649. Found 1-bit 4-to-1 multiplexer for signal created at line 649. Found 1-bit 4-to-1 multiplexer for signal created at line 649. Found 1-bit 4-to-1 multiplexer for signal created at line 649. Found 1-bit 4-to-1 multiplexer for signal > created at line 649. Found 1-bit 4-to-1 multiplexer for signal > created at line 649. Found 1-bit 4-to-1 multiplexer for signal > created at line 649. Found 1-bit 4-to-1 multiplexer for signal > created at line 649. Found 1-bit 4-to-1 multiplexer for signal > created at line 649. Found 1-bit 4-to-1 multiplexer for signal > created at line 649. Found 1-bit 4-to-1 multiplexer for signal > created at line 649. Found 1-bit 4-to-1 multiplexer for signal > created at line 649. Found 1-bit tristate buffer for signal > created at line 498 Found 1-bit tristate buffer for signal > created at line 498 Found 1-bit tristate buffer for signal > created at line 498 Found 1-bit tristate buffer for signal > created at line 498 Found 1-bit tristate buffer for signal > created at line 498 Found 1-bit tristate buffer for signal > created at line 498 Found 1-bit tristate buffer for signal > created at line 498 Found 1-bit tristate buffer for signal > created at line 498 Found 1-bit tristate buffer for signal > created at line 498 Found 1-bit tristate buffer for signal > created at line 498 Found 1-bit tristate buffer for signal > created at line 498 Found 1-bit tristate buffer for signal > created at line 498 Found 1-bit tristate buffer for signal > created at line 498 Found 1-bit tristate buffer for signal > created at line 498 Found 1-bit tristate buffer for signal > created at line 498 Found 1-bit tristate buffer for signal > created at line 498 Found 1-bit tristate buffer for signal > created at line 498 Found 1-bit tristate buffer for signal > created at line 498 Found 1-bit tristate buffer for signal > created at line 498 Found 1-bit tristate buffer for signal > created at line 498 Found 1-bit tristate buffer for signal > created at line 498 Found 1-bit tristate buffer for signal > created at line 498 Found 1-bit tristate buffer for signal > created at line 498 Found 1-bit tristate buffer for signal > created at line 498 Found 1-bit tristate buffer for signal > created at line 498 Found 1-bit tristate buffer for signal > created at line 498 Found 1-bit tristate buffer for signal > created at line 498 Found 1-bit tristate buffer for signal > created at line 498 Found 1-bit tristate buffer for signal > created at line 498 Found 1-bit tristate buffer for signal > created at line 498 Found 1-bit tristate buffer for signal > created at line 498 Found 1-bit tristate buffer for signal > created at line 498 Found 1-bit tristate buffer for signal > created at line 498 Found 1-bit tristate buffer for signal > created at line 498 Found 1-bit tristate buffer for signal > created at line 498 Found 1-bit tristate buffer for signal > created at line 498 Found 1-bit tristate buffer for signal > created at line 498 Found 1-bit tristate buffer for signal > created at line 498 Found 1-bit tristate buffer for signal > created at line 498 Found 1-bit tristate buffer for signal > created at line 498 Found 1-bit tristate buffer for signal > created at line 601 Found 1-bit tristate buffer for signal > created at line 601 Found 1-bit tristate buffer for signal > created at line 601 Found 1-bit tristate buffer for signal > created at line 601 Found 1-bit tristate buffer for signal > created at line 601 Found 1-bit tristate buffer for signal > created at line 601 Found 1-bit tristate buffer for signal > created at line 601 Found 1-bit tristate buffer for signal > created at line 601 Found 1-bit tristate buffer for signal > created at line 601 Found 1-bit tristate buffer for signal > created at line 601 Found 1-bit tristate buffer for signal > created at line 601 Found 1-bit tristate buffer for signal > created at line 601 Found 1-bit tristate buffer for signal > created at line 601 Found 1-bit tristate buffer for signal > created at line 601 Found 1-bit tristate buffer for signal > created at line 601 Found 1-bit tristate buffer for signal > created at line 601 Found 1-bit tristate buffer for signal > created at line 601 Found 1-bit tristate buffer for signal > created at line 601 Found 1-bit tristate buffer for signal > created at line 601 Found 1-bit tristate buffer for signal > created at line 601 Found 1-bit tristate buffer for signal > created at line 601 Found 1-bit tristate buffer for signal > created at line 601 Found 1-bit tristate buffer for signal > created at line 601 Found 1-bit tristate buffer for signal > created at line 601 Found 1-bit tristate buffer for signal > created at line 601 Found 1-bit tristate buffer for signal > created at line 601 Found 1-bit tristate buffer for signal > created at line 601 Found 1-bit tristate buffer for signal > created at line 601 Found 1-bit tristate buffer for signal > created at line 601 Found 1-bit tristate buffer for signal > created at line 601 Found 1-bit tristate buffer for signal > created at line 601 Found 1-bit tristate buffer for signal > created at line 601 Found 1-bit tristate buffer for signal > created at line 601 Found 1-bit tristate buffer for signal > created at line 601 Found 1-bit tristate buffer for signal > created at line 601 Found 1-bit tristate buffer for signal > created at line 601 Found 1-bit tristate buffer for signal > created at line 601 Found 1-bit tristate buffer for signal > created at line 601 Found 1-bit tristate buffer for signal > created at line 601 Found 1-bit tristate buffer for signal > created at line 601 Found 1-bit tristate buffer for signal > created at line 671 Found 1-bit tristate buffer for signal > created at line 671 Found 1-bit tristate buffer for signal > created at line 671 Found 1-bit tristate buffer for signal > created at line 671 Found 1-bit tristate buffer for signal > created at line 671 Found 1-bit tristate buffer for signal > created at line 671 Found 1-bit tristate buffer for signal > created at line 671 Found 1-bit tristate buffer for signal > created at line 671 Found 1-bit tristate buffer for signal > created at line 700 Found 1-bit tristate buffer for signal > created at line 700 Found 1-bit tristate buffer for signal > created at line 700 Found 1-bit tristate buffer for signal > created at line 700 Found 1-bit tristate buffer for signal > created at line 700 Found 1-bit tristate buffer for signal > created at line 700 Found 1-bit tristate buffer for signal > created at line 700 Found 1-bit tristate buffer for signal > created at line 700 Found 1-bit tristate buffer for signal > created at line 715 Found 1-bit tristate buffer for signal > created at line 715 Found 1-bit tristate buffer for signal > created at line 715 Found 1-bit tristate buffer for signal > created at line 715 Found 1-bit tristate buffer for signal > created at line 715 Found 1-bit tristate buffer for signal > created at line 715 Found 1-bit tristate buffer for signal > created at line 715 Found 1-bit tristate buffer for signal > created at line 715 Found 1-bit tristate buffer for signal > created at line 724 Found 1-bit tristate buffer for signal > created at line 724 Found 1-bit tristate buffer for signal > created at line 724 Found 1-bit tristate buffer for signal > created at line 724 Found 1-bit tristate buffer for signal > created at line 724 Found 1-bit tristate buffer for signal > created at line 724 Found 1-bit tristate buffer for signal > created at line 724 Found 1-bit tristate buffer for signal > created at line 724 Summary: inferred 1 RAM(s). inferred 2 Adder/Subtractor(s). inferred 182 D-type flip-flop(s). inferred 207 Multiplexer(s). inferred 112 Tristate(s). Unit synthesized. Synthesizing Unit . Related source file is "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\d8o8sqws.vhd". width = 8 iwidth = 16 maddwidth = 12 paddwidth = 11 INFO:Xst:3210 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\d8o8sqws.vhd" line 277: Output port of the instance is unconnected or connected to loadless signal. Found 16-bit register for signal . Found 16-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 4-bit register for signal . Found 12-bit register for signal . Found 12-bit register for signal . Found 12-bit register for signal . Found 1-bit register for signal . Found 8-bit register for signal . Found 9-bit register for signal . Found 4-bit register for signal . Found 12-bit register for signal . Found 12-bit register for signal . Found 12-bit register for signal . Found 12-bit register for signal . Found 11-bit register for signal . Found 11-bit adder for signal created at line 296. Found 12-bit adder for signal created at line 357. Found 9-bit adder for signal created at line 453. Found 9-bit adder for signal created at line 453. Found 4-bit adder for signal created at line 460. Found 9-bit subtractor for signal > created at line 455. Found 9-bit subtractor for signal > created at line 455. Found 4-bit subtractor for signal created at line 252. Found 12-bit 4-to-1 multiplexer for signal created at line 346. Summary: inferred 6 Adder/Subtractor(s). inferred 155 D-type flip-flop(s). inferred 95 Multiplexer(s). Unit synthesized. Synthesizing Unit . Related source file is "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\adpram.vhd". width = 11 depth = 16 Found 16x11-bit dual-port RAM for signal . Summary: inferred 2 RAM(s). Unit synthesized. Synthesizing Unit . Related source file is "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\sslbprom43.vhd". Found 11-bit register for signal . Found 11-bit register for signal . Found 2048x16-bit dual-port RAM for signal . Summary: inferred 2 RAM(s). inferred 22 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\sslbpram.vhd". Found 10-bit register for signal . Found 10-bit register for signal . Found 1024x8-bit dual-port RAM for signal . Summary: inferred 2 RAM(s). inferred 20 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\adpram.vhd". width = 32 depth = 1 Found 32-bit register for signal >. Summary: inferred 32 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\uartr8.vhd". clock = 100000000 Found 4-bit register for signal . Found 1-bit register for signal . Found 2-bit register for signal . Found 8-bit register for signal . Found 1-bit register for signal . Found 20-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 4-bit register for signal . Found 10-bit register for signal . Found 4-bit register for signal . Found 1-bit register for signal . Found 20-bit register for signal . Found 8-bit register for signal . Found 5-bit register for signal . Found 5-bit adder for signal created at line 177. Found 4-bit adder for signal created at line 178. Found 8-bit adder for signal created at line 213. Found 20-bit adder for signal created at line 226. Found 5-bit subtractor for signal > created at line 182. Found 4-bit subtractor for signal > created at line 183. Found 8-bit subtractor for signal > created at line 216. Found 4-bit subtractor for signal > created at line 245. Found 1-bit tristate buffer for signal > created at line 201 Found 1-bit tristate buffer for signal > created at line 201 Found 1-bit tristate buffer for signal > created at line 201 Found 1-bit tristate buffer for signal > created at line 201 Found 1-bit tristate buffer for signal > created at line 201 Found 1-bit tristate buffer for signal > created at line 201 Found 1-bit tristate buffer for signal > created at line 201 Found 1-bit tristate buffer for signal > created at line 201 Found 8-bit comparator greater for signal created at line 212 Summary: inferred 5 Adder/Subtractor(s). inferred 90 D-type flip-flop(s). inferred 1 Comparator(s). inferred 43 Multiplexer(s). inferred 8 Tristate(s). Unit synthesized. Synthesizing Unit . Related source file is "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\uartx8.vhd". Found 4-bit register for signal . Found 20-bit register for signal . Found 11-bit register for signal . Found 4-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 4-bit register for signal . Found 1-bit register for signal . Found 20-bit register for signal . Found 6-bit register for signal . Found 5-bit register for signal . Found 5-bit adder for signal created at line 172. Found 4-bit adder for signal created at line 173. Found 5-bit subtractor for signal > created at line 178. Found 4-bit subtractor for signal > created at line 179. Found 20-bit subtractor for signal > created at line 207. Found 4-bit subtractor for signal > created at line 210. Found 4-bit subtractor for signal > created at line 241. Found 1-bit tristate buffer for signal > created at line 199 Found 1-bit tristate buffer for signal > created at line 199 Found 1-bit tristate buffer for signal > created at line 199 Found 1-bit tristate buffer for signal > created at line 199 Found 1-bit tristate buffer for signal > created at line 199 Found 1-bit tristate buffer for signal > created at line 199 Found 1-bit tristate buffer for signal > created at line 199 Found 1-bit tristate buffer for signal > created at line 199 Summary: inferred 5 Adder/Subtractor(s). inferred 77 D-type flip-flop(s). inferred 33 Multiplexer(s). inferred 8 Tristate(s). Unit synthesized. Synthesizing Unit . Related source file is "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\boutreg.vhd". size = 4 buswidth = 4 invert = true Found 4-bit register for signal . Found 1-bit tristate buffer for signal > created at line 93 Found 1-bit tristate buffer for signal > created at line 93 Found 1-bit tristate buffer for signal > created at line 93 Found 1-bit tristate buffer for signal > created at line 93 Summary: inferred 4 D-type flip-flop(s). inferred 4 Tristate(s). Unit synthesized. Synthesizing Unit . Related source file is "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\boutreg.vhd". size = 1 buswidth = 32 invert = false WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Found 1-bit register for signal . Found 1-bit tristate buffer for signal > created at line 93 Found 1-bit tristate buffer for signal > created at line 93 Found 1-bit tristate buffer for signal > created at line 93 Found 1-bit tristate buffer for signal > created at line 93 Found 1-bit tristate buffer for signal > created at line 93 Found 1-bit tristate buffer for signal > created at line 93 Found 1-bit tristate buffer for signal > created at line 93 Found 1-bit tristate buffer for signal > created at line 93 Found 1-bit tristate buffer for signal > created at line 93 Found 1-bit tristate buffer for signal > created at line 93 Found 1-bit tristate buffer for signal > created at line 93 Found 1-bit tristate buffer for signal > created at line 93 Found 1-bit tristate buffer for signal > created at line 93 Found 1-bit tristate buffer for signal > created at line 93 Found 1-bit tristate buffer for signal > created at line 93 Found 1-bit tristate buffer for signal > created at line 93 Found 1-bit tristate buffer for signal > created at line 93 Found 1-bit tristate buffer for signal > created at line 93 Found 1-bit tristate buffer for signal > created at line 93 Found 1-bit tristate buffer for signal > created at line 93 Found 1-bit tristate buffer for signal > created at line 93 Found 1-bit tristate buffer for signal > created at line 93 Found 1-bit tristate buffer for signal > created at line 93 Found 1-bit tristate buffer for signal > created at line 93 Found 1-bit tristate buffer for signal > created at line 93 Found 1-bit tristate buffer for signal > created at line 93 Found 1-bit tristate buffer for signal > created at line 93 Found 1-bit tristate buffer for signal > created at line 93 Found 1-bit tristate buffer for signal > created at line 93 Found 1-bit tristate buffer for signal > created at line 93 Found 1-bit tristate buffer for signal > created at line 93 Found 1-bit tristate buffer for signal > created at line 93 Summary: inferred 1 D-type flip-flop(s). inferred 32 Tristate(s). Unit synthesized. Synthesizing Unit . Related source file is "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\idrom.vhd". idromtype = 3 offsettomodules = 64 offsettopindesc = 448 boardnamelow = "01000001010100110100010101001101" boardnamehigh = "00111000001110010100100100110111" fpgasize = 9 fpgapins = 144 ioports = 3 iowidth = 51 portwidth = 17 clocklow = 100000000 clockhigh = 200000000 inststride0 = 4 inststride1 = 64 regstride0 = 256 regstride1 = 256 pindesc = ("00000011000000010000010000000001","00000011000000010000010000000110","00000011000000010000010000000010","00000011000001000000010000000011","00000011000000001100000100000001","00000011000001000000010000000010","00000011000000001100000110000001","00000011000001000000010000000001","00000011000000000000010000000001","00000011000000000000010000000010","00000011000000000000010000000110","00000011000000110000010000000011","00000011000000110000010000000010","00000011000000110000010000000001","000000110 00000100000010000000011","00000011000000100000010000000010","00000011000000100000010000000001","00000011000000000000011010000001","00000011000000000000011010000010","00000011000000000000010110000001","00000011000000000000010110000010","00000011000000010000010110000001","00000011000000010000010110000010","00000011000000100000010110000001","00000011000000100000010110000010","00000011000000110000010110000001","00000011000000110000010110000010","00000011000000000001111010000001","00000011000000000001 111010000010","0000001 1000000000001111010000011","00000011000000000001111010000100","00000011000000000001111010000101","00000011000000000001111000000001","00000011000000000000000000000000","00000011000000000000000000000000","00000011000000000000000000000000","00000011000000000000000000000000","00000011000000000000000000000000","00000011000000000000000000000000","00000011000000000000000000000000","00000011000000000000000000000000","00000011000000000000000000000000","00000011000000000000000000000000","000000110000000000 00000000000000","00000011000000000000000000000000","00000011000000000000000000000000","00000011000000000000000000000000","00000011000000000000000000000000","00000011000000000000000000000000","00000011000000000000000000000000","00000011000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000 000","0000000000000000 0000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","000000000000000000000000000 00000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","000 0000000000000000000000 0000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","0 0000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","000000000000 00000000000000000000", "00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","0000000000 0000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000") moduleid = (("00011010","00000000","00000001","00000001","0111000000000000","00000111","00000000","00000000000000000000000000000000"),("00000010","00000000","00000001","00000001","0000110000000000","00000011","00000000","00000000000000000000000000000000"),("00000011","00000000","00000001","00000011","0001000000000000","00000101","00000000","00000000000000000000000000011111"),("00011110","00000000","00000001","00000001","1000000000000000","00000101","00000000","00000000000000000000000000011111"),("00000100", "00000010","00000001","00000101","0011000000000000","00000101","00000000","00000000000000000000000000000011"),("00000101","11000010","00000001","00000100","0010000000000000","00001010","00000000","00000000000000000000000111111111"),("00000110","00000000","00000010","00000001","0100000100000000","00000101","00000000","00000000000000000000000000000011"),("11000001","00000000","00000001","00000001","0101101100000000","00000110","00010000","00000000000000000000000000111100"),("10000000","00000000","0 0000001","00000001","0 000001000000000","00000001","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","00000000000000 00","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000 ","00000000","00000000 000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","000000000000000000000 00000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000") ,("00000000","00000000 ","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000", "00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00011111","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000011000")) Found 256x32-bit dual-port RAM for signal . Found 8-bit register for signal . Found 1-bit tristate buffer for signal > created at line 285 Found 1-bit tristate buffer for signal > created at line 285 Found 1-bit tristate buffer for signal > created at line 285 Found 1-bit tristate buffer for signal > created at line 285 Found 1-bit tristate buffer for signal > created at line 285 Found 1-bit tristate buffer for signal > created at line 285 Found 1-bit tristate buffer for signal > created at line 285 Found 1-bit tristate buffer for signal > created at line 285 Found 1-bit tristate buffer for signal > created at line 285 Found 1-bit tristate buffer for signal > created at line 285 Found 1-bit tristate buffer for signal > created at line 285 Found 1-bit tristate buffer for signal > created at line 285 Found 1-bit tristate buffer for signal > created at line 285 Found 1-bit tristate buffer for signal > created at line 285 Found 1-bit tristate buffer for signal > created at line 285 Found 1-bit tristate buffer for signal > created at line 285 Found 1-bit tristate buffer for signal > created at line 285 Found 1-bit tristate buffer for signal > created at line 285 Found 1-bit tristate buffer for signal > created at line 285 Found 1-bit tristate buffer for signal > created at line 285 Found 1-bit tristate buffer for signal > created at line 285 Found 1-bit tristate buffer for signal > created at line 285 Found 1-bit tristate buffer for signal > created at line 285 Found 1-bit tristate buffer for signal > created at line 285 Found 1-bit tristate buffer for signal > created at line 285 Found 1-bit tristate buffer for signal > created at line 285 Found 1-bit tristate buffer for signal > created at line 285 Found 1-bit tristate buffer for signal > created at line 285 Found 1-bit tristate buffer for signal > created at line 285 Found 1-bit tristate buffer for signal > created at line 285 Found 1-bit tristate buffer for signal > created at line 285 Found 1-bit tristate buffer for signal > created at line 285 Summary: inferred 1 RAM(s). inferred 8 D-type flip-flop(s). inferred 32 Tristate(s). Unit synthesized. Synthesizing Unit . Related source file is "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\simplespi8x.vhd". buswidth = 8 div = 1 bits = 8 Found 4-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 3-bit register for signal . Found 1-bit register for signal . Found 8-bit register for signal . Found 8-bit register for signal . Found 4-bit subtractor for signal > created at line 134. Found 3-bit subtractor for signal > created at line 141. Found 1-bit tristate buffer for signal > created at line 108 Found 1-bit tristate buffer for signal > created at line 108 Found 1-bit tristate buffer for signal > created at line 108 Found 1-bit tristate buffer for signal > created at line 108 Found 1-bit tristate buffer for signal > created at line 108 Found 1-bit tristate buffer for signal > created at line 108 Found 1-bit tristate buffer for signal > created at line 108 Found 1-bit tristate buffer for signal > created at line 108 Summary: inferred 2 Adder/Subtractor(s). inferred 27 D-type flip-flop(s). inferred 11 Multiplexer(s). inferred 8 Tristate(s). Unit synthesized. Synthesizing Unit . Related source file is "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\d16w.vhd". width = 16 iwidth = 24 maddwidth = 12 paddwidth = 12 INFO:Xst:3210 - "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\d16w.vhd" line 293: Output port of the instance is unconnected or connected to loadless signal. Found 24-bit register for signal . Found 24-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 4-bit register for signal . Found 1-bit register for signal . Found 12-bit register for signal . Found 12-bit register for signal . Found 12-bit register for signal . Found 16-bit register for signal . Found 17-bit register for signal . Found 16-bit register for signal . Found 12-bit register for signal . Found 12-bit register for signal . Found 12-bit register for signal . Found 12-bit register for signal . Found 4-bit register for signal . Found 12-bit register for signal . Found 12-bit adder for signal created at line 316. Found 12-bit adder for signal created at line 366. Found 17-bit adder for signal created at line 457. Found 17-bit adder for signal created at line 457. Found 4-bit adder for signal created at line 464. Found 16-bit subtractor for signal > created at line 412. Found 16-bit subtractor for signal > created at line 412. Found 17-bit subtractor for signal > created at line 459. Found 17-bit subtractor for signal > created at line 459. Found 4-bit subtractor for signal created at line 248. Found 16x16-bit multiplier for signal created at line 498. Found 12-bit 4-to-1 multiplexer for signal created at line 355. Summary: inferred 1 Multiplier(s). inferred 8 Adder/Subtractor(s). inferred 204 D-type flip-flop(s). inferred 147 Multiplexer(s). Unit synthesized. Synthesizing Unit . Related source file is "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\adpram.vhd". width = 16 depth = 16 Found 16-bit register for signal >. Found 16-bit register for signal >. Found 16-bit register for signal >. Found 16-bit register for signal >. Found 16-bit register for signal >. Found 16-bit register for signal >. Found 16-bit register for signal >. Found 16-bit register for signal >. Found 16-bit register for signal >. Found 16-bit register for signal >. Found 16-bit register for signal >. Found 16-bit register for signal >. Found 16-bit register for signal >. Found 16-bit register for signal >. Found 16-bit register for signal >. Found 16-bit register for signal >. INFO:Xst:3019 - HDL ADVISOR - 256 flip-flops were inferred for signal . You may be trying to describe a RAM in a way that is incompatible with block and distributed RAM resources available on Xilinx devices, or with a specific template that is not supported. Please review the Xilinx resources documentation and the XST user manual for coding guidelines. Taking advantage of RAM resources will lead to improved device usage and reduced synthesis time. INFO:Xst:3019 - HDL ADVISOR - 256 flip-flops were inferred for signal . You may be trying to describe a RAM in a way that is incompatible with block and distributed RAM resources available on Xilinx devices, or with a specific template that is not supported. Please review the Xilinx resources documentation and the XST user manual for coding guidelines. Taking advantage of RAM resources will lead to improved device usage and reduced synthesis time. Found 16-bit 16-to-1 multiplexer for signal created at line 100. Found 16-bit 16-to-1 multiplexer for signal created at line 101. Summary: inferred 256 D-type flip-flop(s). inferred 2 Multiplexer(s). Unit synthesized. Synthesizing Unit . Related source file is "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\etherhm2.vhd". Found 4096x24-bit dual-port RAM for signal . Found 12-bit register for signal . Summary: inferred 1 RAM(s). inferred 12 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is "D:\Base Danni Metal_Mill LTD\Mesa_Project_Analog_Encoder_PWM\hostmod\7i98\configs\hostmot2\source\hostmot2\dpram.vhd". width = 16 depth = 4096 Found 12-bit register for signal . Found 12-bit register for signal . Found 4096x16-bit dual-port RAM for signal . Summary: inferred 2 RAM(s). inferred 24 D-type flip-flop(s). Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # RAMs : 17 1024x8-bit dual-port RAM : 2 16x11-bit dual-port RAM : 1 16x11-bit single-port RAM : 1 2048x16-bit dual-port RAM : 2 24x10-bit single-port RAM : 1 256x32-bit dual-port RAM : 1 4096x16-bit dual-port RAM : 2 4096x24-bit dual-port RAM : 1 4x12-bit single-port Read Only RAM : 1 4x2-bit single-port Read Only RAM : 4 4x8-bit single-port Read Only RAM : 1 # Multipliers : 1 16x16-bit multiplier : 1 # Adders/Subtractors : 114 10-bit adder : 1 10-bit subtractor : 2 11-bit adder : 1 12-bit adder : 3 12-bit subtractor : 1 13-bit adder : 2 14-bit subtractor : 8 16-bit adder : 8 16-bit addsub : 5 16-bit subtractor : 5 17-bit adder : 2 17-bit addsub : 2 2-bit adder : 2 20-bit adder : 1 20-bit subtractor : 1 24-bit adder : 4 24-bit subtractor : 1 25-bit subtractor : 1 3-bit addsub : 1 3-bit subtractor : 1 32-bit subtractor : 1 33-bit adder : 1 4-bit adder : 2 4-bit addsub : 21 4-bit subtractor : 7 42-bit adder : 1 42-bit subtractor : 1 48-bit adder : 4 5-bit addsub : 2 5-bit subtractor : 1 8-bit adder : 4 8-bit addsub : 9 8-bit subtractor : 6 9-bit addsub : 2 # Registers : 662 1-bit register : 373 10-bit register : 6 11-bit register : 4 12-bit register : 25 13-bit register : 2 14-bit register : 25 16-bit register : 58 17-bit register : 18 2-bit register : 14 20-bit register : 4 24-bit register : 16 3-bit register : 2 32-bit register : 29 33-bit register : 1 4-bit register : 41 42-bit register : 1 48-bit register : 4 5-bit register : 5 6-bit register : 3 8-bit register : 30 9-bit register : 1 # Comparators : 28 10-bit comparator greater : 3 10-bit comparator not equal : 1 12-bit comparator greater : 1 24-bit comparator greater : 2 3-bit comparator lessequal : 1 4-bit comparator equal : 4 4-bit comparator greater : 15 8-bit comparator greater : 1 # Multiplexers : 1964 1-bit 2-to-1 multiplexer : 1732 1-bit 24-to-1 multiplexer : 2 1-bit 4-to-1 multiplexer : 19 1-bit 5-to-1 multiplexer : 1 1-bit 7-to-1 multiplexer : 2 10-bit 2-to-1 multiplexer : 5 11-bit 2-to-1 multiplexer : 10 12-bit 2-to-1 multiplexer : 20 12-bit 4-to-1 multiplexer : 2 14-bit 2-to-1 multiplexer : 20 16-bit 16-to-1 multiplexer : 2 16-bit 2-to-1 multiplexer : 9 17-bit 2-to-1 multiplexer : 14 2-bit 2-to-1 multiplexer : 5 2-bit 4-to-1 multiplexer : 4 24-bit 2-to-1 multiplexer : 5 24-bit 4-to-1 multiplexer : 2 3-bit 2-to-1 multiplexer : 7 32-bit 2-to-1 multiplexer : 5 4-bit 2-to-1 multiplexer : 48 42-bit 2-to-1 multiplexer : 1 48-bit 2-to-1 multiplexer : 4 5-bit 2-to-1 multiplexer : 6 8-bit 2-to-1 multiplexer : 28 9-bit 2-to-1 multiplexer : 11 # Tristates : 1057 1-bit tristate buffer : 1057 # Xors : 27 1-bit xor2 : 17 16-bit xor2 : 1 8-bit xor2 : 9 ========================================================================= INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing. ========================================================================= * Advanced HDL Synthesis * ========================================================================= INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . Synthesizing (advanced) Unit . INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): ----------------------------------------------------------------------- | ram_type | Block | | ----------------------------------------------------------------------- | Port A | | aspect ratio | 256-word x 32-bit | | | mode | read-first | | | clkA | connected to signal | rise | | weA | connected to signal | high | | addrA | connected to signal > | | | diA | connected to signal | | ----------------------------------------------------------------------- | optimization | speed | | ----------------------------------------------------------------------- | Port B | | aspect ratio | 256-word x 32-bit | | | mode | read-first | | | clkB | connected to signal | rise | | addrB | connected to signal > | | | doB | connected to internal node | | ----------------------------------------------------------------------- | optimization | speed | | ----------------------------------------------------------------------- Unit synthesized (advanced). Synthesizing (advanced) Unit . The following registers are absorbed into counter : 1 register on signal . The following registers are absorbed into counter : 1 register on signal . The following registers are absorbed into counter : 1 register on signal . INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): ----------------------------------------------------------------------- | ram_type | Block | | ----------------------------------------------------------------------- | Port A | | aspect ratio | 4096-word x 16-bit | | | mode | read-first | | | clkA | connected to signal | rise | | weA | connected to signal | high | | addrA | connected to signal | | | diA | connected to signal | | ----------------------------------------------------------------------- | optimization | speed | | ----------------------------------------------------------------------- | Port B | | aspect ratio | 4096-word x 16-bit | | | mode | write-first | | | clkB | connected to signal | rise | | addrB | connected to signal | | | doB | connected to signal | | ----------------------------------------------------------------------- | optimization | speed | | ----------------------------------------------------------------------- Unit synthesized (advanced). Synthesizing (advanced) Unit . INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. ----------------------------------------------------------------------- | ram_type | Distributed | | ----------------------------------------------------------------------- | Port A | | aspect ratio | 16-word x 11-bit | | | clkA | connected to signal | rise | | weA | connected to signal | high | | addrA | connected to signal | | | diA | connected to signal | | ----------------------------------------------------------------------- | Port B | | aspect ratio | 16-word x 11-bit | | | addrB | connected to signal | | | doB | connected to internal node | | ----------------------------------------------------------------------- INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. ----------------------------------------------------------------------- | ram_type | Distributed | | ----------------------------------------------------------------------- | Port A | | aspect ratio | 16-word x 11-bit | | | clkA | connected to signal | rise | | weA | connected to signal | high | | addrA | connected to signal | | | diA | connected to signal | | | doA | connected to signal | | ----------------------------------------------------------------------- Unit synthesized (advanced). Synthesizing (advanced) Unit . INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): ----------------------------------------------------------------------- | ram_type | Block | | ----------------------------------------------------------------------- | Port A | | aspect ratio | 4096-word x 24-bit | | | mode | write-first | | | clkA | connected to signal | rise | | weA | connected to signal | high | | addrA | connected to signal | | | diA | connected to signal | | | doA | connected to internal node | | ----------------------------------------------------------------------- | optimization | speed | | ----------------------------------------------------------------------- Unit synthesized (advanced). Synthesizing (advanced) Unit . The following registers are absorbed into accumulator : 1 register on signal . The following registers are absorbed into accumulator : 1 register on signal . The following registers are absorbed into counter : 1 register on signal . The following registers are absorbed into counter : 1 register on signal . The following registers are absorbed into counter : 1 register on signal . Unit synthesized (advanced). Synthesizing (advanced) Unit . The following registers are absorbed into counter : 1 register on signal . The following registers are absorbed into counter : 1 register on signal . The following registers are absorbed into counter : 1 register on signal . The following registers are absorbed into counter : 1 register on signal . INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. ----------------------------------------------------------------------- | ram_type | Distributed | | ----------------------------------------------------------------------- | Port A | | aspect ratio | 24-word x 10-bit | | | clkA | connected to signal | rise | | weA | connected to internal node | high | | addrA | connected to signal | | | diA | connected to signal <_n0846> | | | doA | connected to internal node | | ----------------------------------------------------------------------- Unit synthesized (advanced). Synthesizing (advanced) Unit . INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. ----------------------------------------------------------------------- | ram_type | Distributed | | ----------------------------------------------------------------------- | Port A | | aspect ratio | 4-word x 12-bit | | | weA | connected to signal | high | | addrA | connected to signal > | | | diA | connected to signal | | | doA | connected to signal | | ----------------------------------------------------------------------- Unit synthesized (advanced). Synthesizing (advanced) Unit . The following registers are absorbed into accumulator : 1 register on signal . The following registers are absorbed into accumulator : 1 register on signal . The following registers are absorbed into counter : 1 register on signal . Unit synthesized (advanced). Synthesizing (advanced) Unit . The following registers are absorbed into counter : 1 register on signal . Unit synthesized (advanced). Synthesizing (advanced) Unit . The following registers are absorbed into counter : 1 register on signal . The following registers are absorbed into counter : 1 register on signal . The following registers are absorbed into counter : 1 register on signal . The following registers are absorbed into counter : 1 register on signal . Unit synthesized (advanced). Synthesizing (advanced) Unit . The following registers are absorbed into accumulator : 1 register on signal . Unit synthesized (advanced). Synthesizing (advanced) Unit . The following registers are absorbed into counter : 1 register on signal . Unit synthesized (advanced). Synthesizing (advanced) Unit . The following registers are absorbed into counter : 1 register on signal . The following registers are absorbed into counter : 1 register on signal . INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. ----------------------------------------------------------------------- | ram_type | Distributed | | ----------------------------------------------------------------------- | Port A | | aspect ratio | 4-word x 8-bit | | | weA | connected to signal | high | | addrA | connected to signal > | | | diA | connected to signal | | | doA | connected to internal node | | ----------------------------------------------------------------------- INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): ----------------------------------------------------------------------- | ram_type | Block | | ----------------------------------------------------------------------- | Port A | | aspect ratio | 1024-word x 8-bit | | | mode | read-first | | | clkA | connected to signal | rise | | weA | connected to signal | high | | addrA | connected to signal <(mwadd<10>,mwadd<8:0>)> | | | diA | connected to signal | | ----------------------------------------------------------------------- | optimization | speed | | ----------------------------------------------------------------------- | Port B | | aspect ratio | 1024-word x 8-bit | | | mode | write-first | | | clkB | connected to signal | rise | | addrB | connected to signal <(mradd<10>,mradd<8:0>)> | | | doB | connected to signal | | ----------------------------------------------------------------------- | optimization | speed | | ----------------------------------------------------------------------- Unit synthesized (advanced). Synthesizing (advanced) Unit . INFO:Xst:3227 - The RAM , combined with , will be implemented as a BLOCK RAM, absorbing the following register(s): ----------------------------------------------------------------------- | ram_type | Block | | ----------------------------------------------------------------------- | Port A | | aspect ratio | 2048-word x 16-bit | | | mode | write-first | | | clkA | connected to signal | rise | | weA | connected to signal | high | | addrA | connected to signal | | | diA | connected to signal | | | doA | connected to signal | | ----------------------------------------------------------------------- | optimization | speed | | ----------------------------------------------------------------------- | Port B | | aspect ratio | 2048-word x 16-bit | | | mode | write-first | | | clkB | connected to signal | rise | | addrB | connected to signal | | | doB | connected to signal | | ----------------------------------------------------------------------- | optimization | speed | | ----------------------------------------------------------------------- Unit synthesized (advanced). Synthesizing (advanced) Unit . The following registers are absorbed into counter : 1 register on signal . The following registers are absorbed into counter : 1 register on signal . INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. ----------------------------------------------------------------------- | ram_type | Distributed | | ----------------------------------------------------------------------- | Port A | | aspect ratio | 4-word x 2-bit | | | weA | connected to signal | high | | addrA | connected to signal > | | | diA | connected to signal | | | doA | connected to internal node | | ----------------------------------------------------------------------- Unit synthesized (advanced). Synthesizing (advanced) Unit . The following registers are absorbed into counter
: 1 register on signal
. The following registers are absorbed into counter : 1 register on signal . Unit synthesized (advanced). Synthesizing (advanced) Unit . The following registers are absorbed into accumulator : 1 register on signal . The following registers are absorbed into counter : 1 register on signal . The following registers are absorbed into counter : 1 register on signal . The following registers are absorbed into counter : 1 register on signal . The following registers are absorbed into counter : 1 register on signal . Unit synthesized (advanced). Synthesizing (advanced) Unit . The following registers are absorbed into accumulator : 1 register on signal . The following registers are absorbed into counter : 1 register on signal . The following registers are absorbed into counter : 1 register on signal . The following registers are absorbed into counter : 1 register on signal . The following registers are absorbed into counter : 1 register on signal . Unit synthesized (advanced). WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . ========================================================================= Advanced HDL Synthesis Report Macro Statistics # RAMs : 14 1024x8-bit dual-port block RAM : 1 16x11-bit dual-port distributed RAM : 1 16x11-bit single-port distributed RAM : 1 2048x16-bit dual-port block RAM : 1 24x10-bit single-port distributed RAM : 1 256x32-bit dual-port block RAM : 1 4096x16-bit dual-port block RAM : 1 4096x24-bit single-port block RAM : 1 4x12-bit single-port distributed Read Only RAM : 1 4x2-bit single-port distributed Read Only RAM : 4 4x8-bit single-port distributed Read Only RAM : 1 # Multipliers : 1 16x16-bit multiplier : 1 # Adders/Subtractors : 52 10-bit adder : 1 10-bit subtractor : 1 11-bit adder : 1 12-bit adder : 3 13-bit adder : 1 14-bit subtractor : 8 16-bit adder : 5 16-bit subtractor : 2 17-bit addsub carry/borrow in : 1 24-bit adder : 2 24-bit subtractor : 2 32-bit subtractor : 1 4-bit adder : 2 4-bit addsub : 4 4-bit subtractor : 3 42-bit adder : 1 42-bit subtractor : 1 48-bit adder : 4 8-bit adder : 4 8-bit subtractor : 4 9-bit addsub carry/borrow in : 1 # Counters : 53 10-bit down counter : 1 12-bit down counter : 1 13-bit up counter : 1 16-bit down counter : 3 16-bit up counter : 3 16-bit updown counter : 5 2-bit up counter : 2 3-bit down counter : 1 3-bit updown counter : 1 4-bit down counter : 4 4-bit updown counter : 17 5-bit down counter : 1 5-bit updown counter : 2 8-bit down counter : 2 8-bit updown counter : 9 # Accumulators : 7 17-bit up accumulator : 2 20-bit down accumulator : 1 20-bit up accumulator : 1 24-bit up accumulator : 2 33-bit up accumulator : 1 # Registers : 3847 Flip-Flops : 3847 # Comparators : 28 10-bit comparator greater : 3 10-bit comparator not equal : 1 12-bit comparator greater : 1 24-bit comparator greater : 2 3-bit comparator lessequal : 1 4-bit comparator equal : 4 4-bit comparator greater : 15 8-bit comparator greater : 1 # Multiplexers : 2301 1-bit 16-to-1 multiplexer : 32 1-bit 2-to-1 multiplexer : 2052 1-bit 24-to-1 multiplexer : 2 1-bit 4-to-1 multiplexer : 31 1-bit 5-to-1 multiplexer : 1 1-bit 7-to-1 multiplexer : 2 10-bit 2-to-1 multiplexer : 4 11-bit 2-to-1 multiplexer : 9 12-bit 2-to-1 multiplexer : 18 12-bit 4-to-1 multiplexer : 1 14-bit 2-to-1 multiplexer : 20 16-bit 2-to-1 multiplexer : 6 17-bit 2-to-1 multiplexer : 13 2-bit 2-to-1 multiplexer : 5 2-bit 4-to-1 multiplexer : 4 24-bit 2-to-1 multiplexer : 5 24-bit 4-to-1 multiplexer : 2 3-bit 2-to-1 multiplexer : 7 32-bit 2-to-1 multiplexer : 5 4-bit 2-to-1 multiplexer : 42 5-bit 2-to-1 multiplexer : 6 8-bit 2-to-1 multiplexer : 23 9-bit 2-to-1 multiplexer : 11 # Xors : 27 1-bit xor2 : 17 16-bit xor2 : 1 8-bit xor2 : 9 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches, which will be removed : INFO:Xst:1901 - Instance ClockMult1 in unit TopEthernetHostMot2 of type DCM has been replaced by DCM_SP INFO:Xst:1901 - Instance ClockMult2 in unit TopEthernetHostMot2 of type DCM has been replaced by DCM_SP WARNING:Xst:2040 - Unit TopEthernetHostMot2: 48 multi-source signals are replaced by logic (pull-up yes): HM2obus<0>, HM2obus<10>, HM2obus<11>, HM2obus<12>, HM2obus<13>, HM2obus<14>, HM2obus<15>, HM2obus<16>, HM2obus<17>, HM2obus<18>, HM2obus<19>, HM2obus<1>, HM2obus<20>, HM2obus<21>, HM2obus<22>, HM2obus<23>, HM2obus<24>, HM2obus<25>, HM2obus<26>, HM2obus<27>, HM2obus<28>, HM2obus<29>, HM2obus<2>, HM2obus<30>, HM2obus<31>, HM2obus<3>, HM2obus<4>, HM2obus<5>, HM2obus<6>, HM2obus<7>, HM2obus<8>, H M2obus<9>, mibus_io<10>, mibus_io<11>, mibus_io<12>, mibus_io<13>, mibus_io<14>, mibus_io<15>, mibus_io<8>, mibus_io<9>, n0308<0>, n0308<1>, n0308<2>, n0308<3>, n0308<4>, n0308<5>, n0308<6>, n0308<7>. WARNING:Xst:2042 - Unit simplespi8: 8 internal tristates are replaced by logic (pull-up yes): obus<0>, obus<1>, obus<2>, obus<3>, obus<4>, obus<5>, obus<6>, obus<7>. WARNING:Xst:2042 - Unit watchdog: 32 internal tristates are replaced by logic (pull-up yes): obus<0>, obus<10>, obus<11>, obus<12>, obus<13>, obus<14>, obus<15>, obus<16>, obus<17>, obus<18>, obus<19>, obus<1>, obus<20>, obus<21>, obus<22>, obus<23>, obus<24>, obus<25>, obus<26>, obus<27>, obus<28>, obus<29>, obus<2>, obus<30>, obus<31>, obus<3>, obus<4>, obus<5>, obus<6>, obus<7>, obus<8>, obus<9>. WARNING:Xst:2042 - Unit irqlogics: 32 internal tristates are replaced by logic (pull-up yes): obus<0>, obus<10>, obus<11>, obus<12>, obus<13>, obus<14>, obus<15>, obus<16>, obus<17>, obus<18>, obus<19>, obus<1>, obus<20>, obus<21>, obus<22>, obus<23>, obus<24>, obus<25>, obus<26>, obus<27>, obus<28>, obus<29>, obus<2>, obus<30>, obus<31>, obus<3>, obus<4>, obus<5>, obus<6>, obus<7>, obus<8>, obus<9>. WARNING:Xst:2042 - Unit hm2dpll: 32 internal tristates are replaced by logic (pull-up yes): obus<0>, obus<10>, obus<11>, obus<12>, obus<13>, obus<14>, obus<15>, obus<16>, obus<17>, obus<18>, obus<19>, obus<1>, obus<20>, obus<21>, obus<22>, obus<23>, obus<24>, obus<25>, obus<26>, obus<27>, obus<28>, obus<29>, obus<2>, obus<30>, obus<31>, obus<3>, obus<4>, obus<5>, obus<6>, obus<7>, obus<8>, obus<9>. WARNING:Xst:2042 - Unit rategend: 32 internal tristates are replaced by logic (pull-up yes): obus<0>, obus<10>, obus<11>, obus<12>, obus<13>, obus<14>, obus<15>, obus<16>, obus<17>, obus<18>, obus<19>, obus<1>, obus<20>, obus<21>, obus<22>, obus<23>, obus<24>, obus<25>, obus<26>, obus<27>, obus<28>, obus<29>, obus<2>, obus<30>, obus<31>, obus<3>, obus<4>, obus<5>, obus<6>, obus<7>, obus<8>, obus<9>. WARNING:Xst:2042 - Unit stepgenid: 32 internal tristates are replaced by logic (pull-up yes): obus<0>, obus<10>, obus<11>, obus<12>, obus<13>, obus<14>, obus<15>, obus<16>, obus<17>, obus<18>, obus<19>, obus<1>, obus<20>, obus<21>, obus<22>, obus<23>, obus<24>, obus<25>, obus<26>, obus<27>, obus<28>, obus<29>, obus<2>, obus<30>, obus<31>, obus<3>, obus<4>, obus<5>, obus<6>, obus<7>, obus<8>, obus<9>. WARNING:Xst:2042 - Unit qcounterated: 32 internal tristates are replaced by logic (pull-up yes): obus<0>, obus<10>, obus<11>, obus<12>, obus<13>, obus<14>, obus<15>, obus<16>, obus<17>, obus<18>, obus<19>, obus<1>, obus<20>, obus<21>, obus<22>, obus<23>, obus<24>, obus<25>, obus<26>, obus<27>, obus<28>, obus<29>, obus<2>, obus<30>, obus<31>, obus<3>, obus<4>, obus<5>, obus<6>, obus<7>, obus<8>, obus<9>. WARNING:Xst:2042 - Unit inmuxm: 32 internal tristates are replaced by logic (pull-up yes): obus<0>, obus<10>, obus<11>, obus<12>, obus<13>, obus<14>, obus<15>, obus<16>, obus<17>, obus<18>, obus<19>, obus<1>, obus<20>, obus<21>, obus<22>, obus<23>, obus<24>, obus<25>, obus<26>, obus<27>, obus<28>, obus<29>, obus<2>, obus<30>, obus<31>, obus<3>, obus<4>, obus<5>, obus<6>, obus<7>, obus<8>, obus<9>. WARNING:Xst:2040 - Unit sserialwa: 40 multi-source signals are replaced by logic (pull-up yes): iodata<0>, iodata<1>, iodata<2>, iodata<3>, iodata<4>, iodata<5>, iodata<6>, iodata<7>, obus<0>, obus<10>, obus<11>, obus<12>, obus<13>, obus<14>, obus<15>, obus<16>, obus<17>, obus<18>, obus<19>, obus<1>, obus<20>, obus<21>, obus<22>, obus<23>, obus<24>, obus<25>, obus<26>, obus<27>, obus<28>, obus<29>, obus<2>, obus<30>, obus<31>, obus<3>, obus<4>, obus<5>, obus<6>, obus<7>, obus<8>, obus<9>. WARNING:Xst:2042 - Unit boutreg_2: 32 internal tristates are replaced by logic (pull-up yes): obus<0>, obus<10>, obus<11>, obus<12>, obus<13>, obus<14>, obus<15>, obus<16>, obus<17>, obus<18>, obus<19>, obus<1>, obus<20>, obus<21>, obus<22>, obus<23>, obus<24>, obus<25>, obus<26>, obus<27>, obus<28>, obus<29>, obus<2>, obus<30>, obus<31>, obus<3>, obus<4>, obus<5>, obus<6>, obus<7>, obus<8>, obus<9>. WARNING:Xst:2042 - Unit timestampd: 16 internal tristates are replaced by logic (pull-up yes): obus<0>, obus<10>, obus<11>, obus<12>, obus<13>, obus<14>, obus<15>, obus<1>, obus<2>, obus<3>, obus<4>, obus<5>, obus<6>, obus<7>, obus<8>, obus<9>. WARNING:Xst:2042 - Unit boutreg_1: 4 internal tristates are replaced by logic (pull-up yes): obus<0>, obus<1>, obus<2>, obus<3>. WARNING:Xst:2042 - Unit wordrb: 32 internal tristates are replaced by logic (pull-up yes): obus<0>, obus<10>, obus<11>, obus<12>, obus<13>, obus<14>, obus<15>, obus<16>, obus<17>, obus<18>, obus<19>, obus<1>, obus<20>, obus<21>, obus<22>, obus<23>, obus<24>, obus<25>, obus<26>, obus<27>, obus<28>, obus<29>, obus<2>, obus<30>, obus<31>, obus<3>, obus<4>, obus<5>, obus<6>, obus<7>, obus<8>, obus<9>. WARNING:Xst:2042 - Unit hostmotid: 32 internal tristates are replaced by logic (pull-up yes): obus<0>, obus<10>, obus<11>, obus<12>, obus<13>, obus<14>, obus<15>, obus<16>, obus<17>, obus<18>, obus<19>, obus<1>, obus<20>, obus<21>, obus<22>, obus<23>, obus<24>, obus<25>, obus<26>, obus<27>, obus<28>, obus<29>, obus<2>, obus<30>, obus<31>, obus<3>, obus<4>, obus<5>, obus<6>, obus<7>, obus<8>, obus<9>. WARNING:Xst:2042 - Unit uartr8: 8 internal tristates are replaced by logic (pull-up yes): obus<0>, obus<1>, obus<2>, obus<3>, obus<4>, obus<5>, obus<6>, obus<7>. WARNING:Xst:2042 - Unit uartx8: 8 internal tristates are replaced by logic (pull-up yes): obus<0>, obus<1>, obus<2>, obus<3>, obus<4>, obus<5>, obus<6>, obus<7>. WARNING:Xst:2677 - Node of sequential type is unconnected in block . INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : Optimizing unit ... Optimizing unit ... WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. Optimizing unit ... Optimizing unit ... Optimizing unit ... WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : INFO:Xst:3203 - The FF/Latch in Unit is the opposite to the following FF/Latch, which will be removed : INFO:Xst:3203 - The FF/Latch in Unit is the opposite to the following FF/Latch, which will be removed : INFO:Xst:3203 - The FF/Latch in Unit is the opposite to the following FF/Latch, which will be removed : INFO:Xst:3203 - The FF/Latch in Unit is the opposite to the following FF/Latch, which will be removed : Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block TopEthernetHostMot2, actual ratio is 143. Optimizing block to meet ratio 100 (+ 5) of 1430 slices : WARNING:Xst:2254 - Area constraint could not be met for block , final ratio is 124. FlipFlop ahostmot2/makeinmuxmod.generateinmuxes[0].inmuxxm/index_1 has been replicated 1 time(s) FlipFlop ahostmot2/makeinmuxmod.generateinmuxes[0].inmuxxm/index_2 has been replicated 1 time(s) FlipFlop ahostmot2/makeinmuxmod.generateinmuxes[0].inmuxxm/index_4 has been replicated 1 time(s) FlipFlop ahostmot2/makeinmuxmod.generateinmuxes[0].inmuxxm/muxcount_0 has been replicated 1 time(s) Final Macro Processing ... Processing Unit : Found 2-bit shift register for signal . Found 2-bit shift register for signal . Found 2-bit shift register for signal . Unit processed. ========================================================================= Final Register Report Macro Statistics # Registers : 4229 Flip-Flops : 4229 # Shift Registers : 3 2-bit shift register : 3 ========================================================================= ========================================================================= * Partition Report * ========================================================================= Partition Implementation Status ------------------------------- No Partitions were found in this design. ------------------------------- ========================================================================= * Design Summary * ========================================================================= Clock Information: ------------------ -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ CLK | DCM_SP:CLKFX | 4151 | CLK | DCM_SP:CLKFX | 135 | -----------------------------------+------------------------+-------+ Asynchronous Control Signals Information: ---------------------------------------- No asynchronous control signals found in this design Timing Summary: --------------- Speed Grade: -2 Minimum period: 19.376ns (Maximum Frequency: 51.610MHz) Minimum input arrival time before clock: 5.556ns Maximum output required time after clock: 8.906ns Maximum combinational path delay: No path found ========================================================================= Process "Synthesize - XST" completed successfully Started : "Translate". Running ngdbuild... Command Line: ngdbuild -intstyle ise -dd _ngo -aut -nt timestamp -uc 7i98.ucf -p xc6slx9-tqg144-2 "TopEthernetHostMot2.ngc" TopEthernetHostMot2.ngd Command Line: C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe -intstyle ise -dd _ngo -aut -nt timestamp -uc 7i98.ucf -p xc6slx9-tqg144-2 TopEthernetHostMot2.ngc TopEthernetHostMot2.ngd Reading NGO file "D:/Base Danni Metal_Mill LTD/Mesa_Project_Analog_Encoder_PWM/hostmod/7i98/configs/hostmot2/source/hostmot 2/TopEthernetHostMot2.ngc" ... Gathering constraint information from source properties... Done. Annotating constraints to design from ucf file "7i98.ucf" ... Resolving constraint associations... Checking Constraint Associations... Done... Checking expanded design ... Partition Implementation Status ------------------------------- No Partitions were found in this design. ------------------------------- NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Writing NGD file "TopEthernetHostMot2.ngd" ... Total REAL time to NGDBUILD completion: 8 sec Total CPU time to NGDBUILD completion: 8 sec Writing NGDBUILD log file "TopEthernetHostMot2.bld"... NGDBUILD done. Process "Translate" completed successfully Started : "Map". Running map... Command Line: map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o TopEthernetHostMot2_map.ncd TopEthernetHostMot2.ngd TopEthernetHostMot2.pcf Using target part "6slx9tqg144-2". vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv INFO:Security:54 - 'xc6slx9' is a WebPack part. WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases. ---------------------------------------------------------------------- Mapping design into LUTs... Running directed packing... Running delay-based LUT packing... Updating timing models... INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report (.mrp). Running timing-driven placement... Total REAL time at the beginning of Placer: 15 secs Total CPU time at the beginning of Placer: 15 secs Phase 1.1 Initial Placement Analysis Phase 1.1 Initial Placement Analysis (Checksum:a4e7a0b2) REAL time: 17 secs Phase 2.7 Design Feasibility Check Phase 2.7 Design Feasibility Check (Checksum:a4e7a0b2) REAL time: 17 secs Phase 3.31 Local Placement Optimization Phase 3.31 Local Placement Optimization (Checksum:a4e7a0b2) REAL time: 17 secs Phase 4.2 Initial Placement for Architecture Specific Features Phase 4.2 Initial Placement for Architecture Specific Features (Checksum:be8e4d39) REAL time: 25 secs Phase 5.36 Local Placement Optimization Phase 5.36 Local Placement Optimization (Checksum:be8e4d39) REAL time: 25 secs Phase 6.30 Global Clock Region Assignment Phase 6.30 Global Clock Region Assignment (Checksum:be8e4d39) REAL time: 25 secs Phase 7.3 Local Placement Optimization Phase 7.3 Local Placement Optimization (Checksum:35baa568) REAL time: 25 secs Phase 8.5 Local Placement Optimization Phase 8.5 Local Placement Optimization (Checksum:35baa568) REAL time: 25 secs Phase 9.8 Global Placement ........................ ................................................................................ ........................................................................................................................................................................................ ........................................................................................................................................................................ .............................................. Phase 9.8 Global Placement (Checksum:26b8cfd7) REAL time: 1 mins 51 secs Phase 10.5 Local Placement Optimization Phase 10.5 Local Placement Optimization (Checksum:26b8cfd7) REAL time: 1 mins 51 secs Phase 11.18 Placement Optimization Phase 11.18 Placement Optimization (Checksum:b855f103) REAL time: 2 mins 3 secs Phase 12.5 Local Placement Optimization Phase 12.5 Local Placement Optimization (Checksum:b855f103) REAL time: 2 mins 3 secs Phase 13.34 Placement Validation Phase 13.34 Placement Validation (Checksum:524af4fd) REAL time: 2 mins 3 secs Total REAL time to Placer completion: 2 mins 4 secs Total CPU time to Placer completion: 2 mins 4 secs Running post-placement packing... Writing output files... Design Summary: Number of errors: 0 Number of warnings: 3 Slice Logic Utilization: Number of Slice Registers: 4,271 out of 11,440 37% Number used as Flip Flops: 4,232 Number used as Latches: 0 Number used as Latch-thrus: 0 Number used as AND/OR logics: 39 Number of Slice LUTs: 4,327 out of 5,720 75% Number used as logic: 4,227 out of 5,720 73% Number using O6 output only: 2,912 Number using O5 output only: 86 Number using O5 and O6: 1,229 Number used as ROM: 0 Number used as Memory: 34 out of 1,440 2% Number used as Dual Port RAM: 8 Number using O6 output only: 0 Number using O5 output only: 1 Number using O5 and O6: 7 Number used as Single Port RAM: 7 Number using O6 output only: 4 Number using O5 output only: 0 Number using O5 and O6: 3 Number used as Shift Register: 19 Number using O6 output only: 11 Number using O5 output only: 0 Number using O5 and O6: 8 Number used exclusively as route-thrus: 66 Number with same-slice register load: 55 Number with same-slice carry load: 11 Number with other load: 0 Slice Logic Distribution: Number of occupied Slices: 1,405 out of 1,430 98% Number of MUXCYs used: 1,628 out of 2,860 56% Number of LUT Flip Flop pairs used: 5,096 Number with an unused Flip Flop: 1,395 out of 5,096 27% Number with an unused LUT: 769 out of 5,096 15% Number of fully used LUT-FF pairs: 2,932 out of 5,096 57% Number of unique control sets: 192 Number of slice register sites lost to control set restrictions: 444 out of 11,440 3% A LUT Flip Flop pair for this architecture represents one LUT paired with one Flip Flop within a slice. A control set is a unique combination of clock, reset, set, and enable signals for a registered element. The Slice Logic Distribution report is not meaningful if the design is over-mapped for a non-slice resource or if Placement fails. IO Utilization: Number of bonded IOBs: 88 out of 102 86% Number of LOCed IOBs: 88 out of 88 100% Specific Feature Utilization: Number of RAMB16BWERs: 12 out of 32 37% Number of RAMB8BWERs: 2 out of 64 3% Number of BUFIO2/BUFIO2_2CLKs: 2 out of 32 6% Number used as BUFIO2s: 2 Number used as BUFIO2_2CLKs: 0 Number of BUFIO2FB/BUFIO2FB_2CLKs: 2 out of 32 6% Number used as BUFIO2FBs: 2 Number used as BUFIO2FB_2CLKs: 0 Number of BUFG/BUFGMUXs: 4 out of 16 25% Number used as BUFGs: 4 Number used as BUFGMUX: 0 Number of DCM/DCM_CLKGENs: 2 out of 4 50% Number used as DCMs: 2 Number used as DCM_CLKGENs: 0 Number of ILOGIC2/ISERDES2s: 0 out of 200 0% Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 200 0% Number of OLOGIC2/OSERDES2s: 0 out of 200 0% Number of BSCANs: 0 out of 4 0% Number of BUFHs: 0 out of 128 0% Number of BUFPLLs: 0 out of 8 0% Number of BUFPLL_MCBs: 0 out of 4 0% Number of DSP48A1s: 1 out of 16 6% Number of ICAPs: 1 out of 1 100% Number of MCBs: 0 out of 2 0% Number of PCILOGICSEs: 0 out of 2 0% Number of PLL_ADVs: 0 out of 2 0% Number of PMVs: 0 out of 1 0% Number of STARTUPs: 0 out of 1 0% Number of SUSPEND_SYNCs: 0 out of 1 0% Average Fanout of Non-Clock Nets: 3.59 Peak Memory Usage: 4639 MB Total REAL time to MAP completion: 2 mins 9 secs Total CPU time to MAP completion: 2 mins 8 secs Mapping completed. See MAP report file "TopEthernetHostMot2_map.mrp" for details. Process "Map" completed successfully Started : "Place & Route". Running par... Command Line: par -w -intstyle ise -ol high -mt off TopEthernetHostMot2_map.ncd TopEthernetHostMot2.ncd TopEthernetHostMot2.pcf Constraints file: TopEthernetHostMot2.pcf. Loading device for application Rf_Device from file '6slx9.nph' in environment C:\Xilinx\14.7\ISE_DS\ISE\. "TopEthernetHostMot2" is an NCD, version 3.2, device xc6slx9, package tqg144, speed -2 vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv INFO:Security:54 - 'xc6slx9' is a WebPack part. WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases. ---------------------------------------------------------------------- Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius) Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts) Device speed data version: "PRODUCTION 1.23 2013-10-13". Device Utilization Summary: Slice Logic Utilization: Number of Slice Registers: 4,271 out of 11,440 37% Number used as Flip Flops: 4,232 Number used as Latches: 0 Number used as Latch-thrus: 0 Number used as AND/OR logics: 39 Number of Slice LUTs: 4,327 out of 5,720 75% Number used as logic: 4,227 out of 5,720 73% Number using O6 output only: 2,912 Number using O5 output only: 86 Number using O5 and O6: 1,229 Number used as ROM: 0 Number used as Memory: 34 out of 1,440 2% Number used as Dual Port RAM: 8 Number using O6 output only: 0 Number using O5 output only: 1 Number using O5 and O6: 7 Number used as Single Port RAM: 7 Number using O6 output only: 4 Number using O5 output only: 0 Number using O5 and O6: 3 Number used as Shift Register: 19 Number using O6 output only: 11 Number using O5 output only: 0 Number using O5 and O6: 8 Number used exclusively as route-thrus: 66 Number with same-slice register load: 55 Number with same-slice carry load: 11 Number with other load: 0 Slice Logic Distribution: Number of occupied Slices: 1,405 out of 1,430 98% Number of MUXCYs used: 1,628 out of 2,860 56% Number of LUT Flip Flop pairs used: 5,096 Number with an unused Flip Flop: 1,395 out of 5,096 27% Number with an unused LUT: 769 out of 5,096 15% Number of fully used LUT-FF pairs: 2,932 out of 5,096 57% Number of slice register sites lost to control set restrictions: 0 out of 11,440 0% A LUT Flip Flop pair for this architecture represents one LUT paired with one Flip Flop within a slice. A control set is a unique combination of clock, reset, set, and enable signals for a registered element. The Slice Logic Distribution report is not meaningful if the design is over-mapped for a non-slice resource or if Placement fails. IO Utilization: Number of bonded IOBs: 88 out of 102 86% Number of LOCed IOBs: 88 out of 88 100% Specific Feature Utilization: Number of RAMB16BWERs: 12 out of 32 37% Number of RAMB8BWERs: 2 out of 64 3% Number of BUFIO2/BUFIO2_2CLKs: 2 out of 32 6% Number used as BUFIO2s: 2 Number used as BUFIO2_2CLKs: 0 Number of BUFIO2FB/BUFIO2FB_2CLKs: 2 out of 32 6% Number used as BUFIO2FBs: 2 Number used as BUFIO2FB_2CLKs: 0 Number of BUFG/BUFGMUXs: 4 out of 16 25% Number used as BUFGs: 4 Number used as BUFGMUX: 0 Number of DCM/DCM_CLKGENs: 2 out of 4 50% Number used as DCMs: 2 Number used as DCM_CLKGENs: 0 Number of ILOGIC2/ISERDES2s: 0 out of 200 0% Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 200 0% Number of OLOGIC2/OSERDES2s: 0 out of 200 0% Number of BSCANs: 0 out of 4 0% Number of BUFHs: 0 out of 128 0% Number of BUFPLLs: 0 out of 8 0% Number of BUFPLL_MCBs: 0 out of 4 0% Number of DSP48A1s: 1 out of 16 6% Number of ICAPs: 1 out of 1 100% Number of MCBs: 0 out of 2 0% Number of PCILOGICSEs: 0 out of 2 0% Number of PLL_ADVs: 0 out of 2 0% Number of PMVs: 0 out of 1 0% Number of STARTUPs: 0 out of 1 0% Number of SUSPEND_SYNCs: 0 out of 1 0% Overall effort level (-ol): High Router effort level (-rl): High Starting initial Timing Analysis. REAL time: 7 secs Finished initial Timing Analysis. REAL time: 8 secs WARNING:Par:288 - The signal ahostmot2/makesserialmod.makesserials[0].asserial/processor/StackRam/Mram_RAM2_RAMD_D1_O has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal ahostmot2/makesserialmod.makesserials[0].asserial/processor/StackRam/Mram_RAM1_RAMD_D1_O has no load. PAR will not attempt to route this signal. Starting Router Phase 1 : 26272 unrouted; REAL time: 8 secs Phase 2 : 22935 unrouted; REAL time: 9 secs Phase 3 : 11305 unrouted; REAL time: 24 secs Phase 4 : 11310 unrouted; (Setup:0, Hold:28484, Component Switching Limit:0) REAL time: 26 secs Updating file: TopEthernetHostMot2.ncd with current fully routed design. Phase 5 : 0 unrouted; (Setup:0, Hold:26435, Component Switching Limit:0) REAL time: 50 secs Phase 6 : 0 unrouted; (Setup:0, Hold:26435, Component Switching Limit:0) REAL time: 50 secs Phase 7 : 0 unrouted; (Setup:0, Hold:26435, Component Switching Limit:0) REAL time: 50 secs Phase 8 : 0 unrouted; (Setup:0, Hold:26435, Component Switching Limit:0) REAL time: 50 secs Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 50 secs Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 52 secs Total REAL time to Router completion: 52 secs Total CPU time to Router completion: 54 secs Partition Implementation Status ------------------------------- No Partitions were found in this design. ------------------------------- Generating "PAR" statistics. ************************** Generating Clock Report ************************** +---------------------+--------------+------+------+------------+-------------+ | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| +---------------------+--------------+------+------+------------+-------------+ | procclk | BUFGMUX_X2Y2| No | 1137 | 0.123 | 1.514 | +---------------------+--------------+------+------+------------+-------------+ | hm2fastclock | BUFGMUX_X2Y4| No | 42 | 0.084 | 1.511 | +---------------------+--------------+------+------+------------+-------------+ | ICapClk | Local| | 2 | 0.000 | 1.489 | +---------------------+--------------+------+------+------------+-------------+ * Net Skew is the difference between the minimum and maximum routing only delays for the net. Note this is different from Clock Skew which is reported in TRCE timing report. Clock Skew is the difference between the minimum and maximum path delays which includes logic delays. * The fanout is the number of component pins not the individual BEL loads, for example SLICE loads not FF loads. Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Number of Timing Constraints that were not applied: 1 Asterisk (*) preceding a constraint indicates it was not met. This may be due to a setup or hold violation. ---------------------------------------------------------------------------------------------------------- Constraint | Check | Worst Case | Best Case | Timing | Timing | | Slack | Achievable | Errors | Score ---------------------------------------------------------------------------------------------------------- TS_clk1fx = PERIOD TIMEGRP "clk1fx" TS_CL | SETUP | 0.004ns| 4.971ns| 0| 0 K / 4 HIGH 50% | HOLD | 0.008ns| | 0| 0 ---------------------------------------------------------------------------------------------------------- TS_clk0fx = PERIOD TIMEGRP "clk0fx" TS_CL | SETUP | 0.514ns| 9.347ns| 0| 0 K / 2 HIGH 50% | HOLD | 0.287ns| | 0| 0 ---------------------------------------------------------------------------------------------------------- TS_CLK = PERIOD TIMEGRP "CLK" 19.9 ns HIG | MINLOWPULSE | 11.900ns| 8.000ns| 0| 0 H 50% | | | | | ---------------------------------------------------------------------------------------------------------- Derived Constraint Report Review Timing Report for more details on the following derived constraints. To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf" or "Run Timing Analysis" from Timing Analyzer (timingan). Derived Constraints for TS_CLK +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ | | Period | Actual Period | Timing Errors | Paths Analyzed | | Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------| | | | Direct | Derivative | Direct | Derivative | Direct | Derivative | +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ |TS_CLK | 19.900ns| 8.000ns| 19.884ns| 0| 0| 0| 258324| | TS_clk1fx | 4.975ns| 4.971ns| N/A| 0| 0| 1605| 0| | TS_clk0fx | 9.950ns| 9.347ns| N/A| 0| 0| 256719| 0| +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ All constraints were met. Generating Pad Report. All signals are completely routed. WARNING:Par:283 - There are 2 loadless signals in this design. This design will cause Bitgen to issue DRC warnings. Total REAL time to PAR completion: 54 secs Total CPU time to PAR completion: 56 secs Peak Memory Usage: 4592 MB Placer: Placement generated during map. Routing: Completed - No errors found. Timing: Completed - No errors found. Number of error messages: 0 Number of warning messages: 4 Number of info messages: 0 Writing design to file TopEthernetHostMot2.ncd PAR done! Process "Place & Route" completed successfully Started : "Generate Post-Place & Route Static Timing". Running trce... Command Line: trce -intstyle ise -v 10 -s 2 -n 3 -fastpaths -xml TopEthernetHostMot2.twx TopEthernetHostMot2.ncd -o TopEthernetHostMot2.twr TopEthernetHostMot2.pcf -ucf 7i98.ucf Loading device for application Rf_Device from file '6slx9.nph' in environment C:\Xilinx\14.7\ISE_DS\ISE\. "TopEthernetHostMot2" is an NCD, version 3.2, device xc6slx9, package tqg144, speed -2 Analysis completed Thu May 30 12:25:12 2024 -------------------------------------------------------------------------------- Generating Report ... Number of warnings: 0 Total time: 11 secs Process "Generate Post-Place & Route Static Timing" completed successfully