Started : "Generate Programming File".
Running bitgen...
Command Line: bitgen -intstyle ise -f TopEthernetHostMot2.ut TopEthernetHostMot2.ncd
WARNING:Bitgen:284 - Setting next_config_register_write to Disable will cause
   the next_config_addr, next_config_new_mode, and next_config_boot_mode options
   to be ignored and their respective register writes to be excluded from the
   bitstream.
INFO:Bitgen:341 - This design is using one or more 9K Block RAMs (RAMB8BWER). 
   9K Block RAM initialization data, both user defined and default, requires a
   special bit stream format.  For more information, please reference Xilinx
   Answer Record 39999.
WARNING:PhysDesignRules:367 - The signal
   <ahostmot2/makesserialmod.makesserials[0].asserial/processor/StackRam/Mram_RA
   M1_RAMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <ahostmot2/makesserialmod.makesserials[0].asserial/processor/StackRam/Mram_RA
   M2_RAMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
INFO:PhysDesignRules:1861 - To achieve optimal frequency synthesis performance
   with the CLKFX and CLKFX180 outputs of the DCM comp ClockMult1, consult the
   device Data Sheet.
INFO:PhysDesignRules:1861 - To achieve optimal frequency synthesis performance
   with the CLKFX and CLKFX180 outputs of the DCM comp ClockMult2, consult the
   device Data Sheet.
WARNING:PhysDesignRules:2410 - This design is using one or more 9K Block RAMs
   (RAMB8BWER).  9K Block RAM initialization data, both user defined and
   default, may be incorrect and should not be used.  For more information,
   please reference Xilinx Answer Record 39999.
FATAL_ERROR:Bitstream:stanbsbitfile.c:3408:1.57 - Incorrect number of bits in
   bitstream (18) for FDRI write.   For technical support on this issue, please
   visit http://www.xilinx.com/support.

Process "Generate Programming File" failed