=== Master 0, Slave 0 === SM0: PhysAddr 0x1000, DefaultSize 128, ControlRegister 0x26, Enable 1 SM1: PhysAddr 0x1400, DefaultSize 128, ControlRegister 0x22, Enable 1 SM2: PhysAddr 0x1800, DefaultSize 5, ControlRegister 0x64, Enable 1 RxPDO 0x1600 "RxPDO0-Map" PDO entry 0x6600:01, 16 bit, "OUT" SM3: PhysAddr 0x1c00, DefaultSize 7, ControlRegister 0x20, Enable 1 TxPDO 0x1a00 "TxPDO0-Map" PDO entry 0x6100:01, 32 bit, "Encoder0" PDO entry 0x6100:02, 32 bit, "Encoder1" PDO entry 0x6100:03, 32 bit, "Encoder2" TxPDO 0x1a01 "TxPDO1-Map" PDO entry 0x6300:01, 8 bit, "HighSpeed_IN0" PDO entry 0x6300:02, 8 bit, "Ltc0_Finished" PDO entry 0x6300:03, 32 bit, "ltc_Encoder0Val" PDO entry 0x6300:04, 32 bit, "ltc_Encoder1Val" PDO entry 0x6300:05, 32 bit, "ltc_Encoder2Val" PDO entry 0x6301:01, 8 bit, "HighSpeed_IN1" PDO entry 0x6301:02, 8 bit, "Ltc1_Finished" PDO entry 0x6301:03, 32 bit, "ltc_Encoder0Val" PDO entry 0x6301:04, 32 bit, "ltc_Encoder1Val" PDO entry 0x6301:05, 32 bit, "ltc_Encoder2Val" TxPDO 0x1a02 "TxPDO2-Map" PDO entry 0x6302:01, 8 bit, "HighSpeed_IN2" PDO entry 0x6302:02, 8 bit, "Ltc2_Finished" PDO entry 0x6302:03, 32 bit, "ltc_Encoder0Val" PDO entry 0x6302:04, 32 bit, "ltc_Encoder1Val" PDO entry 0x6302:05, 32 bit, "ltc_Encoder2Val" PDO entry 0x6303:01, 8 bit, "HighSpeed_IN3" PDO entry 0x6303:02, 8 bit, "Ltc3_Finished" PDO entry 0x6303:03, 32 bit, "ltc_Encoder0Val" PDO entry 0x6303:04, 32 bit, "ltc_Encoder1Val" PDO entry 0x6303:05, 32 bit, "ltc_Encoder2Val" TxPDO 0x1a03 "TxPDO3-Map" PDO entry 0x6500:01, 8 bit, "HighSpeedOut0_Read" PDO entry 0x6500:02, 16 bit, "Cmp0_FIFO_Exist" PDO entry 0x6500:03, 16 bit, "Cmp0_Finished_Number" PDO entry 0x6500:04, 32 bit, "Cmp0_Current_CmpData" PDO entry 0x6501:01, 8 bit, "HighSpeedOut1_Read" PDO entry 0x6501:02, 16 bit, "Cmp1_FIFO_Exist" PDO entry 0x6501:03, 16 bit, "Cmp1_Finished_Number" PDO entry 0x6501:04, 32 bit, "Cmp1_Current_CmpData" PDO entry 0x6502:01, 8 bit, "HighSpeedOut2_Read" PDO entry 0x6502:02, 16 bit, "Cmp2_FIFO_Exist" PDO entry 0x6502:03, 16 bit, "Cmp2_Finished_Number" PDO entry 0x6502:04, 32 bit, "Cmp2_Current_CmpData" TxPDO 0x1a04 "TxPDO4-Map" PDO entry 0x6503:01, 8 bit, "buff0 en" PDO entry 0x6503:02, 8 bit, "buff1 en" PDO entry 0x6503:03, 8 bit, "buff2 en" PDO entry 0x6503:04, 16 bit, "buff0 space" PDO entry 0x6503:05, 16 bit, "buff1 space" PDO entry 0x6503:06, 16 bit, "buff2 space" === Master 0, Slave 1 === SM0: PhysAddr 0x1000, DefaultSize 128, ControlRegister 0x26, Enable 1 SM1: PhysAddr 0x1400, DefaultSize 128, ControlRegister 0x22, Enable 1 SM2: PhysAddr 0x1800, DefaultSize 5, ControlRegister 0x64, Enable 1 RxPDO 0x1602 "RxPDO1-Map" PDO entry 0x7000:01, 16 bit, "OUT 1" PDO entry 0x7000:02, 16 bit, "OUT 2" SM3: PhysAddr 0x1c00, DefaultSize 7, ControlRegister 0x20, Enable 1 TxPDO 0x1a00 "DI Inputs" PDO entry 0x6000:01, 1 bit, "Switch 1" PDO entry 0x6000:02, 1 bit, "Switch 2" PDO entry 0x6000:03, 1 bit, "Switch 3" PDO entry 0x6000:04, 1 bit, "Switch 4" PDO entry 0x6000:05, 1 bit, "Switch 5" PDO entry 0x6000:06, 1 bit, "Switch 6" PDO entry 0x6000:07, 1 bit, "Switch 7" PDO entry 0x6000:08, 1 bit, "Switch 8" TxPDO 0x1a03 "Motor AI Inputs" PDO entry 0x6030:01, 32 bit, "Info 1" PDO entry 0x6030:02, 16 bit, "Info 2" === Master 0, Slave 2 === SM0: PhysAddr 0x1000, DefaultSize 128, ControlRegister 0x26, Enable 1 SM1: PhysAddr 0x1400, DefaultSize 128, ControlRegister 0x22, Enable 1 SM2: PhysAddr 0x1800, DefaultSize 5, ControlRegister 0x64, Enable 1 RxPDO 0x1601 "DO Outputs" PDO entry 0x7010:01, 1 bit, "LED 1" PDO entry 0x7010:02, 1 bit, "LED 2" PDO entry 0x7010:03, 1 bit, "LED 3" PDO entry 0x7010:04, 1 bit, "LED 4" PDO entry 0x7010:05, 1 bit, "LED 5" PDO entry 0x7010:06, 1 bit, "LED 6" PDO entry 0x7010:07, 1 bit, "LED 7" PDO entry 0x7010:08, 1 bit, "LED 8" RxPDO 0x1602 "Motor Outputs" PDO entry 0x7020:01, 8 bit, "Count" PDO entry 0x7020:02, 8 bit, "Cmd" PDO entry 0x7020:03, 16 bit, "Motor Data" SM3: PhysAddr 0x1c00, DefaultSize 7, ControlRegister 0x20, Enable 1 TxPDO 0x1a00 "TxPDO1-Map" PDO entry 0x6000:01, 16 bit, "IN 1" PDO entry 0x6000:02, 16 bit, "IN 2"