Loaded HAL Components: ID Type Name PID State 36 RT hm2_eth ready Component Pins: Owner Type Dir Value Name 36 float IN -50 hm2_7i96s.0.dpll.01.timer-us 36 float IN 100 hm2_7i96s.0.dpll.02.timer-us 36 float IN 100 hm2_7i96s.0.dpll.03.timer-us 36 float IN 100 hm2_7i96s.0.dpll.04.timer-us 36 float IN 1 hm2_7i96s.0.dpll.base-freq-khz 36 u32 OUT 0x0000002A hm2_7i96s.0.dpll.ddsize 36 float OUT 6.148467 hm2_7i96s.0.dpll.phase-error-us 36 u32 IN 0x00400000 hm2_7i96s.0.dpll.plimit 36 u32 OUT 0x00000018 hm2_7i96s.0.dpll.prescale 36 u32 IN 0x000007D0 hm2_7i96s.0.dpll.time-const 36 s32 OUT 538390 hm2_7i96s.0.encoder.00.count 36 s32 OUT 0 hm2_7i96s.0.encoder.00.count-latched 36 bit I/O FALSE hm2_7i96s.0.encoder.00.index-enable <=> spindle-index-enable 36 bit OUT FALSE hm2_7i96s.0.encoder.00.input-a 36 bit OUT TRUE hm2_7i96s.0.encoder.00.input-b 36 bit OUT TRUE hm2_7i96s.0.encoder.00.input-index 36 float OUT 897.3167 hm2_7i96s.0.encoder.00.position ==> spindle-revs 36 float OUT 0 hm2_7i96s.0.encoder.00.position-latched 36 bit OUT FALSE hm2_7i96s.0.encoder.00.quad-error 36 bit IN FALSE hm2_7i96s.0.encoder.00.quad-error-enable 36 s32 OUT 538391 hm2_7i96s.0.encoder.00.rawcounts 36 s32 OUT 1 hm2_7i96s.0.encoder.00.rawlatch 36 bit IN FALSE hm2_7i96s.0.encoder.00.reset 36 float OUT 0 hm2_7i96s.0.encoder.00.velocity ==> spindle-vel-fb-rps 36 float OUT 0 hm2_7i96s.0.encoder.00.velocity-rpm ==> spindle-vel-fb-rpm 36 bit IN FALSE hm2_7i96s.0.encoder.hires-timestamp 36 u32 IN 0x017D7840 hm2_7i96s.0.encoder.sample-frequency 36 s32 IN -1 hm2_7i96s.0.encoder.timer-number 36 bit OUT TRUE hm2_7i96s.0.gpio.000.in 36 bit OUT FALSE hm2_7i96s.0.gpio.000.in_not 36 bit OUT TRUE hm2_7i96s.0.gpio.001.in 36 bit OUT FALSE hm2_7i96s.0.gpio.001.in_not 36 bit OUT FALSE hm2_7i96s.0.gpio.002.in 36 bit OUT TRUE hm2_7i96s.0.gpio.002.in_not 36 bit OUT FALSE hm2_7i96s.0.gpio.003.in 36 bit OUT TRUE hm2_7i96s.0.gpio.003.in_not 36 bit OUT FALSE hm2_7i96s.0.gpio.004.in 36 bit OUT TRUE hm2_7i96s.0.gpio.004.in_not 36 bit OUT FALSE hm2_7i96s.0.gpio.005.in 36 bit OUT TRUE hm2_7i96s.0.gpio.005.in_not 36 bit OUT FALSE hm2_7i96s.0.gpio.006.in 36 bit OUT TRUE hm2_7i96s.0.gpio.006.in_not 36 bit OUT FALSE hm2_7i96s.0.gpio.007.in 36 bit OUT TRUE hm2_7i96s.0.gpio.007.in_not 36 bit OUT FALSE hm2_7i96s.0.gpio.008.in 36 bit OUT TRUE hm2_7i96s.0.gpio.008.in_not 36 bit OUT FALSE hm2_7i96s.0.gpio.009.in ==> limit-any 36 bit OUT TRUE hm2_7i96s.0.gpio.009.in_not 36 bit OUT TRUE hm2_7i96s.0.gpio.010.in 36 bit OUT FALSE hm2_7i96s.0.gpio.010.in_not ==> remote-estop0 36 bit OUT FALSE hm2_7i96s.0.gpio.011.in 36 bit OUT TRUE hm2_7i96s.0.gpio.011.in_not 36 bit OUT FALSE hm2_7i96s.0.gpio.012.in 36 bit OUT TRUE hm2_7i96s.0.gpio.012.in_not 36 bit OUT FALSE hm2_7i96s.0.gpio.013.in 36 bit OUT TRUE hm2_7i96s.0.gpio.013.in_not 36 bit OUT FALSE hm2_7i96s.0.gpio.014.in 36 bit OUT TRUE hm2_7i96s.0.gpio.014.in_not 36 bit OUT TRUE hm2_7i96s.0.gpio.015.in 36 bit OUT FALSE hm2_7i96s.0.gpio.015.in_not 36 bit OUT TRUE hm2_7i96s.0.gpio.016.in 36 bit OUT FALSE hm2_7i96s.0.gpio.016.in_not 36 bit OUT FALSE hm2_7i96s.0.gpio.017.in 36 bit OUT TRUE hm2_7i96s.0.gpio.017.in_not 36 bit OUT FALSE hm2_7i96s.0.gpio.018.in 36 bit OUT TRUE hm2_7i96s.0.gpio.018.in_not 36 bit OUT FALSE hm2_7i96s.0.gpio.019.in 36 bit OUT TRUE hm2_7i96s.0.gpio.019.in_not 36 bit OUT FALSE hm2_7i96s.0.gpio.020.in 36 bit OUT TRUE hm2_7i96s.0.gpio.020.in_not 36 bit OUT TRUE hm2_7i96s.0.gpio.021.in 36 bit OUT FALSE hm2_7i96s.0.gpio.021.in_not 36 bit IN FALSE hm2_7i96s.0.gpio.021.out 36 bit OUT TRUE hm2_7i96s.0.gpio.022.in 36 bit OUT FALSE hm2_7i96s.0.gpio.022.in_not 36 bit IN FALSE hm2_7i96s.0.gpio.022.out 36 bit OUT TRUE hm2_7i96s.0.gpio.023.in 36 bit OUT FALSE hm2_7i96s.0.gpio.023.in_not 36 bit IN FALSE hm2_7i96s.0.gpio.023.out 36 bit OUT TRUE hm2_7i96s.0.gpio.024.in 36 bit OUT FALSE hm2_7i96s.0.gpio.024.in_not 36 bit IN FALSE hm2_7i96s.0.gpio.024.out 36 bit OUT TRUE hm2_7i96s.0.gpio.025.in 36 bit OUT FALSE hm2_7i96s.0.gpio.025.in_not 36 bit IN FALSE hm2_7i96s.0.gpio.025.out 36 bit OUT TRUE hm2_7i96s.0.gpio.026.in 36 bit OUT FALSE hm2_7i96s.0.gpio.026.in_not 36 bit IN FALSE hm2_7i96s.0.gpio.026.out 36 bit OUT FALSE hm2_7i96s.0.gpio.027.in 36 bit OUT TRUE hm2_7i96s.0.gpio.027.in_not 36 bit OUT TRUE hm2_7i96s.0.gpio.028.in 36 bit OUT FALSE hm2_7i96s.0.gpio.028.in_not 36 bit OUT FALSE hm2_7i96s.0.gpio.029.in 36 bit OUT TRUE hm2_7i96s.0.gpio.029.in_not 36 bit OUT TRUE hm2_7i96s.0.gpio.030.in 36 bit OUT FALSE hm2_7i96s.0.gpio.030.in_not 36 bit IN FALSE hm2_7i96s.0.gpio.030.out 36 bit OUT TRUE hm2_7i96s.0.gpio.031.in 36 bit OUT FALSE hm2_7i96s.0.gpio.031.in_not 36 bit IN FALSE hm2_7i96s.0.gpio.031.out 36 bit OUT TRUE hm2_7i96s.0.gpio.032.in 36 bit OUT FALSE hm2_7i96s.0.gpio.032.in_not 36 bit IN FALSE hm2_7i96s.0.gpio.032.out 36 bit OUT FALSE hm2_7i96s.0.gpio.033.in 36 bit OUT TRUE hm2_7i96s.0.gpio.033.in_not 36 bit OUT TRUE hm2_7i96s.0.gpio.034.in 36 bit OUT FALSE hm2_7i96s.0.gpio.034.in_not 36 bit IN FALSE hm2_7i96s.0.gpio.034.out 36 bit OUT TRUE hm2_7i96s.0.gpio.035.in 36 bit OUT FALSE hm2_7i96s.0.gpio.035.in_not 36 bit IN FALSE hm2_7i96s.0.gpio.035.out 36 bit OUT TRUE hm2_7i96s.0.gpio.036.in 36 bit OUT FALSE hm2_7i96s.0.gpio.036.in_not 36 bit IN FALSE hm2_7i96s.0.gpio.036.out 36 bit OUT TRUE hm2_7i96s.0.gpio.037.in 36 bit OUT FALSE hm2_7i96s.0.gpio.037.in_not 36 bit IN FALSE hm2_7i96s.0.gpio.037.out 36 bit OUT TRUE hm2_7i96s.0.gpio.038.in 36 bit OUT FALSE hm2_7i96s.0.gpio.038.in_not 36 bit IN FALSE hm2_7i96s.0.gpio.038.out 36 bit OUT TRUE hm2_7i96s.0.gpio.039.in 36 bit OUT FALSE hm2_7i96s.0.gpio.039.in_not 36 bit IN FALSE hm2_7i96s.0.gpio.039.out 36 bit OUT TRUE hm2_7i96s.0.gpio.040.in 36 bit OUT FALSE hm2_7i96s.0.gpio.040.in_not 36 bit IN FALSE hm2_7i96s.0.gpio.040.out 36 bit OUT TRUE hm2_7i96s.0.gpio.041.in 36 bit OUT FALSE hm2_7i96s.0.gpio.041.in_not 36 bit IN FALSE hm2_7i96s.0.gpio.041.out 36 bit OUT TRUE hm2_7i96s.0.gpio.042.in 36 bit OUT FALSE hm2_7i96s.0.gpio.042.in_not 36 bit IN FALSE hm2_7i96s.0.gpio.042.out 36 bit OUT TRUE hm2_7i96s.0.gpio.043.in 36 bit OUT FALSE hm2_7i96s.0.gpio.043.in_not 36 bit IN FALSE hm2_7i96s.0.gpio.043.out 36 bit OUT TRUE hm2_7i96s.0.gpio.044.in 36 bit OUT FALSE hm2_7i96s.0.gpio.044.in_not 36 bit IN FALSE hm2_7i96s.0.gpio.044.out 36 bit OUT TRUE hm2_7i96s.0.gpio.045.in 36 bit OUT FALSE hm2_7i96s.0.gpio.045.in_not 36 bit IN FALSE hm2_7i96s.0.gpio.045.out 36 bit OUT TRUE hm2_7i96s.0.gpio.046.in 36 bit OUT FALSE hm2_7i96s.0.gpio.046.in_not 36 bit IN FALSE hm2_7i96s.0.gpio.046.out 36 bit OUT TRUE hm2_7i96s.0.gpio.047.in 36 bit OUT FALSE hm2_7i96s.0.gpio.047.in_not 36 bit IN FALSE hm2_7i96s.0.gpio.047.out 36 bit OUT TRUE hm2_7i96s.0.gpio.048.in 36 bit OUT FALSE hm2_7i96s.0.gpio.048.in_not 36 bit IN FALSE hm2_7i96s.0.gpio.048.out 36 bit OUT TRUE hm2_7i96s.0.gpio.049.in 36 bit OUT FALSE hm2_7i96s.0.gpio.049.in_not 36 bit IN FALSE hm2_7i96s.0.gpio.049.out 36 bit OUT TRUE hm2_7i96s.0.gpio.050.in 36 bit OUT FALSE hm2_7i96s.0.gpio.050.in_not 36 bit IN FALSE hm2_7i96s.0.gpio.050.out 36 s32 OUT 58 hm2_7i96s.0.inm.00.enc0-count ==> ydro-in-i 36 bit IN FALSE hm2_7i96s.0.inm.00.enc0-reset 36 s32 OUT 0 hm2_7i96s.0.inm.00.enc1-count 36 bit IN FALSE hm2_7i96s.0.inm.00.enc1-reset 36 s32 OUT 0 hm2_7i96s.0.inm.00.enc2-count 36 bit IN FALSE hm2_7i96s.0.inm.00.enc2-reset 36 s32 OUT 0 hm2_7i96s.0.inm.00.enc3-count 36 bit IN FALSE hm2_7i96s.0.inm.00.enc3-reset 36 bit OUT TRUE hm2_7i96s.0.inm.00.input-00 36 bit OUT FALSE hm2_7i96s.0.inm.00.input-00-not 36 bit IN FALSE hm2_7i96s.0.inm.00.input-00-slow 36 bit OUT TRUE hm2_7i96s.0.inm.00.input-01 36 bit OUT FALSE hm2_7i96s.0.inm.00.input-01-not 36 bit IN FALSE hm2_7i96s.0.inm.00.input-01-slow 36 bit OUT FALSE hm2_7i96s.0.inm.00.input-02 36 bit OUT TRUE hm2_7i96s.0.inm.00.input-02-not 36 bit IN FALSE hm2_7i96s.0.inm.00.input-02-slow 36 bit OUT FALSE hm2_7i96s.0.inm.00.input-03 36 bit OUT TRUE hm2_7i96s.0.inm.00.input-03-not 36 bit IN FALSE hm2_7i96s.0.inm.00.input-03-slow 36 bit OUT FALSE hm2_7i96s.0.inm.00.input-04 36 bit OUT TRUE hm2_7i96s.0.inm.00.input-04-not 36 bit IN FALSE hm2_7i96s.0.inm.00.input-04-slow 36 bit OUT FALSE hm2_7i96s.0.inm.00.input-05 36 bit OUT TRUE hm2_7i96s.0.inm.00.input-05-not 36 bit IN FALSE hm2_7i96s.0.inm.00.input-05-slow 36 bit OUT FALSE hm2_7i96s.0.inm.00.input-06 36 bit OUT TRUE hm2_7i96s.0.inm.00.input-06-not 36 bit IN FALSE hm2_7i96s.0.inm.00.input-06-slow 36 bit OUT FALSE hm2_7i96s.0.inm.00.input-07 36 bit OUT TRUE hm2_7i96s.0.inm.00.input-07-not 36 bit IN FALSE hm2_7i96s.0.inm.00.input-07-slow 36 bit OUT FALSE hm2_7i96s.0.inm.00.input-08 36 bit OUT TRUE hm2_7i96s.0.inm.00.input-08-not 36 bit IN FALSE hm2_7i96s.0.inm.00.input-08-slow 36 bit OUT FALSE hm2_7i96s.0.inm.00.input-09 36 bit OUT TRUE hm2_7i96s.0.inm.00.input-09-not 36 bit IN FALSE hm2_7i96s.0.inm.00.input-09-slow 36 bit OUT TRUE hm2_7i96s.0.inm.00.input-10 36 bit OUT FALSE hm2_7i96s.0.inm.00.input-10-not 36 bit IN FALSE hm2_7i96s.0.inm.00.input-10-slow 36 bit OUT TRUE hm2_7i96s.0.inm.00.raw-input-00 36 bit OUT FALSE hm2_7i96s.0.inm.00.raw-input-00-not 36 bit OUT TRUE hm2_7i96s.0.inm.00.raw-input-01 36 bit OUT FALSE hm2_7i96s.0.inm.00.raw-input-01-not 36 bit OUT FALSE hm2_7i96s.0.inm.00.raw-input-02 36 bit OUT TRUE hm2_7i96s.0.inm.00.raw-input-02-not 36 bit OUT FALSE hm2_7i96s.0.inm.00.raw-input-03 36 bit OUT TRUE hm2_7i96s.0.inm.00.raw-input-03-not 36 bit OUT FALSE hm2_7i96s.0.inm.00.raw-input-04 36 bit OUT TRUE hm2_7i96s.0.inm.00.raw-input-04-not 36 bit OUT FALSE hm2_7i96s.0.inm.00.raw-input-05 36 bit OUT TRUE hm2_7i96s.0.inm.00.raw-input-05-not 36 bit OUT FALSE hm2_7i96s.0.inm.00.raw-input-06 36 bit OUT TRUE hm2_7i96s.0.inm.00.raw-input-06-not 36 bit OUT FALSE hm2_7i96s.0.inm.00.raw-input-07 36 bit OUT TRUE hm2_7i96s.0.inm.00.raw-input-07-not 36 bit OUT FALSE hm2_7i96s.0.inm.00.raw-input-08 36 bit OUT TRUE hm2_7i96s.0.inm.00.raw-input-08-not 36 bit OUT FALSE hm2_7i96s.0.inm.00.raw-input-09 36 bit OUT TRUE hm2_7i96s.0.inm.00.raw-input-09-not 36 bit OUT TRUE hm2_7i96s.0.inm.00.raw-input-10 36 bit OUT FALSE hm2_7i96s.0.inm.00.raw-input-10-not 36 bit IN FALSE hm2_7i96s.0.led.CR01 36 bit IN FALSE hm2_7i96s.0.led.CR02 36 bit IN FALSE hm2_7i96s.0.led.CR03 36 bit IN FALSE hm2_7i96s.0.led.CR04 36 bit IN FALSE hm2_7i96s.0.outm.00.invert-04 36 bit IN FALSE hm2_7i96s.0.outm.00.invert-05 36 bit IN FALSE hm2_7i96s.0.outm.00.out-04 36 bit IN FALSE hm2_7i96s.0.outm.00.out-05 36 bit OUT FALSE hm2_7i96s.0.packet-error 36 bit OUT FALSE hm2_7i96s.0.packet-error-exceeded 36 s32 OUT 0 hm2_7i96s.0.packet-error-level 36 u32 I/O 0x00000013 hm2_7i96s.0.packet-error-total 36 bit IN FALSE hm2_7i96s.0.pwmgen.00.enable <== spindle-enable 36 float IN 0 hm2_7i96s.0.pwmgen.00.value <== spindle-output 36 s32 OUT 0 hm2_7i96s.0.read-request.time 36 s32 OUT 1591240 hm2_7i96s.0.read.time 36 bit IN FALSE hm2_7i96s.0.ssr.00.invert-00 36 bit IN FALSE hm2_7i96s.0.ssr.00.invert-01 36 bit IN FALSE hm2_7i96s.0.ssr.00.invert-02 36 bit IN FALSE hm2_7i96s.0.ssr.00.invert-03 36 bit IN FALSE hm2_7i96s.0.ssr.00.out-00 36 bit IN FALSE hm2_7i96s.0.ssr.00.out-01 36 bit IN FALSE hm2_7i96s.0.ssr.00.out-02 36 bit IN FALSE hm2_7i96s.0.ssr.00.out-03 36 u32 IN 0x000F4240 hm2_7i96s.0.ssr.00.rate 36 bit IN TRUE hm2_7i96s.0.stepgen.00.control-type 36 s32 OUT 0 hm2_7i96s.0.stepgen.00.counts 36 float OUT 0 hm2_7i96s.0.stepgen.00.dbg_err_at_match 36 float OUT 0 hm2_7i96s.0.stepgen.00.dbg_ff_vel 36 float OUT 0 hm2_7i96s.0.stepgen.00.dbg_pos_minus_prev_cmd 36 float OUT 0 hm2_7i96s.0.stepgen.00.dbg_s_to_match 36 s32 OUT 0 hm2_7i96s.0.stepgen.00.dbg_step_rate 36 float OUT 0 hm2_7i96s.0.stepgen.00.dbg_vel_error 36 bit IN TRUE hm2_7i96s.0.stepgen.00.enable <== z-enable 36 float IN 0 hm2_7i96s.0.stepgen.00.position-cmd 36 float OUT 0 hm2_7i96s.0.stepgen.00.position-fb ==> z-pos-fb 36 bit IN FALSE hm2_7i96s.0.stepgen.00.position-reset 36 float IN 0 hm2_7i96s.0.stepgen.00.velocity-cmd <== z-output 36 float OUT 0 hm2_7i96s.0.stepgen.00.velocity-fb 36 bit IN TRUE hm2_7i96s.0.stepgen.01.control-type 36 s32 OUT 0 hm2_7i96s.0.stepgen.01.counts 36 float OUT 0 hm2_7i96s.0.stepgen.01.dbg_err_at_match 36 float OUT 0 hm2_7i96s.0.stepgen.01.dbg_ff_vel 36 float OUT 0 hm2_7i96s.0.stepgen.01.dbg_pos_minus_prev_cmd 36 float OUT 0 hm2_7i96s.0.stepgen.01.dbg_s_to_match 36 s32 OUT 0 hm2_7i96s.0.stepgen.01.dbg_step_rate 36 float OUT 0 hm2_7i96s.0.stepgen.01.dbg_vel_error 36 bit IN TRUE hm2_7i96s.0.stepgen.01.enable <== x-enable 36 float IN 0 hm2_7i96s.0.stepgen.01.position-cmd 36 float OUT -0 hm2_7i96s.0.stepgen.01.position-fb ==> x-pos-fb 36 bit IN FALSE hm2_7i96s.0.stepgen.01.position-reset 36 float IN 0 hm2_7i96s.0.stepgen.01.velocity-cmd <== x-output 36 float OUT 0 hm2_7i96s.0.stepgen.01.velocity-fb 36 s32 IN 1 hm2_7i96s.0.stepgen.timer-number 36 bit I/O FALSE hm2_7i96s.0.watchdog.has_bit 36 s32 OUT 52588 hm2_7i96s.0.write.time Pin Aliases: Alias Original Name Signals: Type Value Name (linked to) Parameters: Owner Type Dir Value Name 36 bit RW FALSE hm2_7i96s.0.encoder.00.counter-mode 36 bit RW TRUE hm2_7i96s.0.encoder.00.filter 36 bit RW FALSE hm2_7i96s.0.encoder.00.index-invert 36 bit RW FALSE hm2_7i96s.0.encoder.00.index-mask 36 bit RW FALSE hm2_7i96s.0.encoder.00.index-mask-invert 36 float RW 600 hm2_7i96s.0.encoder.00.scale 36 float RW 0.5 hm2_7i96s.0.encoder.00.vel-timeout 36 bit RW FALSE hm2_7i96s.0.gpio.011.invert_output 36 bit RW FALSE hm2_7i96s.0.gpio.011.is_opendrain 36 bit RW FALSE hm2_7i96s.0.gpio.012.invert_output 36 bit RW FALSE hm2_7i96s.0.gpio.012.is_opendrain 36 bit RW FALSE hm2_7i96s.0.gpio.013.invert_output 36 bit RW FALSE hm2_7i96s.0.gpio.013.is_opendrain 36 bit RW FALSE hm2_7i96s.0.gpio.014.invert_output 36 bit RW FALSE hm2_7i96s.0.gpio.014.is_opendrain 36 bit RW FALSE hm2_7i96s.0.gpio.015.invert_output 36 bit RW FALSE hm2_7i96s.0.gpio.015.is_opendrain 36 bit RW FALSE hm2_7i96s.0.gpio.016.invert_output 36 bit RW FALSE hm2_7i96s.0.gpio.016.is_opendrain 36 bit RW FALSE hm2_7i96s.0.gpio.021.invert_output 36 bit RW FALSE hm2_7i96s.0.gpio.021.is_opendrain 36 bit RW FALSE hm2_7i96s.0.gpio.021.is_output 36 bit RW FALSE hm2_7i96s.0.gpio.022.invert_output 36 bit RW FALSE hm2_7i96s.0.gpio.022.is_opendrain 36 bit RW FALSE hm2_7i96s.0.gpio.022.is_output 36 bit RW FALSE hm2_7i96s.0.gpio.023.invert_output 36 bit RW FALSE hm2_7i96s.0.gpio.023.is_opendrain 36 bit RW FALSE hm2_7i96s.0.gpio.023.is_output 36 bit RW FALSE hm2_7i96s.0.gpio.024.invert_output 36 bit RW FALSE hm2_7i96s.0.gpio.024.is_opendrain 36 bit RW FALSE hm2_7i96s.0.gpio.024.is_output 36 bit RW FALSE hm2_7i96s.0.gpio.025.invert_output 36 bit RW FALSE hm2_7i96s.0.gpio.025.is_opendrain 36 bit RW FALSE hm2_7i96s.0.gpio.025.is_output 36 bit RW FALSE hm2_7i96s.0.gpio.026.invert_output 36 bit RW FALSE hm2_7i96s.0.gpio.026.is_opendrain 36 bit RW FALSE hm2_7i96s.0.gpio.026.is_output 36 bit RW FALSE hm2_7i96s.0.gpio.030.invert_output 36 bit RW FALSE hm2_7i96s.0.gpio.030.is_opendrain 36 bit RW FALSE hm2_7i96s.0.gpio.030.is_output 36 bit RW FALSE hm2_7i96s.0.gpio.031.invert_output 36 bit RW FALSE hm2_7i96s.0.gpio.031.is_opendrain 36 bit RW FALSE hm2_7i96s.0.gpio.031.is_output 36 bit RW FALSE hm2_7i96s.0.gpio.032.invert_output 36 bit RW FALSE hm2_7i96s.0.gpio.032.is_opendrain 36 bit RW FALSE hm2_7i96s.0.gpio.032.is_output 36 bit RW FALSE hm2_7i96s.0.gpio.033.invert_output 36 bit RW FALSE hm2_7i96s.0.gpio.033.is_opendrain 36 bit RW FALSE hm2_7i96s.0.gpio.034.invert_output 36 bit RW FALSE hm2_7i96s.0.gpio.034.is_opendrain 36 bit RW FALSE hm2_7i96s.0.gpio.034.is_output 36 bit RW FALSE hm2_7i96s.0.gpio.035.invert_output 36 bit RW FALSE hm2_7i96s.0.gpio.035.is_opendrain 36 bit RW FALSE hm2_7i96s.0.gpio.035.is_output 36 bit RW FALSE hm2_7i96s.0.gpio.036.invert_output 36 bit RW FALSE hm2_7i96s.0.gpio.036.is_opendrain 36 bit RW FALSE hm2_7i96s.0.gpio.036.is_output 36 bit RW FALSE hm2_7i96s.0.gpio.037.invert_output 36 bit RW FALSE hm2_7i96s.0.gpio.037.is_opendrain 36 bit RW FALSE hm2_7i96s.0.gpio.037.is_output 36 bit RW FALSE hm2_7i96s.0.gpio.038.invert_output 36 bit RW FALSE hm2_7i96s.0.gpio.038.is_opendrain 36 bit RW FALSE hm2_7i96s.0.gpio.038.is_output 36 bit RW FALSE hm2_7i96s.0.gpio.039.invert_output 36 bit RW FALSE hm2_7i96s.0.gpio.039.is_opendrain 36 bit RW FALSE hm2_7i96s.0.gpio.039.is_output 36 bit RW FALSE hm2_7i96s.0.gpio.040.invert_output 36 bit RW FALSE hm2_7i96s.0.gpio.040.is_opendrain 36 bit RW FALSE hm2_7i96s.0.gpio.040.is_output 36 bit RW FALSE hm2_7i96s.0.gpio.041.invert_output 36 bit RW FALSE hm2_7i96s.0.gpio.041.is_opendrain 36 bit RW FALSE hm2_7i96s.0.gpio.041.is_output 36 bit RW FALSE hm2_7i96s.0.gpio.042.invert_output 36 bit RW FALSE hm2_7i96s.0.gpio.042.is_opendrain 36 bit RW FALSE hm2_7i96s.0.gpio.042.is_output 36 bit RW FALSE hm2_7i96s.0.gpio.043.invert_output 36 bit RW FALSE hm2_7i96s.0.gpio.043.is_opendrain 36 bit RW FALSE hm2_7i96s.0.gpio.043.is_output 36 bit RW FALSE hm2_7i96s.0.gpio.044.invert_output 36 bit RW FALSE hm2_7i96s.0.gpio.044.is_opendrain 36 bit RW FALSE hm2_7i96s.0.gpio.044.is_output 36 bit RW FALSE hm2_7i96s.0.gpio.045.invert_output 36 bit RW FALSE hm2_7i96s.0.gpio.045.is_opendrain 36 bit RW FALSE hm2_7i96s.0.gpio.045.is_output 36 bit RW FALSE hm2_7i96s.0.gpio.046.invert_output 36 bit RW FALSE hm2_7i96s.0.gpio.046.is_opendrain 36 bit RW FALSE hm2_7i96s.0.gpio.046.is_output 36 bit RW FALSE hm2_7i96s.0.gpio.047.invert_output 36 bit RW FALSE hm2_7i96s.0.gpio.047.is_opendrain 36 bit RW FALSE hm2_7i96s.0.gpio.047.is_output 36 bit RW FALSE hm2_7i96s.0.gpio.048.invert_output 36 bit RW FALSE hm2_7i96s.0.gpio.048.is_opendrain 36 bit RW FALSE hm2_7i96s.0.gpio.048.is_output 36 bit RW FALSE hm2_7i96s.0.gpio.049.invert_output 36 bit RW FALSE hm2_7i96s.0.gpio.049.is_opendrain 36 bit RW FALSE hm2_7i96s.0.gpio.049.is_output 36 bit RW FALSE hm2_7i96s.0.gpio.050.invert_output 36 bit RW FALSE hm2_7i96s.0.gpio.050.is_opendrain 36 bit RW FALSE hm2_7i96s.0.gpio.050.is_output 36 bit RW FALSE hm2_7i96s.0.inm.00.enc0_4xmode 36 bit RW FALSE hm2_7i96s.0.inm.00.enc1_4xmode 36 bit RW FALSE hm2_7i96s.0.inm.00.enc2_4xmode 36 bit RW FALSE hm2_7i96s.0.inm.00.enc3_4xmode 36 u32 RW 0x00000005 hm2_7i96s.0.inm.00.fast_scans 36 u32 RW 0x00004E20 hm2_7i96s.0.inm.00.scan_rate 36 u32 RO 0x0000000B hm2_7i96s.0.inm.00.scan_width 36 u32 RW 0x000001F4 hm2_7i96s.0.inm.00.slow_scans 36 bit RW FALSE hm2_7i96s.0.io_error 36 s32 RO 1 hm2_7i96s.0.packet-error-decrement 36 s32 RW 2 hm2_7i96s.0.packet-error-increment 36 s32 RW 10 hm2_7i96s.0.packet-error-limit 36 s32 RW 80 hm2_7i96s.0.packet-read-timeout 36 bit RW FALSE hm2_7i96s.0.pwmgen.00.offset-mode 36 s32 RW 1 hm2_7i96s.0.pwmgen.00.output-type 36 float RW 5000 hm2_7i96s.0.pwmgen.00.scale 36 u32 RW 0x005B8D80 hm2_7i96s.0.pwmgen.pdm_frequency 36 u32 RW 0x00004E20 hm2_7i96s.0.pwmgen.pwm_frequency 36 s32 RW 0 hm2_7i96s.0.read-request.tmax 36 bit RO FALSE hm2_7i96s.0.read-request.tmax-increased 36 s32 RW 2391276 hm2_7i96s.0.read.tmax 36 bit RO FALSE hm2_7i96s.0.read.tmax-increased 36 bit RW FALSE hm2_7i96s.0.stepgen.00.direction.invert_output 36 bit RW FALSE hm2_7i96s.0.stepgen.00.direction.is_opendrain 36 u32 RW 0x00002710 hm2_7i96s.0.stepgen.00.dirhold 36 u32 RW 0x00002710 hm2_7i96s.0.stepgen.00.dirsetup 36 float RW 37.5 hm2_7i96s.0.stepgen.00.maxaccel 36 float RW 1.25 hm2_7i96s.0.stepgen.00.maxvel 36 float RW 10000 hm2_7i96s.0.stepgen.00.position-scale 36 bit RW FALSE hm2_7i96s.0.stepgen.00.step.invert_output 36 bit RW FALSE hm2_7i96s.0.stepgen.00.step.is_opendrain 36 u32 RW 0x00000000 hm2_7i96s.0.stepgen.00.step_type 36 u32 RW 0x00001388 hm2_7i96s.0.stepgen.00.steplen 36 u32 RW 0x00001388 hm2_7i96s.0.stepgen.00.stepspace 36 u32 RW 0x00000000 hm2_7i96s.0.stepgen.00.table-data-0 36 u32 RW 0x00000000 hm2_7i96s.0.stepgen.00.table-data-1 36 u32 RW 0x00000000 hm2_7i96s.0.stepgen.00.table-data-2 36 u32 RW 0x00000000 hm2_7i96s.0.stepgen.00.table-data-3 36 bit RW FALSE hm2_7i96s.0.stepgen.01.direction.invert_output 36 bit RW FALSE hm2_7i96s.0.stepgen.01.direction.is_opendrain 36 u32 RW 0x00002710 hm2_7i96s.0.stepgen.01.dirhold 36 u32 RW 0x00002710 hm2_7i96s.0.stepgen.01.dirsetup 36 float RW 60 hm2_7i96s.0.stepgen.01.maxaccel 36 float RW 1.25 hm2_7i96s.0.stepgen.01.maxvel 36 float RW -48077 hm2_7i96s.0.stepgen.01.position-scale 36 bit RW FALSE hm2_7i96s.0.stepgen.01.step.invert_output 36 bit RW FALSE hm2_7i96s.0.stepgen.01.step.is_opendrain 36 u32 RW 0x00000000 hm2_7i96s.0.stepgen.01.step_type 36 u32 RW 0x00001388 hm2_7i96s.0.stepgen.01.steplen 36 u32 RW 0x00001388 hm2_7i96s.0.stepgen.01.stepspace 36 u32 RW 0x00000000 hm2_7i96s.0.stepgen.01.table-data-0 36 u32 RW 0x00000000 hm2_7i96s.0.stepgen.01.table-data-1 36 u32 RW 0x00000000 hm2_7i96s.0.stepgen.01.table-data-2 36 u32 RW 0x00000000 hm2_7i96s.0.stepgen.01.table-data-3 36 u32 RW 0x004C4B40 hm2_7i96s.0.watchdog.timeout_ns 36 s32 RW 700120 hm2_7i96s.0.write.tmax 36 bit RO FALSE hm2_7i96s.0.write.tmax-increased Parameter Aliases: Alias Original Name hm2_7i96s.0.stepgen.00.direction.invert_output hm2_7i96s.0.gpio.018.invert_output hm2_7i96s.0.stepgen.00.direction.is_opendrain hm2_7i96s.0.gpio.018.is_opendrain hm2_7i96s.0.stepgen.00.step.invert_output hm2_7i96s.0.gpio.017.invert_output hm2_7i96s.0.stepgen.00.step.is_opendrain hm2_7i96s.0.gpio.017.is_opendrain hm2_7i96s.0.stepgen.01.direction.invert_output hm2_7i96s.0.gpio.020.invert_output hm2_7i96s.0.stepgen.01.direction.is_opendrain hm2_7i96s.0.gpio.020.is_opendrain hm2_7i96s.0.stepgen.01.step.invert_output hm2_7i96s.0.gpio.019.invert_output hm2_7i96s.0.stepgen.01.step.is_opendrain hm2_7i96s.0.gpio.019.is_opendrain Exported Functions: Owner CodeAddr Arg FP Users Name 00036 7f1ad0010908 557782136b70 YES 1 hm2_7i96s.0.read 00036 7f1ad0010891 557782136b70 YES 0 hm2_7i96s.0.read-request 00036 7f1ad0010749 557782136b70 YES 1 hm2_7i96s.0.write Realtime Threads: Period FP Name ( Time, Max-Time )