Loaded HAL Components: ID Type Name PID State 33 RT hm2_eth ready Component Pins: Owner Type Dir Value Name 33 s32 OUT 2098000000 hm2_7i96s.0.0.debug 33 u32 IN 0x00000000 hm2_7i96s.0.7i73.0.0.display 33 s32 OUT 0 hm2_7i96s.0.7i73.0.0.enc0.count 33 bit I/O FALSE hm2_7i96s.0.7i73.0.0.enc0.index-enable 33 float OUT 0 hm2_7i96s.0.7i73.0.0.enc0.position 33 s32 OUT 0 hm2_7i96s.0.7i73.0.0.enc0.rawcounts 33 bit I/O FALSE hm2_7i96s.0.7i73.0.0.enc0.reset 33 s32 OUT 0 hm2_7i96s.0.7i73.0.0.enc1.count 33 bit I/O FALSE hm2_7i96s.0.7i73.0.0.enc1.index-enable 33 float OUT 0 hm2_7i96s.0.7i73.0.0.enc1.position 33 s32 OUT 0 hm2_7i96s.0.7i73.0.0.enc1.rawcounts 33 bit I/O FALSE hm2_7i96s.0.7i73.0.0.enc1.reset 33 s32 OUT 0 hm2_7i96s.0.7i73.0.0.enc2.count 33 bit I/O FALSE hm2_7i96s.0.7i73.0.0.enc2.index-enable 33 float OUT 0 hm2_7i96s.0.7i73.0.0.enc2.position 33 s32 OUT 0 hm2_7i96s.0.7i73.0.0.enc2.rawcounts 33 bit I/O FALSE hm2_7i96s.0.7i73.0.0.enc2.reset 33 s32 OUT 0 hm2_7i96s.0.7i73.0.0.enc3.count 33 bit I/O FALSE hm2_7i96s.0.7i73.0.0.enc3.index-enable 33 float OUT 0 hm2_7i96s.0.7i73.0.0.enc3.position 33 s32 OUT 0 hm2_7i96s.0.7i73.0.0.enc3.rawcounts 33 bit I/O FALSE hm2_7i96s.0.7i73.0.0.enc3.reset 33 bit OUT FALSE hm2_7i96s.0.7i73.0.0.input-00 33 bit OUT TRUE hm2_7i96s.0.7i73.0.0.input-00-not 33 bit OUT FALSE hm2_7i96s.0.7i73.0.0.input-01 33 bit OUT TRUE hm2_7i96s.0.7i73.0.0.input-01-not 33 bit OUT FALSE hm2_7i96s.0.7i73.0.0.input-02 33 bit OUT TRUE hm2_7i96s.0.7i73.0.0.input-02-not 33 bit OUT FALSE hm2_7i96s.0.7i73.0.0.input-03 33 bit OUT TRUE hm2_7i96s.0.7i73.0.0.input-03-not 33 bit OUT FALSE hm2_7i96s.0.7i73.0.0.input-04 33 bit OUT TRUE hm2_7i96s.0.7i73.0.0.input-04-not 33 bit OUT FALSE hm2_7i96s.0.7i73.0.0.input-05 33 bit OUT TRUE hm2_7i96s.0.7i73.0.0.input-05-not 33 bit OUT FALSE hm2_7i96s.0.7i73.0.0.input-06 33 bit OUT TRUE hm2_7i96s.0.7i73.0.0.input-06-not 33 bit OUT FALSE hm2_7i96s.0.7i73.0.0.input-07 33 bit OUT TRUE hm2_7i96s.0.7i73.0.0.input-07-not 33 bit OUT TRUE hm2_7i96s.0.7i73.0.0.input-08 33 bit OUT FALSE hm2_7i96s.0.7i73.0.0.input-08-not 33 bit OUT TRUE hm2_7i96s.0.7i73.0.0.input-09 33 bit OUT FALSE hm2_7i96s.0.7i73.0.0.input-09-not 33 bit OUT TRUE hm2_7i96s.0.7i73.0.0.input-10 33 bit OUT FALSE hm2_7i96s.0.7i73.0.0.input-10-not 33 bit OUT TRUE hm2_7i96s.0.7i73.0.0.input-11 33 bit OUT FALSE hm2_7i96s.0.7i73.0.0.input-11-not 33 bit OUT TRUE hm2_7i96s.0.7i73.0.0.input-12 33 bit OUT FALSE hm2_7i96s.0.7i73.0.0.input-12-not 33 bit OUT TRUE hm2_7i96s.0.7i73.0.0.input-13 33 bit OUT FALSE hm2_7i96s.0.7i73.0.0.input-13-not 33 bit OUT TRUE hm2_7i96s.0.7i73.0.0.input-14 33 bit OUT FALSE hm2_7i96s.0.7i73.0.0.input-14-not 33 bit OUT TRUE hm2_7i96s.0.7i73.0.0.input-15 33 bit OUT FALSE hm2_7i96s.0.7i73.0.0.input-15-not 33 u32 OUT 0x00000040 hm2_7i96s.0.7i73.0.0.keycode 33 bit IN FALSE hm2_7i96s.0.7i73.0.0.output-00 33 bit IN FALSE hm2_7i96s.0.7i73.0.0.output-01 33 bit IN FALSE hm2_7i96s.0.7i73.0.0.output-02 33 bit IN FALSE hm2_7i96s.0.7i73.0.0.output-03 33 bit IN FALSE hm2_7i96s.0.7i73.0.0.output-04 33 bit IN FALSE hm2_7i96s.0.7i73.0.0.output-05 33 bit IN FALSE hm2_7i96s.0.7i73.0.0.output-06 33 bit IN FALSE hm2_7i96s.0.7i73.0.0.output-07 33 bit IN FALSE hm2_7i96s.0.7i73.0.0.output-08 33 bit IN FALSE hm2_7i96s.0.7i73.0.0.output-09 33 bit OUT FALSE hm2_7i96s.0.7i76.0.1.input-00 33 bit OUT TRUE hm2_7i96s.0.7i76.0.1.input-00-not 33 bit OUT FALSE hm2_7i96s.0.7i76.0.1.input-01 33 bit OUT TRUE hm2_7i96s.0.7i76.0.1.input-01-not 33 bit OUT FALSE hm2_7i96s.0.7i76.0.1.input-02 33 bit OUT TRUE hm2_7i96s.0.7i76.0.1.input-02-not 33 bit OUT FALSE hm2_7i96s.0.7i76.0.1.input-03 33 bit OUT TRUE hm2_7i96s.0.7i76.0.1.input-03-not 33 bit OUT FALSE hm2_7i96s.0.7i76.0.1.input-04 33 bit OUT TRUE hm2_7i96s.0.7i76.0.1.input-04-not 33 bit OUT FALSE hm2_7i96s.0.7i76.0.1.input-05 33 bit OUT TRUE hm2_7i96s.0.7i76.0.1.input-05-not 33 bit OUT FALSE hm2_7i96s.0.7i76.0.1.input-06 33 bit OUT TRUE hm2_7i96s.0.7i76.0.1.input-06-not 33 bit OUT FALSE hm2_7i96s.0.7i76.0.1.input-07 33 bit OUT TRUE hm2_7i96s.0.7i76.0.1.input-07-not 33 bit OUT FALSE hm2_7i96s.0.7i76.0.1.input-08 33 bit OUT TRUE hm2_7i96s.0.7i76.0.1.input-08-not 33 bit OUT FALSE hm2_7i96s.0.7i76.0.1.input-09 33 bit OUT TRUE hm2_7i96s.0.7i76.0.1.input-09-not 33 bit OUT FALSE hm2_7i96s.0.7i76.0.1.input-10 33 bit OUT TRUE hm2_7i96s.0.7i76.0.1.input-10-not 33 bit OUT FALSE hm2_7i96s.0.7i76.0.1.input-11 33 bit OUT TRUE hm2_7i96s.0.7i76.0.1.input-11-not 33 bit OUT FALSE hm2_7i96s.0.7i76.0.1.input-12 33 bit OUT TRUE hm2_7i96s.0.7i76.0.1.input-12-not 33 bit OUT FALSE hm2_7i96s.0.7i76.0.1.input-13 33 bit OUT TRUE hm2_7i96s.0.7i76.0.1.input-13-not 33 bit OUT FALSE hm2_7i96s.0.7i76.0.1.input-14 33 bit OUT TRUE hm2_7i96s.0.7i76.0.1.input-14-not 33 bit OUT FALSE hm2_7i96s.0.7i76.0.1.input-15 33 bit OUT TRUE hm2_7i96s.0.7i76.0.1.input-15-not 33 bit OUT FALSE hm2_7i96s.0.7i76.0.1.input-16 33 bit OUT TRUE hm2_7i96s.0.7i76.0.1.input-16-not 33 bit OUT FALSE hm2_7i96s.0.7i76.0.1.input-17 33 bit OUT TRUE hm2_7i96s.0.7i76.0.1.input-17-not 33 bit OUT FALSE hm2_7i96s.0.7i76.0.1.input-18 33 bit OUT TRUE hm2_7i96s.0.7i76.0.1.input-18-not 33 bit OUT FALSE hm2_7i96s.0.7i76.0.1.input-19 33 bit OUT TRUE hm2_7i96s.0.7i76.0.1.input-19-not 33 bit OUT FALSE hm2_7i96s.0.7i76.0.1.input-20 33 bit OUT TRUE hm2_7i96s.0.7i76.0.1.input-20-not 33 bit OUT FALSE hm2_7i96s.0.7i76.0.1.input-21 33 bit OUT TRUE hm2_7i96s.0.7i76.0.1.input-21-not 33 bit OUT FALSE hm2_7i96s.0.7i76.0.1.input-22 33 bit OUT TRUE hm2_7i96s.0.7i76.0.1.input-22-not 33 bit OUT FALSE hm2_7i96s.0.7i76.0.1.input-23 33 bit OUT TRUE hm2_7i96s.0.7i76.0.1.input-23-not 33 bit OUT FALSE hm2_7i96s.0.7i76.0.1.input-24 33 bit OUT TRUE hm2_7i96s.0.7i76.0.1.input-24-not 33 bit OUT FALSE hm2_7i96s.0.7i76.0.1.input-25 33 bit OUT TRUE hm2_7i96s.0.7i76.0.1.input-25-not 33 bit OUT FALSE hm2_7i96s.0.7i76.0.1.input-26 33 bit OUT TRUE hm2_7i96s.0.7i76.0.1.input-26-not 33 bit OUT FALSE hm2_7i96s.0.7i76.0.1.input-27 33 bit OUT TRUE hm2_7i96s.0.7i76.0.1.input-27-not 33 bit OUT FALSE hm2_7i96s.0.7i76.0.1.input-28 33 bit OUT TRUE hm2_7i96s.0.7i76.0.1.input-28-not 33 bit OUT FALSE hm2_7i96s.0.7i76.0.1.input-29 33 bit OUT TRUE hm2_7i96s.0.7i76.0.1.input-29-not 33 bit OUT FALSE hm2_7i96s.0.7i76.0.1.input-30 33 bit OUT TRUE hm2_7i96s.0.7i76.0.1.input-30-not 33 bit OUT FALSE hm2_7i96s.0.7i76.0.1.input-31 33 bit OUT TRUE hm2_7i96s.0.7i76.0.1.input-31-not 33 bit IN FALSE hm2_7i96s.0.7i76.0.1.output-00 33 bit IN FALSE hm2_7i96s.0.7i76.0.1.output-01 33 bit IN FALSE hm2_7i96s.0.7i76.0.1.output-02 33 bit IN FALSE hm2_7i96s.0.7i76.0.1.output-03 33 bit IN FALSE hm2_7i96s.0.7i76.0.1.output-04 33 bit IN FALSE hm2_7i96s.0.7i76.0.1.output-05 33 bit IN FALSE hm2_7i96s.0.7i76.0.1.output-06 33 bit IN FALSE hm2_7i96s.0.7i76.0.1.output-07 33 bit IN FALSE hm2_7i96s.0.7i76.0.1.output-08 33 bit IN FALSE hm2_7i96s.0.7i76.0.1.output-09 33 bit IN FALSE hm2_7i96s.0.7i76.0.1.output-10 33 bit IN FALSE hm2_7i96s.0.7i76.0.1.output-11 33 bit IN FALSE hm2_7i96s.0.7i76.0.1.output-12 33 bit IN FALSE hm2_7i96s.0.7i76.0.1.output-13 33 bit IN FALSE hm2_7i96s.0.7i76.0.1.output-14 33 bit IN FALSE hm2_7i96s.0.7i76.0.1.output-15 33 bit IN FALSE hm2_7i96s.0.7i76.0.1.spindir 33 bit IN FALSE hm2_7i96s.0.7i76.0.1.spinena 33 float IN 0 hm2_7i96s.0.7i76.0.1.spinout 33 float IN -50 hm2_7i96s.0.dpll.01.timer-us 33 float IN 100 hm2_7i96s.0.dpll.02.timer-us 33 float IN 100 hm2_7i96s.0.dpll.03.timer-us 33 float IN 100 hm2_7i96s.0.dpll.04.timer-us 33 float IN 1 hm2_7i96s.0.dpll.base-freq-khz 33 u32 OUT 0x0000002A hm2_7i96s.0.dpll.ddsize 33 float OUT 5.357122 hm2_7i96s.0.dpll.phase-error-us 33 u32 IN 0x00400000 hm2_7i96s.0.dpll.plimit 33 u32 OUT 0x00000018 hm2_7i96s.0.dpll.prescale 33 u32 IN 0x000007D0 hm2_7i96s.0.dpll.time-const 33 s32 OUT 0 hm2_7i96s.0.encoder.00.count 33 s32 OUT 0 hm2_7i96s.0.encoder.00.count-latched 33 bit I/O FALSE hm2_7i96s.0.encoder.00.index-enable <=> spindle-index-enable 33 bit OUT TRUE hm2_7i96s.0.encoder.00.input-a 33 bit OUT TRUE hm2_7i96s.0.encoder.00.input-b 33 bit OUT TRUE hm2_7i96s.0.encoder.00.input-index 33 float OUT 0 hm2_7i96s.0.encoder.00.position 33 float OUT 0 hm2_7i96s.0.encoder.00.position-latched 33 bit OUT FALSE hm2_7i96s.0.encoder.00.quad-error 33 bit IN FALSE hm2_7i96s.0.encoder.00.quad-error-enable 33 s32 OUT 0 hm2_7i96s.0.encoder.00.rawcounts 33 s32 OUT 0 hm2_7i96s.0.encoder.00.rawlatch 33 bit IN FALSE hm2_7i96s.0.encoder.00.reset 33 float OUT 0 hm2_7i96s.0.encoder.00.velocity 33 float OUT 0 hm2_7i96s.0.encoder.00.velocity-rpm 33 s32 OUT 0 hm2_7i96s.0.encoder.01.count 33 s32 OUT 0 hm2_7i96s.0.encoder.01.count-latched 33 bit I/O FALSE hm2_7i96s.0.encoder.01.index-enable 33 bit OUT TRUE hm2_7i96s.0.encoder.01.input-a 33 bit OUT TRUE hm2_7i96s.0.encoder.01.input-b 33 bit OUT FALSE hm2_7i96s.0.encoder.01.input-index 33 float OUT 0 hm2_7i96s.0.encoder.01.position 33 float OUT 0 hm2_7i96s.0.encoder.01.position-latched 33 bit OUT FALSE hm2_7i96s.0.encoder.01.quad-error 33 bit IN FALSE hm2_7i96s.0.encoder.01.quad-error-enable 33 s32 OUT 0 hm2_7i96s.0.encoder.01.rawcounts 33 s32 OUT 0 hm2_7i96s.0.encoder.01.rawlatch 33 bit IN FALSE hm2_7i96s.0.encoder.01.reset 33 float OUT 0 hm2_7i96s.0.encoder.01.velocity 33 float OUT 0 hm2_7i96s.0.encoder.01.velocity-rpm 33 bit IN FALSE hm2_7i96s.0.encoder.hires-timestamp 33 u32 IN 0x017D7840 hm2_7i96s.0.encoder.sample-frequency 33 s32 IN -1 hm2_7i96s.0.encoder.timer-number 33 bit OUT FALSE hm2_7i96s.0.gpio.000.in 33 bit OUT TRUE hm2_7i96s.0.gpio.000.in_not 33 bit OUT FALSE hm2_7i96s.0.gpio.001.in 33 bit OUT TRUE hm2_7i96s.0.gpio.001.in_not 33 bit OUT FALSE hm2_7i96s.0.gpio.002.in 33 bit OUT TRUE hm2_7i96s.0.gpio.002.in_not 33 bit OUT FALSE hm2_7i96s.0.gpio.003.in 33 bit OUT TRUE hm2_7i96s.0.gpio.003.in_not 33 bit OUT FALSE hm2_7i96s.0.gpio.004.in 33 bit OUT TRUE hm2_7i96s.0.gpio.004.in_not 33 bit OUT FALSE hm2_7i96s.0.gpio.005.in 33 bit OUT TRUE hm2_7i96s.0.gpio.005.in_not 33 bit OUT FALSE hm2_7i96s.0.gpio.006.in 33 bit OUT TRUE hm2_7i96s.0.gpio.006.in_not 33 bit OUT FALSE hm2_7i96s.0.gpio.007.in 33 bit OUT TRUE hm2_7i96s.0.gpio.007.in_not 33 bit OUT FALSE hm2_7i96s.0.gpio.008.in 33 bit OUT TRUE hm2_7i96s.0.gpio.008.in_not 33 bit OUT FALSE hm2_7i96s.0.gpio.009.in 33 bit OUT TRUE hm2_7i96s.0.gpio.009.in_not 33 bit OUT FALSE hm2_7i96s.0.gpio.010.in 33 bit OUT TRUE hm2_7i96s.0.gpio.010.in_not 33 bit OUT FALSE hm2_7i96s.0.gpio.011.in 33 bit OUT TRUE hm2_7i96s.0.gpio.011.in_not 33 bit OUT FALSE hm2_7i96s.0.gpio.012.in 33 bit OUT TRUE hm2_7i96s.0.gpio.012.in_not 33 bit OUT FALSE hm2_7i96s.0.gpio.013.in 33 bit OUT TRUE hm2_7i96s.0.gpio.013.in_not 33 bit OUT FALSE hm2_7i96s.0.gpio.014.in 33 bit OUT TRUE hm2_7i96s.0.gpio.014.in_not 33 bit OUT TRUE hm2_7i96s.0.gpio.015.in 33 bit OUT FALSE hm2_7i96s.0.gpio.015.in_not 33 bit OUT TRUE hm2_7i96s.0.gpio.016.in 33 bit OUT FALSE hm2_7i96s.0.gpio.016.in_not 33 bit OUT FALSE hm2_7i96s.0.gpio.017.in 33 bit OUT TRUE hm2_7i96s.0.gpio.017.in_not 33 bit OUT FALSE hm2_7i96s.0.gpio.018.in 33 bit OUT TRUE hm2_7i96s.0.gpio.018.in_not 33 bit OUT FALSE hm2_7i96s.0.gpio.019.in 33 bit OUT TRUE hm2_7i96s.0.gpio.019.in_not 33 bit OUT FALSE hm2_7i96s.0.gpio.020.in 33 bit OUT TRUE hm2_7i96s.0.gpio.020.in_not 33 bit OUT FALSE hm2_7i96s.0.gpio.021.in 33 bit OUT TRUE hm2_7i96s.0.gpio.021.in_not 33 bit OUT FALSE hm2_7i96s.0.gpio.022.in 33 bit OUT TRUE hm2_7i96s.0.gpio.022.in_not 33 bit OUT FALSE hm2_7i96s.0.gpio.023.in 33 bit OUT TRUE hm2_7i96s.0.gpio.023.in_not 33 bit OUT FALSE hm2_7i96s.0.gpio.024.in 33 bit OUT TRUE hm2_7i96s.0.gpio.024.in_not 33 bit OUT FALSE hm2_7i96s.0.gpio.025.in 33 bit OUT TRUE hm2_7i96s.0.gpio.025.in_not 33 bit OUT FALSE hm2_7i96s.0.gpio.026.in 33 bit OUT TRUE hm2_7i96s.0.gpio.026.in_not 33 bit OUT TRUE hm2_7i96s.0.gpio.027.in 33 bit OUT FALSE hm2_7i96s.0.gpio.027.in_not 33 bit OUT TRUE hm2_7i96s.0.gpio.028.in 33 bit OUT FALSE hm2_7i96s.0.gpio.028.in_not 33 bit OUT FALSE hm2_7i96s.0.gpio.029.in 33 bit OUT TRUE hm2_7i96s.0.gpio.029.in_not 33 bit OUT TRUE hm2_7i96s.0.gpio.030.in 33 bit OUT FALSE hm2_7i96s.0.gpio.030.in_not 33 bit OUT TRUE hm2_7i96s.0.gpio.031.in 33 bit OUT FALSE hm2_7i96s.0.gpio.031.in_not 33 bit OUT FALSE hm2_7i96s.0.gpio.032.in 33 bit OUT TRUE hm2_7i96s.0.gpio.032.in_not 33 bit OUT TRUE hm2_7i96s.0.gpio.033.in 33 bit OUT FALSE hm2_7i96s.0.gpio.033.in_not 33 bit OUT TRUE hm2_7i96s.0.gpio.034.in 33 bit OUT FALSE hm2_7i96s.0.gpio.034.in_not 33 bit IN FALSE hm2_7i96s.0.gpio.034.out 33 bit OUT TRUE hm2_7i96s.0.gpio.035.in 33 bit OUT FALSE hm2_7i96s.0.gpio.035.in_not 33 bit IN FALSE hm2_7i96s.0.gpio.035.out 33 bit OUT TRUE hm2_7i96s.0.gpio.036.in 33 bit OUT FALSE hm2_7i96s.0.gpio.036.in_not 33 bit IN FALSE hm2_7i96s.0.gpio.036.out 33 bit OUT TRUE hm2_7i96s.0.gpio.037.in 33 bit OUT FALSE hm2_7i96s.0.gpio.037.in_not 33 bit IN FALSE hm2_7i96s.0.gpio.037.out 33 bit OUT TRUE hm2_7i96s.0.gpio.038.in 33 bit OUT FALSE hm2_7i96s.0.gpio.038.in_not 33 bit IN FALSE hm2_7i96s.0.gpio.038.out 33 bit OUT TRUE hm2_7i96s.0.gpio.039.in 33 bit OUT FALSE hm2_7i96s.0.gpio.039.in_not 33 bit IN FALSE hm2_7i96s.0.gpio.039.out 33 bit OUT TRUE hm2_7i96s.0.gpio.040.in 33 bit OUT FALSE hm2_7i96s.0.gpio.040.in_not 33 bit IN FALSE hm2_7i96s.0.gpio.040.out 33 bit OUT TRUE hm2_7i96s.0.gpio.041.in 33 bit OUT FALSE hm2_7i96s.0.gpio.041.in_not 33 bit IN FALSE hm2_7i96s.0.gpio.041.out 33 bit OUT TRUE hm2_7i96s.0.gpio.042.in 33 bit OUT FALSE hm2_7i96s.0.gpio.042.in_not 33 bit IN FALSE hm2_7i96s.0.gpio.042.out 33 bit OUT TRUE hm2_7i96s.0.gpio.043.in 33 bit OUT FALSE hm2_7i96s.0.gpio.043.in_not 33 bit IN FALSE hm2_7i96s.0.gpio.043.out 33 bit OUT TRUE hm2_7i96s.0.gpio.044.in 33 bit OUT FALSE hm2_7i96s.0.gpio.044.in_not 33 bit OUT TRUE hm2_7i96s.0.gpio.045.in 33 bit OUT FALSE hm2_7i96s.0.gpio.045.in_not 33 bit OUT TRUE hm2_7i96s.0.gpio.046.in 33 bit OUT FALSE hm2_7i96s.0.gpio.046.in_not 33 bit IN FALSE hm2_7i96s.0.gpio.046.out 33 bit OUT TRUE hm2_7i96s.0.gpio.047.in 33 bit OUT FALSE hm2_7i96s.0.gpio.047.in_not 33 bit IN FALSE hm2_7i96s.0.gpio.047.out 33 bit OUT TRUE hm2_7i96s.0.gpio.048.in 33 bit OUT FALSE hm2_7i96s.0.gpio.048.in_not 33 bit OUT TRUE hm2_7i96s.0.gpio.049.in 33 bit OUT FALSE hm2_7i96s.0.gpio.049.in_not 33 bit OUT TRUE hm2_7i96s.0.gpio.050.in 33 bit OUT FALSE hm2_7i96s.0.gpio.050.in_not 33 s32 OUT 0 hm2_7i96s.0.inm.00.enc0-count 33 bit IN FALSE hm2_7i96s.0.inm.00.enc0-reset 33 s32 OUT 0 hm2_7i96s.0.inm.00.enc1-count 33 bit IN FALSE hm2_7i96s.0.inm.00.enc1-reset 33 s32 OUT 0 hm2_7i96s.0.inm.00.enc2-count 33 bit IN FALSE hm2_7i96s.0.inm.00.enc2-reset 33 s32 OUT 0 hm2_7i96s.0.inm.00.enc3-count 33 bit IN FALSE hm2_7i96s.0.inm.00.enc3-reset 33 bit OUT FALSE hm2_7i96s.0.inm.00.input-00 33 bit OUT TRUE hm2_7i96s.0.inm.00.input-00-not 33 bit IN FALSE hm2_7i96s.0.inm.00.input-00-slow 33 bit OUT FALSE hm2_7i96s.0.inm.00.input-01 33 bit OUT TRUE hm2_7i96s.0.inm.00.input-01-not 33 bit IN FALSE hm2_7i96s.0.inm.00.input-01-slow 33 bit OUT FALSE hm2_7i96s.0.inm.00.input-02 33 bit OUT TRUE hm2_7i96s.0.inm.00.input-02-not 33 bit IN FALSE hm2_7i96s.0.inm.00.input-02-slow 33 bit OUT FALSE hm2_7i96s.0.inm.00.input-03 33 bit OUT TRUE hm2_7i96s.0.inm.00.input-03-not 33 bit IN FALSE hm2_7i96s.0.inm.00.input-03-slow 33 bit OUT FALSE hm2_7i96s.0.inm.00.input-04 33 bit OUT TRUE hm2_7i96s.0.inm.00.input-04-not 33 bit IN FALSE hm2_7i96s.0.inm.00.input-04-slow 33 bit OUT FALSE hm2_7i96s.0.inm.00.input-05 33 bit OUT TRUE hm2_7i96s.0.inm.00.input-05-not 33 bit IN FALSE hm2_7i96s.0.inm.00.input-05-slow 33 bit OUT FALSE hm2_7i96s.0.inm.00.input-06 33 bit OUT TRUE hm2_7i96s.0.inm.00.input-06-not 33 bit IN FALSE hm2_7i96s.0.inm.00.input-06-slow 33 bit OUT FALSE hm2_7i96s.0.inm.00.input-07 33 bit OUT TRUE hm2_7i96s.0.inm.00.input-07-not 33 bit IN FALSE hm2_7i96s.0.inm.00.input-07-slow 33 bit OUT FALSE hm2_7i96s.0.inm.00.input-08 33 bit OUT TRUE hm2_7i96s.0.inm.00.input-08-not 33 bit IN FALSE hm2_7i96s.0.inm.00.input-08-slow 33 bit OUT FALSE hm2_7i96s.0.inm.00.input-09 33 bit OUT TRUE hm2_7i96s.0.inm.00.input-09-not 33 bit IN FALSE hm2_7i96s.0.inm.00.input-09-slow 33 bit OUT FALSE hm2_7i96s.0.inm.00.input-10 33 bit OUT TRUE hm2_7i96s.0.inm.00.input-10-not 33 bit IN FALSE hm2_7i96s.0.inm.00.input-10-slow 33 bit OUT FALSE hm2_7i96s.0.inm.00.raw-input-00 33 bit OUT TRUE hm2_7i96s.0.inm.00.raw-input-00-not 33 bit OUT FALSE hm2_7i96s.0.inm.00.raw-input-01 33 bit OUT TRUE hm2_7i96s.0.inm.00.raw-input-01-not 33 bit OUT FALSE hm2_7i96s.0.inm.00.raw-input-02 33 bit OUT TRUE hm2_7i96s.0.inm.00.raw-input-02-not 33 bit OUT FALSE hm2_7i96s.0.inm.00.raw-input-03 33 bit OUT TRUE hm2_7i96s.0.inm.00.raw-input-03-not 33 bit OUT FALSE hm2_7i96s.0.inm.00.raw-input-04 33 bit OUT TRUE hm2_7i96s.0.inm.00.raw-input-04-not 33 bit OUT FALSE hm2_7i96s.0.inm.00.raw-input-05 33 bit OUT TRUE hm2_7i96s.0.inm.00.raw-input-05-not 33 bit OUT FALSE hm2_7i96s.0.inm.00.raw-input-06 33 bit OUT TRUE hm2_7i96s.0.inm.00.raw-input-06-not 33 bit OUT FALSE hm2_7i96s.0.inm.00.raw-input-07 33 bit OUT TRUE hm2_7i96s.0.inm.00.raw-input-07-not 33 bit OUT FALSE hm2_7i96s.0.inm.00.raw-input-08 33 bit OUT TRUE hm2_7i96s.0.inm.00.raw-input-08-not 33 bit OUT FALSE hm2_7i96s.0.inm.00.raw-input-09 33 bit OUT TRUE hm2_7i96s.0.inm.00.raw-input-09-not 33 bit OUT FALSE hm2_7i96s.0.inm.00.raw-input-10 33 bit OUT TRUE hm2_7i96s.0.inm.00.raw-input-10-not 33 bit IN FALSE hm2_7i96s.0.led.CR01 33 bit IN FALSE hm2_7i96s.0.led.CR02 33 bit IN FALSE hm2_7i96s.0.led.CR03 33 bit IN FALSE hm2_7i96s.0.led.CR04 33 bit IN FALSE hm2_7i96s.0.outm.00.invert-04 33 bit IN FALSE hm2_7i96s.0.outm.00.invert-05 33 bit IN FALSE hm2_7i96s.0.outm.00.out-04 33 bit IN FALSE hm2_7i96s.0.outm.00.out-05 33 bit OUT FALSE hm2_7i96s.0.packet-error 33 bit OUT FALSE hm2_7i96s.0.packet-error-exceeded 33 s32 OUT 0 hm2_7i96s.0.packet-error-level 33 u32 I/O 0x00000000 hm2_7i96s.0.packet-error-total 33 bit IN FALSE hm2_7i96s.0.pwmgen.00.enable 33 float IN 0 hm2_7i96s.0.pwmgen.00.value 33 s32 OUT 0 hm2_7i96s.0.read-request.time 33 s32 OUT 422504 hm2_7i96s.0.read.time 33 u32 OUT 0x00000000 hm2_7i96s.0.sserial.port-0.fault-count 33 u32 OUT 0x00000003 hm2_7i96s.0.sserial.port-0.port_state 33 u32 OUT 0x00000000 hm2_7i96s.0.sserial.port-0.port_state2 33 u32 OUT 0x00000000 hm2_7i96s.0.sserial.port-0.port_state3 33 bit IN TRUE hm2_7i96s.0.sserial.port-0.run 33 bit IN FALSE hm2_7i96s.0.ssr.00.invert-00 33 bit IN FALSE hm2_7i96s.0.ssr.00.invert-01 33 bit IN FALSE hm2_7i96s.0.ssr.00.invert-02 33 bit IN FALSE hm2_7i96s.0.ssr.00.invert-03 33 bit IN FALSE hm2_7i96s.0.ssr.00.out-00 33 bit IN FALSE hm2_7i96s.0.ssr.00.out-01 33 bit IN FALSE hm2_7i96s.0.ssr.00.out-02 33 bit IN FALSE hm2_7i96s.0.ssr.00.out-03 33 u32 IN 0x000F4240 hm2_7i96s.0.ssr.00.rate 33 bit IN TRUE hm2_7i96s.0.stepgen.00.control-type 33 s32 OUT 0 hm2_7i96s.0.stepgen.00.counts 33 float OUT 0 hm2_7i96s.0.stepgen.00.dbg_err_at_match 33 float OUT 0 hm2_7i96s.0.stepgen.00.dbg_ff_vel 33 float OUT 0 hm2_7i96s.0.stepgen.00.dbg_pos_minus_prev_cmd 33 float OUT 0 hm2_7i96s.0.stepgen.00.dbg_s_to_match 33 s32 OUT 0 hm2_7i96s.0.stepgen.00.dbg_step_rate 33 float OUT 0 hm2_7i96s.0.stepgen.00.dbg_vel_error 33 bit IN FALSE hm2_7i96s.0.stepgen.00.enable <== emcmot.00.enable 33 float IN 0 hm2_7i96s.0.stepgen.00.position-cmd 33 float OUT 0 hm2_7i96s.0.stepgen.00.position-fb ==> motor.00.pos-fb 33 bit IN FALSE hm2_7i96s.0.stepgen.00.position-reset 33 float IN 0 hm2_7i96s.0.stepgen.00.velocity-cmd <== motor.00.command 33 float OUT 0 hm2_7i96s.0.stepgen.00.velocity-fb 33 bit IN TRUE hm2_7i96s.0.stepgen.01.control-type 33 s32 OUT 0 hm2_7i96s.0.stepgen.01.counts 33 float OUT 0 hm2_7i96s.0.stepgen.01.dbg_err_at_match 33 float OUT 0 hm2_7i96s.0.stepgen.01.dbg_ff_vel 33 float OUT 0 hm2_7i96s.0.stepgen.01.dbg_pos_minus_prev_cmd 33 float OUT 0 hm2_7i96s.0.stepgen.01.dbg_s_to_match 33 s32 OUT 0 hm2_7i96s.0.stepgen.01.dbg_step_rate 33 float OUT 0 hm2_7i96s.0.stepgen.01.dbg_vel_error 33 bit IN FALSE hm2_7i96s.0.stepgen.01.enable <== emcmot.01.enable 33 float IN 0 hm2_7i96s.0.stepgen.01.position-cmd 33 float OUT 0 hm2_7i96s.0.stepgen.01.position-fb ==> motor.01.pos-fb 33 bit IN FALSE hm2_7i96s.0.stepgen.01.position-reset 33 float IN 0 hm2_7i96s.0.stepgen.01.velocity-cmd <== motor.01.command 33 float OUT 0 hm2_7i96s.0.stepgen.01.velocity-fb 33 bit IN TRUE hm2_7i96s.0.stepgen.02.control-type 33 s32 OUT 0 hm2_7i96s.0.stepgen.02.counts 33 float OUT 0 hm2_7i96s.0.stepgen.02.dbg_err_at_match 33 float OUT 0 hm2_7i96s.0.stepgen.02.dbg_ff_vel 33 float OUT 0 hm2_7i96s.0.stepgen.02.dbg_pos_minus_prev_cmd 33 float OUT 0 hm2_7i96s.0.stepgen.02.dbg_s_to_match 33 s32 OUT 0 hm2_7i96s.0.stepgen.02.dbg_step_rate 33 float OUT 0 hm2_7i96s.0.stepgen.02.dbg_vel_error 33 bit IN FALSE hm2_7i96s.0.stepgen.02.enable <== emcmot.02.enable 33 float IN 0 hm2_7i96s.0.stepgen.02.position-cmd 33 float OUT 0 hm2_7i96s.0.stepgen.02.position-fb ==> motor.02.pos-fb 33 bit IN FALSE hm2_7i96s.0.stepgen.02.position-reset 33 float IN 0 hm2_7i96s.0.stepgen.02.velocity-cmd <== motor.02.command 33 float OUT 0 hm2_7i96s.0.stepgen.02.velocity-fb 33 bit IN FALSE hm2_7i96s.0.stepgen.03.control-type 33 s32 OUT 0 hm2_7i96s.0.stepgen.03.counts 33 float OUT 0 hm2_7i96s.0.stepgen.03.dbg_err_at_match 33 float OUT 0 hm2_7i96s.0.stepgen.03.dbg_ff_vel 33 float OUT 0 hm2_7i96s.0.stepgen.03.dbg_pos_minus_prev_cmd 33 float OUT 0 hm2_7i96s.0.stepgen.03.dbg_s_to_match 33 s32 OUT 0 hm2_7i96s.0.stepgen.03.dbg_step_rate 33 float OUT 0 hm2_7i96s.0.stepgen.03.dbg_vel_error 33 bit IN FALSE hm2_7i96s.0.stepgen.03.enable 33 float IN 0 hm2_7i96s.0.stepgen.03.position-cmd 33 float OUT 0 hm2_7i96s.0.stepgen.03.position-fb 33 bit IN FALSE hm2_7i96s.0.stepgen.03.position-reset 33 float IN 0 hm2_7i96s.0.stepgen.03.velocity-cmd 33 float OUT 0 hm2_7i96s.0.stepgen.03.velocity-fb 33 bit IN FALSE hm2_7i96s.0.stepgen.04.control-type 33 s32 OUT 0 hm2_7i96s.0.stepgen.04.counts 33 float OUT 0 hm2_7i96s.0.stepgen.04.dbg_err_at_match 33 float OUT 0 hm2_7i96s.0.stepgen.04.dbg_ff_vel 33 float OUT 0 hm2_7i96s.0.stepgen.04.dbg_pos_minus_prev_cmd 33 float OUT 0 hm2_7i96s.0.stepgen.04.dbg_s_to_match 33 s32 OUT 0 hm2_7i96s.0.stepgen.04.dbg_step_rate 33 float OUT 0 hm2_7i96s.0.stepgen.04.dbg_vel_error 33 bit IN FALSE hm2_7i96s.0.stepgen.04.enable 33 float IN 0 hm2_7i96s.0.stepgen.04.position-cmd 33 float OUT 0 hm2_7i96s.0.stepgen.04.position-fb 33 bit IN FALSE hm2_7i96s.0.stepgen.04.position-reset 33 float IN 0 hm2_7i96s.0.stepgen.04.velocity-cmd 33 float OUT 0 hm2_7i96s.0.stepgen.04.velocity-fb 33 s32 IN 1 hm2_7i96s.0.stepgen.timer-number 33 bit I/O FALSE hm2_7i96s.0.watchdog.has_bit 33 s32 OUT 29684 hm2_7i96s.0.write.time Pin Aliases: Alias Original Name Signals: Type Value Name (linked to) Parameters: Owner Type Dir Value Name 33 u32 RO 0x00000002 hm2_7i96s.0.7i73.0.0.analogin0 33 u32 RO 0x00000003 hm2_7i96s.0.7i73.0.0.analogin1 33 u32 RO 0x00000000 hm2_7i96s.0.7i73.0.0.analogin2 33 u32 RO 0x00000002 hm2_7i96s.0.7i73.0.0.analogin3 33 u32 RW 0x00002710 hm2_7i96s.0.7i73.0.0.contrast 33 u32 RW 0x00000100 hm2_7i96s.0.7i73.0.0.enc0.counts-per-rev 33 float RW 1 hm2_7i96s.0.7i73.0.0.enc0.scale 33 u32 RW 0x00000100 hm2_7i96s.0.7i73.0.0.enc1.counts-per-rev 33 float RW 1 hm2_7i96s.0.7i73.0.0.enc1.scale 33 u32 RW 0x00000100 hm2_7i96s.0.7i73.0.0.enc2.counts-per-rev 33 float RW 1 hm2_7i96s.0.7i73.0.0.enc2.scale 33 u32 RW 0x00000100 hm2_7i96s.0.7i73.0.0.enc3.counts-per-rev 33 float RW 1 hm2_7i96s.0.7i73.0.0.enc3.scale 33 u32 RW 0x00000000 hm2_7i96s.0.7i73.0.0.encmode0 33 u32 RW 0x00000000 hm2_7i96s.0.7i73.0.0.encmode1 33 u32 RW 0x00000000 hm2_7i96s.0.7i73.0.0.encmode2 33 u32 RW 0x00000000 hm2_7i96s.0.7i73.0.0.encmode3 33 u32 RW 0x00000001 hm2_7i96s.0.7i73.0.0.hwrevision 33 u32 RW 0x00000001 hm2_7i96s.0.7i73.0.0.keymode 33 u32 RW 0x00008000 hm2_7i96s.0.7i73.0.0.nvanalogfilter 33 u32 RW 0x00002710 hm2_7i96s.0.7i73.0.0.nvcontrast 33 u32 RW 0x00000414 hm2_7i96s.0.7i73.0.0.nvdispmode 33 u32 RW 0x00000000 hm2_7i96s.0.7i73.0.0.nvencmode0 33 u32 RW 0x00000000 hm2_7i96s.0.7i73.0.0.nvencmode1 33 u32 RW 0x00000000 hm2_7i96s.0.7i73.0.0.nvencmode2 33 u32 RW 0x00000000 hm2_7i96s.0.7i73.0.0.nvencmode3 33 u32 RW 0x0000001E hm2_7i96s.0.7i73.0.0.nvkeytimer 33 u32 RO 0x12345678 hm2_7i96s.0.7i73.0.0.nvunitnumber 33 u32 RO 0x00000032 hm2_7i96s.0.7i73.0.0.nvwatchdogtimeout 33 bit RW FALSE hm2_7i96s.0.7i73.0.0.output-00-invert 33 bit RW FALSE hm2_7i96s.0.7i73.0.0.output-01-invert 33 bit RW FALSE hm2_7i96s.0.7i73.0.0.output-02-invert 33 bit RW FALSE hm2_7i96s.0.7i73.0.0.output-03-invert 33 bit RW FALSE hm2_7i96s.0.7i73.0.0.output-04-invert 33 bit RW FALSE hm2_7i96s.0.7i73.0.0.output-05-invert 33 bit RW FALSE hm2_7i96s.0.7i73.0.0.output-06-invert 33 bit RW FALSE hm2_7i96s.0.7i73.0.0.output-07-invert 33 bit RW FALSE hm2_7i96s.0.7i73.0.0.output-08-invert 33 bit RW FALSE hm2_7i96s.0.7i73.0.0.output-09-invert 33 u32 RW 0x00000010 hm2_7i96s.0.7i73.0.0.swrevision 33 u32 RO 0x00000000 hm2_7i96s.0.7i76.0.1.analogin0 33 u32 RO 0x00000000 hm2_7i96s.0.7i76.0.1.analogin1 33 u32 RO 0x00000000 hm2_7i96s.0.7i76.0.1.analogin2 33 u32 RO 0x00000000 hm2_7i96s.0.7i76.0.1.analogin3 33 u32 RW 0x00000000 hm2_7i96s.0.7i76.0.1.encmode0 33 u32 RW 0x00000000 hm2_7i96s.0.7i76.0.1.encmode1 33 u32 RO 0x000051C0 hm2_7i96s.0.7i76.0.1.fieldvoltage 33 u32 RW 0x00000001 hm2_7i96s.0.7i76.0.1.hwrevision 33 u32 RW 0x00000009 hm2_7i96s.0.7i76.0.1.nvbaudrate 33 u32 RW 0x00000000 hm2_7i96s.0.7i76.0.1.nvencmode0 33 u32 RW 0x00000000 hm2_7i96s.0.7i76.0.1.nvencmode1 33 u32 RW 0x10000B8A hm2_7i96s.0.7i76.0.1.nvunitnumber 33 u32 RW 0x00000032 hm2_7i96s.0.7i76.0.1.nvwatchdogtimeout 33 bit RW FALSE hm2_7i96s.0.7i76.0.1.output-00-invert 33 bit RW FALSE hm2_7i96s.0.7i76.0.1.output-01-invert 33 bit RW FALSE hm2_7i96s.0.7i76.0.1.output-02-invert 33 bit RW FALSE hm2_7i96s.0.7i76.0.1.output-03-invert 33 bit RW FALSE hm2_7i96s.0.7i76.0.1.output-04-invert 33 bit RW FALSE hm2_7i96s.0.7i76.0.1.output-05-invert 33 bit RW FALSE hm2_7i96s.0.7i76.0.1.output-06-invert 33 bit RW FALSE hm2_7i96s.0.7i76.0.1.output-07-invert 33 bit RW FALSE hm2_7i96s.0.7i76.0.1.output-08-invert 33 bit RW FALSE hm2_7i96s.0.7i76.0.1.output-09-invert 33 bit RW FALSE hm2_7i96s.0.7i76.0.1.output-10-invert 33 bit RW FALSE hm2_7i96s.0.7i76.0.1.output-11-invert 33 bit RW FALSE hm2_7i96s.0.7i76.0.1.output-12-invert 33 bit RW FALSE hm2_7i96s.0.7i76.0.1.output-13-invert 33 bit RW FALSE hm2_7i96s.0.7i76.0.1.output-14-invert 33 bit RW FALSE hm2_7i96s.0.7i76.0.1.output-15-invert 33 bit RW FALSE hm2_7i96s.0.7i76.0.1.spindir-invert 33 bit RW FALSE hm2_7i96s.0.7i76.0.1.spinena-invert 33 float RW 100 hm2_7i96s.0.7i76.0.1.spinout-maxlim 33 float RW 0 hm2_7i96s.0.7i76.0.1.spinout-minlim 33 float RW 100 hm2_7i96s.0.7i76.0.1.spinout-scalemax 33 u32 RW 0x0000000F hm2_7i96s.0.7i76.0.1.swrevision 33 bit RW FALSE hm2_7i96s.0.encoder.00.counter-mode 33 bit RW TRUE hm2_7i96s.0.encoder.00.filter 33 bit RW FALSE hm2_7i96s.0.encoder.00.index-invert 33 bit RW FALSE hm2_7i96s.0.encoder.00.index-mask 33 bit RW FALSE hm2_7i96s.0.encoder.00.index-mask-invert 33 float RW 1 hm2_7i96s.0.encoder.00.scale 33 float RW 0.5 hm2_7i96s.0.encoder.00.vel-timeout 33 bit RW FALSE hm2_7i96s.0.encoder.01.counter-mode 33 bit RW TRUE hm2_7i96s.0.encoder.01.filter 33 bit RW FALSE hm2_7i96s.0.encoder.01.index-invert 33 bit RW FALSE hm2_7i96s.0.encoder.01.index-mask 33 bit RW FALSE hm2_7i96s.0.encoder.01.index-mask-invert 33 float RW 1 hm2_7i96s.0.encoder.01.scale 33 float RW 0.5 hm2_7i96s.0.encoder.01.vel-timeout 33 bit RW FALSE hm2_7i96s.0.gpio.011.invert_output 33 bit RW FALSE hm2_7i96s.0.gpio.011.is_opendrain 33 bit RW FALSE hm2_7i96s.0.gpio.012.invert_output 33 bit RW FALSE hm2_7i96s.0.gpio.012.is_opendrain 33 bit RW FALSE hm2_7i96s.0.gpio.013.invert_output 33 bit RW FALSE hm2_7i96s.0.gpio.013.is_opendrain 33 bit RW FALSE hm2_7i96s.0.gpio.014.invert_output 33 bit RW FALSE hm2_7i96s.0.gpio.014.is_opendrain 33 bit RW FALSE hm2_7i96s.0.gpio.015.invert_output 33 bit RW FALSE hm2_7i96s.0.gpio.015.is_opendrain 33 bit RW FALSE hm2_7i96s.0.gpio.016.invert_output 33 bit RW FALSE hm2_7i96s.0.gpio.016.is_opendrain 33 bit RW FALSE hm2_7i96s.0.gpio.033.invert_output 33 bit RW FALSE hm2_7i96s.0.gpio.033.is_opendrain 33 bit RW FALSE hm2_7i96s.0.gpio.034.invert_output 33 bit RW FALSE hm2_7i96s.0.gpio.034.is_opendrain 33 bit RW FALSE hm2_7i96s.0.gpio.034.is_output 33 bit RW FALSE hm2_7i96s.0.gpio.035.invert_output 33 bit RW FALSE hm2_7i96s.0.gpio.035.is_opendrain 33 bit RW FALSE hm2_7i96s.0.gpio.035.is_output 33 bit RW FALSE hm2_7i96s.0.gpio.036.invert_output 33 bit RW FALSE hm2_7i96s.0.gpio.036.is_opendrain 33 bit RW FALSE hm2_7i96s.0.gpio.036.is_output 33 bit RW FALSE hm2_7i96s.0.gpio.037.invert_output 33 bit RW FALSE hm2_7i96s.0.gpio.037.is_opendrain 33 bit RW FALSE hm2_7i96s.0.gpio.037.is_output 33 bit RW FALSE hm2_7i96s.0.gpio.038.invert_output 33 bit RW FALSE hm2_7i96s.0.gpio.038.is_opendrain 33 bit RW FALSE hm2_7i96s.0.gpio.038.is_output 33 bit RW FALSE hm2_7i96s.0.gpio.039.invert_output 33 bit RW FALSE hm2_7i96s.0.gpio.039.is_opendrain 33 bit RW FALSE hm2_7i96s.0.gpio.039.is_output 33 bit RW FALSE hm2_7i96s.0.gpio.040.invert_output 33 bit RW FALSE hm2_7i96s.0.gpio.040.is_opendrain 33 bit RW FALSE hm2_7i96s.0.gpio.040.is_output 33 bit RW FALSE hm2_7i96s.0.gpio.041.invert_output 33 bit RW FALSE hm2_7i96s.0.gpio.041.is_opendrain 33 bit RW FALSE hm2_7i96s.0.gpio.041.is_output 33 bit RW FALSE hm2_7i96s.0.gpio.042.invert_output 33 bit RW FALSE hm2_7i96s.0.gpio.042.is_opendrain 33 bit RW FALSE hm2_7i96s.0.gpio.042.is_output 33 bit RW FALSE hm2_7i96s.0.gpio.043.invert_output 33 bit RW FALSE hm2_7i96s.0.gpio.043.is_opendrain 33 bit RW FALSE hm2_7i96s.0.gpio.043.is_output 33 bit RW FALSE hm2_7i96s.0.gpio.046.invert_output 33 bit RW FALSE hm2_7i96s.0.gpio.046.is_opendrain 33 bit RW FALSE hm2_7i96s.0.gpio.046.is_output 33 bit RW FALSE hm2_7i96s.0.gpio.047.invert_output 33 bit RW FALSE hm2_7i96s.0.gpio.047.is_opendrain 33 bit RW FALSE hm2_7i96s.0.gpio.047.is_output 33 bit RW FALSE hm2_7i96s.0.inm.00.enc0_4xmode 33 bit RW FALSE hm2_7i96s.0.inm.00.enc1_4xmode 33 bit RW FALSE hm2_7i96s.0.inm.00.enc2_4xmode 33 bit RW FALSE hm2_7i96s.0.inm.00.enc3_4xmode 33 u32 RW 0x00000005 hm2_7i96s.0.inm.00.fast_scans 33 u32 RW 0x00004E20 hm2_7i96s.0.inm.00.scan_rate 33 u32 RO 0x0000000B hm2_7i96s.0.inm.00.scan_width 33 u32 RW 0x000001F4 hm2_7i96s.0.inm.00.slow_scans 33 bit RW FALSE hm2_7i96s.0.io_error 33 s32 RO 1 hm2_7i96s.0.packet-error-decrement 33 s32 RW 2 hm2_7i96s.0.packet-error-increment 33 s32 RW 10 hm2_7i96s.0.packet-error-limit 33 s32 RW 70 hm2_7i96s.0.packet-read-timeout 33 bit RW FALSE hm2_7i96s.0.pwmgen.00.offset-mode 33 s32 RW 1 hm2_7i96s.0.pwmgen.00.output-type 33 float RW 1 hm2_7i96s.0.pwmgen.00.scale 33 u32 RW 0x00004E20 hm2_7i96s.0.pwmgen.pdm_frequency 33 u32 RW 0x00004E20 hm2_7i96s.0.pwmgen.pwm_frequency 33 s32 RW 0 hm2_7i96s.0.read-request.tmax 33 bit RO FALSE hm2_7i96s.0.read-request.tmax-increased 33 s32 RW 518216 hm2_7i96s.0.read.tmax 33 bit RO FALSE hm2_7i96s.0.read.tmax-increased 33 bit RW FALSE hm2_7i96s.0.sserial.00.tx0.invert_output 33 bit RW FALSE hm2_7i96s.0.sserial.00.tx0.is_opendrain 33 bit RW FALSE hm2_7i96s.0.sserial.00.tx1.invert_output 33 bit RW FALSE hm2_7i96s.0.sserial.00.tx1.is_opendrain 33 bit RW FALSE hm2_7i96s.0.sserial.00.txen0.invert_output 33 bit RW FALSE hm2_7i96s.0.sserial.00.txen0.is_opendrain 33 u32 RW 0x00000001 hm2_7i96s.0.sserial.port-0.fault-dec 33 u32 RW 0x0000000A hm2_7i96s.0.sserial.port-0.fault-inc 33 u32 RW 0x000000C8 hm2_7i96s.0.sserial.port-0.fault-lim 33 bit RW FALSE hm2_7i96s.0.stepgen.00.direction.invert_output 33 bit RW FALSE hm2_7i96s.0.stepgen.00.direction.is_opendrain 33 u32 RW 0x000007D0 hm2_7i96s.0.stepgen.00.dirhold 33 u32 RW 0x000007D0 hm2_7i96s.0.stepgen.00.dirsetup 33 float RW 2400 hm2_7i96s.0.stepgen.00.maxaccel 33 float RW 240 hm2_7i96s.0.stepgen.00.maxvel 33 float RW 10000 hm2_7i96s.0.stepgen.00.position-scale 33 bit RW FALSE hm2_7i96s.0.stepgen.00.step.invert_output 33 bit RW FALSE hm2_7i96s.0.stepgen.00.step.is_opendrain 33 u32 RW 0x00000000 hm2_7i96s.0.stepgen.00.step_type 33 u32 RW 0x00000064 hm2_7i96s.0.stepgen.00.steplen 33 u32 RW 0x00000064 hm2_7i96s.0.stepgen.00.stepspace 33 u32 RW 0x00000000 hm2_7i96s.0.stepgen.00.table-data-0 33 u32 RW 0x00000000 hm2_7i96s.0.stepgen.00.table-data-1 33 u32 RW 0x00000000 hm2_7i96s.0.stepgen.00.table-data-2 33 u32 RW 0x00000000 hm2_7i96s.0.stepgen.00.table-data-3 33 bit RW FALSE hm2_7i96s.0.stepgen.01.direction.invert_output 33 bit RW FALSE hm2_7i96s.0.stepgen.01.direction.is_opendrain 33 u32 RW 0x000007D0 hm2_7i96s.0.stepgen.01.dirhold 33 u32 RW 0x000007D0 hm2_7i96s.0.stepgen.01.dirsetup 33 float RW 2400 hm2_7i96s.0.stepgen.01.maxaccel 33 float RW 240 hm2_7i96s.0.stepgen.01.maxvel 33 float RW 10000 hm2_7i96s.0.stepgen.01.position-scale 33 bit RW FALSE hm2_7i96s.0.stepgen.01.step.invert_output 33 bit RW FALSE hm2_7i96s.0.stepgen.01.step.is_opendrain 33 u32 RW 0x00000000 hm2_7i96s.0.stepgen.01.step_type 33 u32 RW 0x00000064 hm2_7i96s.0.stepgen.01.steplen 33 u32 RW 0x00000064 hm2_7i96s.0.stepgen.01.stepspace 33 u32 RW 0x00000000 hm2_7i96s.0.stepgen.01.table-data-0 33 u32 RW 0x00000000 hm2_7i96s.0.stepgen.01.table-data-1 33 u32 RW 0x00000000 hm2_7i96s.0.stepgen.01.table-data-2 33 u32 RW 0x00000000 hm2_7i96s.0.stepgen.01.table-data-3 33 bit RW FALSE hm2_7i96s.0.stepgen.02.direction.invert_output 33 bit RW FALSE hm2_7i96s.0.stepgen.02.direction.is_opendrain 33 u32 RW 0x000007D0 hm2_7i96s.0.stepgen.02.dirhold 33 u32 RW 0x000007D0 hm2_7i96s.0.stepgen.02.dirsetup 33 float RW 2400 hm2_7i96s.0.stepgen.02.maxaccel 33 float RW 240 hm2_7i96s.0.stepgen.02.maxvel 33 float RW 10000 hm2_7i96s.0.stepgen.02.position-scale 33 bit RW FALSE hm2_7i96s.0.stepgen.02.step.invert_output 33 bit RW FALSE hm2_7i96s.0.stepgen.02.step.is_opendrain 33 u32 RW 0x00000000 hm2_7i96s.0.stepgen.02.step_type 33 u32 RW 0x00000064 hm2_7i96s.0.stepgen.02.steplen 33 u32 RW 0x00000064 hm2_7i96s.0.stepgen.02.stepspace 33 u32 RW 0x00000000 hm2_7i96s.0.stepgen.02.table-data-0 33 u32 RW 0x00000000 hm2_7i96s.0.stepgen.02.table-data-1 33 u32 RW 0x00000000 hm2_7i96s.0.stepgen.02.table-data-2 33 u32 RW 0x00000000 hm2_7i96s.0.stepgen.02.table-data-3 33 bit RW FALSE hm2_7i96s.0.stepgen.03.direction.invert_output 33 bit RW FALSE hm2_7i96s.0.stepgen.03.direction.is_opendrain 33 u32 RW 0x00027FF6 hm2_7i96s.0.stepgen.03.dirhold 33 u32 RW 0x00027FF6 hm2_7i96s.0.stepgen.03.dirsetup 33 float RW 1 hm2_7i96s.0.stepgen.03.maxaccel 33 float RW 0 hm2_7i96s.0.stepgen.03.maxvel 33 float RW 1 hm2_7i96s.0.stepgen.03.position-scale 33 bit RW FALSE hm2_7i96s.0.stepgen.03.step.invert_output 33 bit RW FALSE hm2_7i96s.0.stepgen.03.step.is_opendrain 33 u32 RW 0x00000000 hm2_7i96s.0.stepgen.03.step_type 33 u32 RW 0x00027FF6 hm2_7i96s.0.stepgen.03.steplen 33 u32 RW 0x00027FF6 hm2_7i96s.0.stepgen.03.stepspace 33 u32 RW 0x00000000 hm2_7i96s.0.stepgen.03.table-data-0 33 u32 RW 0x00000000 hm2_7i96s.0.stepgen.03.table-data-1 33 u32 RW 0x00000000 hm2_7i96s.0.stepgen.03.table-data-2 33 u32 RW 0x00000000 hm2_7i96s.0.stepgen.03.table-data-3 33 bit RW FALSE hm2_7i96s.0.stepgen.04.direction.invert_output 33 bit RW FALSE hm2_7i96s.0.stepgen.04.direction.is_opendrain 33 u32 RW 0x00027FF6 hm2_7i96s.0.stepgen.04.dirhold 33 u32 RW 0x00027FF6 hm2_7i96s.0.stepgen.04.dirsetup 33 float RW 1 hm2_7i96s.0.stepgen.04.maxaccel 33 float RW 0 hm2_7i96s.0.stepgen.04.maxvel 33 float RW 1 hm2_7i96s.0.stepgen.04.position-scale 33 bit RW FALSE hm2_7i96s.0.stepgen.04.step.invert_output 33 bit RW FALSE hm2_7i96s.0.stepgen.04.step.is_opendrain 33 u32 RW 0x00000000 hm2_7i96s.0.stepgen.04.step_type 33 u32 RW 0x00027FF6 hm2_7i96s.0.stepgen.04.steplen 33 u32 RW 0x00027FF6 hm2_7i96s.0.stepgen.04.stepspace 33 u32 RW 0x00000000 hm2_7i96s.0.stepgen.04.table-data-0 33 u32 RW 0x00000000 hm2_7i96s.0.stepgen.04.table-data-1 33 u32 RW 0x00000000 hm2_7i96s.0.stepgen.04.table-data-2 33 u32 RW 0x00000000 hm2_7i96s.0.stepgen.04.table-data-3 33 u32 RW 0x017D7840 hm2_7i96s.0.watchdog.timeout_ns 33 s32 RW 59472 hm2_7i96s.0.write.tmax 33 bit RO FALSE hm2_7i96s.0.write.tmax-increased Parameter Aliases: Alias Original Name hm2_7i96s.0.sserial.00.tx0.invert_output hm2_7i96s.0.gpio.031.invert_output hm2_7i96s.0.sserial.00.tx0.is_opendrain hm2_7i96s.0.gpio.031.is_opendrain hm2_7i96s.0.sserial.00.tx1.invert_output hm2_7i96s.0.gpio.044.invert_output hm2_7i96s.0.sserial.00.tx1.is_opendrain hm2_7i96s.0.gpio.044.is_opendrain hm2_7i96s.0.sserial.00.txen0.invert_output hm2_7i96s.0.gpio.032.invert_output hm2_7i96s.0.sserial.00.txen0.is_opendrain hm2_7i96s.0.gpio.032.is_opendrain hm2_7i96s.0.stepgen.00.direction.invert_output hm2_7i96s.0.gpio.018.invert_output hm2_7i96s.0.stepgen.00.direction.is_opendrain hm2_7i96s.0.gpio.018.is_opendrain hm2_7i96s.0.stepgen.00.step.invert_output hm2_7i96s.0.gpio.017.invert_output hm2_7i96s.0.stepgen.00.step.is_opendrain hm2_7i96s.0.gpio.017.is_opendrain hm2_7i96s.0.stepgen.01.direction.invert_output hm2_7i96s.0.gpio.020.invert_output hm2_7i96s.0.stepgen.01.direction.is_opendrain hm2_7i96s.0.gpio.020.is_opendrain hm2_7i96s.0.stepgen.01.step.invert_output hm2_7i96s.0.gpio.019.invert_output hm2_7i96s.0.stepgen.01.step.is_opendrain hm2_7i96s.0.gpio.019.is_opendrain hm2_7i96s.0.stepgen.02.direction.invert_output hm2_7i96s.0.gpio.022.invert_output hm2_7i96s.0.stepgen.02.direction.is_opendrain hm2_7i96s.0.gpio.022.is_opendrain hm2_7i96s.0.stepgen.02.step.invert_output hm2_7i96s.0.gpio.021.invert_output hm2_7i96s.0.stepgen.02.step.is_opendrain hm2_7i96s.0.gpio.021.is_opendrain hm2_7i96s.0.stepgen.03.direction.invert_output hm2_7i96s.0.gpio.024.invert_output hm2_7i96s.0.stepgen.03.direction.is_opendrain hm2_7i96s.0.gpio.024.is_opendrain hm2_7i96s.0.stepgen.03.step.invert_output hm2_7i96s.0.gpio.023.invert_output hm2_7i96s.0.stepgen.03.step.is_opendrain hm2_7i96s.0.gpio.023.is_opendrain hm2_7i96s.0.stepgen.04.direction.invert_output hm2_7i96s.0.gpio.026.invert_output hm2_7i96s.0.stepgen.04.direction.is_opendrain hm2_7i96s.0.gpio.026.is_opendrain hm2_7i96s.0.stepgen.04.step.invert_output hm2_7i96s.0.gpio.025.invert_output hm2_7i96s.0.stepgen.04.step.is_opendrain hm2_7i96s.0.gpio.025.is_opendrain Exported Functions: Owner CodeAddr Arg FP Users Name 00033 7f2d27822c72 55b55f36a180 YES 1 hm2_7i96s.0.read 00033 7f2d27822bf7 55b55f36a180 YES 0 hm2_7i96s.0.read-request 00033 7f2d27822aa9 55b55f36a180 YES 1 hm2_7i96s.0.write Realtime Threads: Period FP Name ( Time, Max-Time )