7i43 + 7i76? And where is 7i76E up to?
13 Mar 2015 03:11 #56767
by pippin88
Replied by pippin88 on topic 7i43 + 7i76? And where is 7i76E up to?
PCW, that would be great.
I believe it's a 400k. The firmwares I tried were for the 400k and linuxcnc loaded fine without error. Is there any other way to tell? I couldn't see it on the card or chip.
Can the other 50pin port be assigned for GPIO?
Thanks
I believe it's a 400k. The firmwares I tried were for the 400k and linuxcnc loaded fine without error. Is there any other way to tell? I couldn't see it on the card or chip.
Can the other 50pin port be assigned for GPIO?
Thanks
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13 Mar 2015 19:18 - 13 Mar 2015 19:19 #56785
by pippin88
Replied by pippin88 on topic 7i43 + 7i76? And where is 7i76E up to?
I've made an attempt to roll my own bitfile.
I downloaded Xilinx ISE Design - 14.7. (Win7)
I downloaded 7i43.zip from mesa website -> unpacked
In ISE Project Navigator I opened seveni43u.xise (7i43\CONFIGS\HOSTMOT2\SOURCE\hostmot2\seveni43u.xise)
In TopUSBHostMot2 I changed it to:
When I attempt to "Generate programming file"
I get error:
ERROR:HDLParsers:804 - "E:/Shed Stuff/7i43/CONFIGS/HOSTMOT2/SOURCE/hostmot2/hostmot2.vhd" Line 1198. Size of ibus is different than size of the target.
If I comment out that whole block, it will generate the file (with a number of warnings that don't seem too serious).
It'll have to wait till morning (it's late in Australia) before I can test the file, but I wan't sure what harm I would be doing by commenting that out.
I downloaded Xilinx ISE Design - 14.7. (Win7)
I downloaded 7i43.zip from mesa website -> unpacked
In ISE Project Navigator I opened seveni43u.xise (7i43\CONFIGS\HOSTMOT2\SOURCE\hostmot2\seveni43u.xise)
In TopUSBHostMot2 I changed it to:
use work.i43_400card.all;
use work.PIN_7I76_34.all;When I attempt to "Generate programming file"
I get error:
ERROR:HDLParsers:804 - "E:/Shed Stuff/7i43/CONFIGS/HOSTMOT2/SOURCE/hostmot2/hostmot2.vhd" Line 1198. Size of ibus is different than size of the target.
1194 nodpllqcratem: if HM2DPLLs = 0 generate
1195 qcountratemx: entity work.qcounteratesk
1196 generic map (clock => ClockLow) -- default encoder clock is 16 MHz
1197 port map(
1198 ibus => ibus(11 downto 0),
1199 loadRate => LoadMuxedQCountRate,
1200 rateout => MuxedQcountFilterRate,
1201 clk => clklow
1202 );
1203 end generate nodpllqcratem;If I comment out that whole block, it will generate the file (with a number of warnings that don't seem too serious).
It'll have to wait till morning (it's late in Australia) before I can test the file, but I wan't sure what harm I would be doing by commenting that out.
Last edit: 13 Mar 2015 19:19 by pippin88.
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13 Mar 2015 19:38 - 13 Mar 2015 22:19 #56786
by PCW
Replied by PCW on topic 7i43 + 7i76? And where is 7i76E up to?
ibus => ibus(11 downto 0),
is simply a mistake from recent encoder dpll shuffling
it should be
ibus => ibus,
The project file should be seveni43.xise
(seveni43u.xise is for a USB connected 7I43)
is simply a mistake from recent encoder dpll shuffling
it should be
ibus => ibus,
The project file should be seveni43.xise
(seveni43u.xise is for a USB connected 7I43)
Last edit: 13 Mar 2015 22:19 by PCW.
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14 Mar 2015 18:06 #56803
by pippin88
Replied by pippin88 on topic 7i43 + 7i76? And where is 7i76E up to?
Thanks PCW, got it working with that changed.
I used seveni43.xise. I'd gone for the USB one because the target device in the summary was the 400k chip, but found on that I could change it on the EPP one.
I customised a pinout file:
Attached is my bit file for a 7i43 and 7i76. The second 7i43 port is just assigned to GPIO. It seems to work ok. I've tested 4 of the stepgens, and the serial IO works with the 7i76. I haven't tested an encoder.
I used seveni43.xise. I'd gone for the USB one because the target device in the summary was the 400k chip, but found on that I could change it on the EPP one.
I customised a pinout file:
library IEEE;
use IEEE.std_logic_1164.all; -- defines std_logic types
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
-- http://www.mesanet.com
--
-- This program is is licensed under a disjunctive dual license giving you
-- the choice of one of the two following sets of free software/open source
-- licensing terms:
--
-- * GNU General Public License (GPL), version 2.0 or later
-- * 3-clause BSD License
--
--
-- The GNU GPL License:
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--
--
-- The 3-clause BSD License:
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- * Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- * Neither the name of Mesa Electronics nor the names of its
-- contributors may be used to endorse or promote products
-- derived from this software without specific prior written
-- permission.
--
--
-- Disclaimer:
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
--
--
--
-- File created by pippin88
-- For 7i43 with 7i76
--
--
use work.IDROMConst.all;
package PIN_7I76_GPIO is
constant ModuleID : ModuleIDType :=(
(HM2DPLLTag, x"00", ClockLowTag, x"01", HM2DPLLBaseRateAddr&PadT, HM2DPLLNumRegs, x"00", HM2DPLLMPBitMask),
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
(IOPortTag, x"00", ClockLowTag, x"02", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
(QcountTag, x"02", ClockLowTag, x"01", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
(SSerialTag, x"00", ClockLowTag, x"01", SSerialCommandAddr&PadT, SSerialNumRegs, x"10", SSerialMPBitMask),
(StepGenTag, x"02", ClockLowTag, x"05", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
);
constant PinDesc : PinDescType :=(
-- Base func sec unit sec func sec pin -- external DB25
IOPortTag & x"00" & StepGenTag & StepGenDirPin, -- I/O 00 PIN 1
IOPortTag & x"00" & StepGenTag & StepGenStepPin, -- I/O 01 PIN 14
IOPortTag & x"01" & StepGenTag & StepGenDirPin, -- I/O 02 PIN 2
IOPortTag & x"01" & StepGenTag & StepGenStepPin, -- I/O 03 PIN 15
IOPortTag & x"02" & StepGenTag & StepGenDirPin, -- I/O 04 PIN 3
IOPortTag & x"02" & StepGenTag & StepGenStepPin, -- I/O 05 PIN 16
IOPortTag & x"03" & StepGenTag & StepGenDirPin, -- I/O 06 PIN 4
IOPortTag & x"03" & StepGenTag & StepGenStepPin, -- I/O 07 PIN 17
IOPortTag & x"04" & StepGenTag & StepGenDirPin, -- I/O 08 PIN 5
IOPortTag & x"04" & StepGenTag & StepGenStepPin, -- I/O 09 PIN 6
IOPortTag & x"00" & SSerialTag & SSerialTX0Pin, -- I/O 10 PIN 7
IOPortTag & x"00" & SSerialTag & SSerialRX0Pin, -- I/O 11 PIN 8
IOPortTag & x"00" & SSerialTag & SSerialTX1Pin, -- I/O 12 PIN 9
IOPortTag & x"00" & SSerialTag & SSerialRX1Pin, -- I/O 13 PIN 10
IOPortTag & x"00" & QCountTag & x"03", -- I/O 14 PIN 11
IOPortTag & x"00" & QCountTag & x"02", -- I/O 15 PIN 12
IOPortTag & x"00" & QCountTag & x"01", -- I/O 16 PIN 13
IOPortTag & x"00" & NullTag & x"00", -- I/O 17 PIN 1
IOPortTag & x"00" & NullTag & x"00", -- I/O 18 PIN 2
IOPortTag & x"00" & NullTag & x"00", -- I/O 19 PIN 3
IOPortTag & x"00" & NullTag & x"00", -- I/O 20 PIN 4
IOPortTag & x"00" & NullTag & x"00", -- I/O 21 PIN 5
IOPortTag & x"00" & NullTag & x"00", -- I/O 22 PIN 6
IOPortTag & x"00" & NullTag & x"00", -- I/O 23 PIN 7
IOPortTag & x"00" & NullTag & x"00", -- I/O 24
IOPortTag & x"00" & NullTag & x"00", -- I/O 25
IOPortTag & x"00" & NullTag & x"00", -- I/O 26
IOPortTag & x"00" & NullTag & x"00", -- I/O 27
IOPortTag & x"00" & NullTag & x"00", -- I/O 28
IOPortTag & x"00" & NullTag & x"00", -- I/O 29
IOPortTag & x"00" & NullTag & x"00", -- I/O 30
IOPortTag & x"00" & NullTag & x"00", -- I/O 31
IOPortTag & x"00" & NullTag & x"00", -- I/O 32
IOPortTag & x"00" & NullTag & x"00", -- I/O 33
IOPortTag & x"00" & NullTag & x"00", -- I/O 34
IOPortTag & x"00" & NullTag & x"00", -- I/O 35
IOPortTag & x"00" & NullTag & x"00", -- I/O 36
IOPortTag & x"00" & NullTag & x"00", -- I/O 37
IOPortTag & x"00" & NullTag & x"00", -- I/O 38
IOPortTag & x"00" & NullTag & x"00", -- I/O 39
IOPortTag & x"00" & NullTag & x"00", -- I/O 40
IOPortTag & x"00" & NullTag & x"00", -- I/O 41
IOPortTag & x"00" & NullTag & x"00", -- I/O 42
IOPortTag & x"00" & NullTag & x"00", -- I/O 43
IOPortTag & x"00" & NullTag & x"00", -- I/O 44
IOPortTag & x"00" & NullTag & x"00", -- I/O 45
IOPortTag & x"00" & NullTag & x"00", -- I/O 46
IOPortTag & x"00" & NullTag & x"00", -- I/O 47
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for IDROM v3
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
end package PIN_7I76_GPIO;Attached is my bit file for a 7i43 and 7i76. The second 7i43 port is just assigned to GPIO. It seems to work ok. I've tested 4 of the stepgens, and the serial IO works with the 7i76. I haven't tested an encoder.
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03 Sep 2017 04:15 - 03 Sep 2017 04:16 #98400
by pippin88
Replied by pippin88 on topic 7i43 + 7i76? And where is 7i76E up to?
My 7i43 + 7i76 combo has been working well.
I now need more stepgens, to enable spindle control (servo driven by a G320x) and other uses. I use the same electronics across a router, mill, and lathe (I have a 48 pin quick swap connector), so my setup needs to be versatile.
I updated my bit file to put 3 additional stepgens and 2 PWM gens (single pin PWM) on the second 7i43 port.
File is attached in case anyone may find it useful.
Comparing the current and previous pin files posted will give some clues to people wanting to make their own custom bitfiles. I had to change the line:to(Note the change in step gen numbers from 5 to 8.
I also had to add a PWM line.
I haven't tested this fully at this stage. It loads on the machine without any error.
Pin File
I now need more stepgens, to enable spindle control (servo driven by a G320x) and other uses. I use the same electronics across a router, mill, and lathe (I have a 48 pin quick swap connector), so my setup needs to be versatile.
I updated my bit file to put 3 additional stepgens and 2 PWM gens (single pin PWM) on the second 7i43 port.
File is attached in case anyone may find it useful.
Comparing the current and previous pin files posted will give some clues to people wanting to make their own custom bitfiles. I had to change the line:
(StepGenTag, x"02", ClockLowTag, x"05",(StepGenTag, x"02", ClockLowTag, x"08",I also had to add a PWM line.
I haven't tested this fully at this stage. It loads on the machine without any error.
Pin File
library IEEE;
use IEEE.std_logic_1164.all; -- defines std_logic types
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
-- http://www.mesanet.com
--
-- This program is is licensed under a disjunctive dual license giving you
-- the choice of one of the two following sets of free software/open source
-- licensing terms:
--
-- * GNU General Public License (GPL), version 2.0 or later
-- * 3-clause BSD License
--
--
-- The GNU GPL License:
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--
--
-- The 3-clause BSD License:
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- * Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- * Neither the name of Mesa Electronics nor the names of its
-- contributors may be used to endorse or promote products
-- derived from this software without specific prior written
-- permission.
--
--
-- Disclaimer:
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
--
--
--
-- File created by pippin88
-- For 7i43 with 7i76
-- 8 Step gens
-- One 50 pin port for 7i76 (with 5 step gens)
-- 2 PWM (single pin)
use work.IDROMConst.all;
package PIN_7I76_7i43_GPIO is
constant ModuleID : ModuleIDType :=(
(HM2DPLLTag, x"00", ClockLowTag, x"01", HM2DPLLBaseRateAddr&PadT, HM2DPLLNumRegs, x"00", HM2DPLLMPBitMask),
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
(IOPortTag, x"00", ClockLowTag, x"02", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
(QcountTag, x"02", ClockLowTag, x"01", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
(SSerialTag, x"00", ClockLowTag, x"01", SSerialCommandAddr&PadT, SSerialNumRegs, x"10", SSerialMPBitMask),
(PWMTag, x"00", ClockHighTag, x"02", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),
(StepGenTag, x"02", ClockLowTag, x"08", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
);
constant PinDesc : PinDescType :=(
-- Base func sec unit sec func sec pin -- external DB25
IOPortTag & x"00" & StepGenTag & StepGenDirPin, -- I/O 00 PIN 1
IOPortTag & x"00" & StepGenTag & StepGenStepPin, -- I/O 01 PIN 14
IOPortTag & x"01" & StepGenTag & StepGenDirPin, -- I/O 02 PIN 2
IOPortTag & x"01" & StepGenTag & StepGenStepPin, -- I/O 03 PIN 15
IOPortTag & x"02" & StepGenTag & StepGenDirPin, -- I/O 04 PIN 3
IOPortTag & x"02" & StepGenTag & StepGenStepPin, -- I/O 05 PIN 16
IOPortTag & x"03" & StepGenTag & StepGenDirPin, -- I/O 06 PIN 4
IOPortTag & x"03" & StepGenTag & StepGenStepPin, -- I/O 07 PIN 17
IOPortTag & x"04" & StepGenTag & StepGenDirPin, -- I/O 08 PIN 5
IOPortTag & x"04" & StepGenTag & StepGenStepPin, -- I/O 09 PIN 6
IOPortTag & x"00" & SSerialTag & SSerialTX0Pin, -- I/O 10 PIN 7
IOPortTag & x"00" & SSerialTag & SSerialRX0Pin, -- I/O 11 PIN 8
IOPortTag & x"00" & SSerialTag & SSerialTX1Pin, -- I/O 12 PIN 9
IOPortTag & x"00" & SSerialTag & SSerialRX1Pin, -- I/O 13 PIN 10
IOPortTag & x"00" & QCountTag & x"03", -- I/O 14 PIN 11
IOPortTag & x"00" & QCountTag & x"02", -- I/O 15 PIN 12
IOPortTag & x"00" & QCountTag & x"01", -- I/O 16 PIN 13
IOPortTag & x"00" & NullTag & x"00", -- I/O 17 PIN 1
IOPortTag & x"00" & NullTag & x"00", -- I/O 18 PIN 2
IOPortTag & x"00" & NullTag & x"00", -- I/O 19 PIN 3
IOPortTag & x"00" & NullTag & x"00", -- I/O 20 PIN 4
IOPortTag & x"00" & NullTag & x"00", -- I/O 21 PIN 5
IOPortTag & x"00" & NullTag & x"00", -- I/O 22 PIN 6
IOPortTag & x"00" & NullTag & x"00", -- I/O 23 PIN 7
IOPortTag & x"05" & StepGenTag & StepGenDirPin, -- I/O 24
IOPortTag & x"05" & StepGenTag & StepGenStepPin, -- I/O 25
IOPortTag & x"06" & StepGenTag & StepGenDirPin, -- I/O 26
IOPortTag & x"06" & StepGenTag & StepGenStepPin, -- I/O 27
IOPortTag & x"07" & StepGenTag & StepGenDirPin, -- I/O 28
IOPortTag & x"07" & StepGenTag & StepGenStepPin, -- I/O 29
IOPortTag & x"00" & PWMTag & PWMAOutPin, -- I/O 30 -- single pin PWM
IOPortTag & x"01" & PWMTag & PWMAOutPin, -- I/O 31 -- single pin PWM
IOPortTag & x"00" & NullTag & x"00", -- I/O 32
IOPortTag & x"00" & NullTag & x"00", -- I/O 33
IOPortTag & x"00" & NullTag & x"00", -- I/O 34
IOPortTag & x"00" & NullTag & x"00", -- I/O 35
IOPortTag & x"00" & NullTag & x"00", -- I/O 36
IOPortTag & x"00" & NullTag & x"00", -- I/O 37
IOPortTag & x"00" & NullTag & x"00", -- I/O 38
IOPortTag & x"00" & NullTag & x"00", -- I/O 39
IOPortTag & x"00" & NullTag & x"00", -- I/O 40
IOPortTag & x"00" & NullTag & x"00", -- I/O 41
IOPortTag & x"00" & NullTag & x"00", -- I/O 42
IOPortTag & x"00" & NullTag & x"00", -- I/O 43
IOPortTag & x"00" & NullTag & x"00", -- I/O 44
IOPortTag & x"00" & NullTag & x"00", -- I/O 45
IOPortTag & x"00" & NullTag & x"00", -- I/O 46
IOPortTag & x"00" & NullTag & x"00", -- I/O 47
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for IDROM v3
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
end package PIN_7I76_7i43_GPIO;
Last edit: 03 Sep 2017 04:16 by pippin88.
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