6i25 + 7i77 + 7i76 + 7i84 I/O port configuration
28 Jan 2017 23:30 #86864
by backtime
6i25 + 7i77 + 7i76 + 7i84 I/O port configuration was created by backtime
Hi, I have this combination of mesa cards, all cards are regularly loaded, but I only have I/O ports available on 7i76 and 7i84, no I/O port on 7i77.
Hostmot2 driver is configured for 6 encoder, 5 step/dir e no pwm.
It may be that the 6i25 have not enough I/O to make available all ports on all cards but I'm not sure about that so I ask for help.
There is a way to have at least one active GPIO port on 7i77 maybe disabling one port on 7i84?
This is the output of driver loading
Hostmot2 driver is configured for 6 encoder, 5 step/dir e no pwm.
It may be that the 6i25 have not enough I/O to make available all ports on all cards but I'm not sure about that so I ask for help.
There is a way to have at least one active GPIO port on 7i77 maybe disabling one port on 7i84?
This is the output of driver loading
[ 26.887814] hm2: loading Mesa HostMot2 driver version 0.15
[ 26.889585] hm2_pci: loading Mesa AnyIO HostMot2 driver version 0.7
[ 26.889607] hm2_pci: discovered 5i25 at 0000:02:00.0
[ 26.890249] hm2/hm2_5i25.0: Smart Serial Firmware Version 43
[ 26.946621] Board hm2_5i25.0.7i77.0.1 Hardware Mode 0 = standard
[ 26.949212] Board hm2_5i25.0.7i77.0.1 Software Mode 0 = analogout_enables
[ 27.030970] Board hm2_5i25.0.7i84.0.2 Hardware Mode 0 = standard
[ 27.033402] Board hm2_5i25.0.7i84.0.2 Software Mode 0 = input_output
[ 27.037022] Board hm2_5i25.0.7i84.0.2 Software Mode 1 = io_analog_fieldvoltage
[ 27.040073] Board hm2_5i25.0.7i84.0.2 Software Mode 2 = io_encoder_analog
[ 27.130964] Board hm2_5i25.0.7i76.0.3 Hardware Mode 0 = standard
[ 27.133032] Board hm2_5i25.0.7i76.0.3 Software Mode 0 = io_spin
[ 27.135717] Board hm2_5i25.0.7i76.0.3 Software Mode 1 = io_ana_spin
[ 27.139594] Board hm2_5i25.0.7i76.0.3 Software Mode 2 = io_enc_ana_spin_fv
[ 27.281681] hm2/hm2_5i25.0: 34 I/O Pins used:
[ 27.281684] hm2/hm2_5i25.0: IO Pin 000 (P3-01): Smart Serial Interface #0, pin TxEn2 (Output)
[ 27.281686] hm2/hm2_5i25.0: IO Pin 001 (P3-14): Smart Serial Interface #0, pin TxData2 (Output)
[ 27.281688] hm2/hm2_5i25.0: IO Pin 002 (P3-02): Smart Serial Interface #0, pin RxData2 (Input)
[ 27.281690] hm2/hm2_5i25.0: IO Pin 003 (P3-15): Smart Serial Interface #0, pin TxData1 (Output)
[ 27.281692] hm2/hm2_5i25.0: IO Pin 004 (P3-03): Smart Serial Interface #0, pin RxData1 (Input)
[ 27.281693] hm2/hm2_5i25.0: IO Pin 005 (P3-16): IOPort
[ 27.281695] hm2/hm2_5i25.0: IO Pin 006 (P3-04): IOPort
[ 27.281697] hm2/hm2_5i25.0: IO Pin 007 (P3-17): Muxed Encoder Select #0, pin Mux Select 0 (Output)
[ 27.281698] hm2/hm2_5i25.0: IO Pin 008 (P3-05): Muxed Encoder #0, pin Muxed A (Input)
[ 27.281700] hm2/hm2_5i25.0: IO Pin 009 (P3-06): Muxed Encoder #0, pin Muxed B (Input)
[ 27.281702] hm2/hm2_5i25.0: IO Pin 010 (P3-07): Muxed Encoder #0, pin Muxed Index (Input)
[ 27.281703] hm2/hm2_5i25.0: IO Pin 011 (P3-08): Muxed Encoder #1, pin Muxed A (Input)
[ 27.281705] hm2/hm2_5i25.0: IO Pin 012 (P3-09): Muxed Encoder #1, pin Muxed B (Input)
[ 27.281707] hm2/hm2_5i25.0: IO Pin 013 (P3-10): Muxed Encoder #1, pin Muxed Index (Input)
[ 27.281708] hm2/hm2_5i25.0: IO Pin 014 (P3-11): Muxed Encoder #2, pin Muxed A (Input)
[ 27.281710] hm2/hm2_5i25.0: IO Pin 015 (P3-12): Muxed Encoder #2, pin Muxed B (Input)
[ 27.281712] hm2/hm2_5i25.0: IO Pin 016 (P3-13): Muxed Encoder #2, pin Muxed Index (Input)
[ 27.281714] hm2/hm2_5i25.0: IO Pin 017 (P2-01): StepGen #0, pin Direction (Output)
[ 27.281715] hm2/hm2_5i25.0: IO Pin 018 (P2-14): StepGen #0, pin Step (Output)
[ 27.281717] hm2/hm2_5i25.0: IO Pin 019 (P2-02): StepGen #1, pin Direction (Output)
[ 27.281719] hm2/hm2_5i25.0: IO Pin 020 (P2-15): StepGen #1, pin Step (Output)
[ 27.281720] hm2/hm2_5i25.0: IO Pin 021 (P2-03): StepGen #2, pin Direction (Output)
[ 27.281722] hm2/hm2_5i25.0: IO Pin 022 (P2-16): StepGen #2, pin Step (Output)
[ 27.281723] hm2/hm2_5i25.0: IO Pin 023 (P2-04): StepGen #3, pin Direction (Output)
[ 27.281725] hm2/hm2_5i25.0: IO Pin 024 (P2-17): StepGen #3, pin Step (Output)
[ 27.281727] hm2/hm2_5i25.0: IO Pin 025 (P2-05): StepGen #4, pin Direction (Output)
[ 27.281728] hm2/hm2_5i25.0: IO Pin 026 (P2-06): StepGen #4, pin Step (Output)
[ 27.281730] hm2/hm2_5i25.0: IO Pin 027 (P2-07): Smart Serial Interface #0, pin TxData3 (Output)
[ 27.281732] hm2/hm2_5i25.0: IO Pin 028 (P2-08): Smart Serial Interface #0, pin RxData3 (Input)
[ 27.281733] hm2/hm2_5i25.0: IO Pin 029 (P2-09): IOPort
[ 27.281735] hm2/hm2_5i25.0: IO Pin 030 (P2-10): IOPort
[ 27.281736] hm2/hm2_5i25.0: IO Pin 031 (P2-11): Muxed Encoder #3, pin Muxed Index (Input)
[ 27.281738] hm2/hm2_5i25.0: IO Pin 032 (P2-12): Muxed Encoder #3, pin Muxed B (Input)
[ 27.281740] hm2/hm2_5i25.0: IO Pin 033 (P2-13): Muxed Encoder #3, pin Muxed A (Input)
[ 27.281790] hm2/hm2_5i25.0: registered
[ 27.281792] hm2_5i25.0: initialized AnyIO board at 0000:02:00.0Please Log in or Create an account to join the conversation.
29 Jan 2017 00:14 #86865
by PCW
Replied by PCW on topic 6i25 + 7i77 + 7i76 + 7i84 I/O port configuration
There is no I/O limitation
Are you sure the 7I77 has Field power and VIN?
You might also check you cabling and 7I77 5V level
Are you sure the 7I77 has Field power and VIN?
You might also check you cabling and 7I77 5V level
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29 Jan 2017 00:31 #86866
by backtime
Replied by backtime on topic 6i25 + 7i77 + 7i76 + 7i84 I/O port configuration
5V came from 6i25 an since all six encoders are connected an work with no problem I think this is correct. Field power is on the same line of 7i76 and in both boards jumper are set to connect VIN to field power. Also 7i84 have power on VFIELDA and VFIELDB and jumper connect VIN to VFIELDB.
May be the 7i77 field power in not properly connected, I'll double check to see what could be wrong.
Thanks.
May be the 7i77 field power in not properly connected, I'll double check to see what could be wrong.
Thanks.
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29 Jan 2017 00:47 - 29 Jan 2017 00:48 #86869
by PCW
Replied by PCW on topic 6i25 + 7i77 + 7i76 + 7i84 I/O port configuration
Its generally not suggested to use FPGA/cable 5V for the 7I77 especially if you have a lot of encoders
The 5V levels may be marginal
The 5V levels may be marginal
Last edit: 29 Jan 2017 00:48 by PCW.
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29 Jan 2017 00:50 - 29 Jan 2017 00:51 #86870
by tommylight
Replied by tommylight on topic 6i25 + 7i77 + 7i76 + 7i84 I/O port configuration
If i remember correctly, you should have smart serial on both ports of 5i25 to be able to use 7i76 and 7i77. On your config you have one sserial for doughtercards not two, so i think you are using the wrong config on the 5i25.
There should be no stepgens from 5i25 if you have a 7i76 attached, they should be on the 7i76.
Please do check that and report back.
PCW please correct me if i am wrong.
There should be no stepgens from 5i25 if you have a 7i76 attached, they should be on the 7i76.
Please do check that and report back.
PCW please correct me if i am wrong.
Last edit: 29 Jan 2017 00:51 by tommylight.
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29 Jan 2017 00:57 #86872
by PCW
Replied by PCW on topic 6i25 + 7i77 + 7i76 + 7i84 I/O port configuration
No, the pinout listing looks OK except the 7I77 digital I/O section was not found
(it would be TXData0 on GPIO5 and RXData0 on GPIO6 if the 7I77s digital I/O section was found)
(it would be TXData0 on GPIO5 and RXData0 on GPIO6 if the 7I77s digital I/O section was found)
The following user(s) said Thank You: tommylight
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29 Jan 2017 12:17 - 29 Jan 2017 12:21 #86894
by backtime
The low 5V level may be the cause of the absence of I/O pins of 7i77?
Anyway tomorrow I'll provide external 5V to 7i77, for 7i76 i can use FPGA 5V or is better to use external power for both?
So if I understand correctly the sserial modules represent the I/O ports?
For example I found the following code in 5i25_7i77_7i76.xml, it represent one of the I/O port of the 7i76 I'm correct?
I forgot to say that the machine is already in operation, all step/gen, encoders and 7i76 I/O port are in use and work, I realize the lack of I/O port on 7i77 only because I run out I/O on 7i76.
Replied by backtime on topic 6i25 + 7i77 + 7i76 + 7i84 I/O port configuration
Its generally not suggested to use FPGA/cable 5V for the 7I77 especially if you have a lot of encoders
The 5V levels may be marginal
The low 5V level may be the cause of the absence of I/O pins of 7i77?
Anyway tomorrow I'll provide external 5V to 7i77, for 7i76 i can use FPGA 5V or is better to use external power for both?
No, the pinout listing looks OK except the 7I77 digital I/O section was not found
(it would be TXData0 on GPIO5 and RXData0 on GPIO6 if the 7I77s digital I/O section was found)
So if I understand correctly the sserial modules represent the I/O ports?
For example I found the following code in 5i25_7i77_7i76.xml, it represent one of the I/O port of the 7i76 I'm correct?
<pin>
<connector>P2</connector>
<secondarymodulename>SSerial</secondarymodulename>
<secondaryfunctionname>TXData4 (out)</secondaryfunctionname>
<secondaryinstance> 0</secondaryinstance>
</pin>
<pin>
<connector>P2</connector>
<secondarymodulename>SSerial</secondarymodulename>
<secondaryfunctionname>RXData4 (in)</secondaryfunctionname>
<secondaryinstance> 0</secondaryinstance>
</pin>I forgot to say that the machine is already in operation, all step/gen, encoders and 7i76 I/O port are in use and work, I realize the lack of I/O port on 7i77 only because I run out I/O on 7i76.
Last edit: 29 Jan 2017 12:21 by backtime.
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30 Jan 2017 10:40 #86955
by backtime
Replied by backtime on topic 6i25 + 7i77 + 7i76 + 7i84 I/O port configuration
I put external 5V power to 7i77 and 7i76, double check field power on both card, nothing changes, 7i77 I/O are not enable, CR3 led (field voltage) is on but also CR16 (I/O fault red LED) remain lit.
All other board function properly, I don't know what else I can do. May be a fault on board?
All other board function properly, I don't know what else I can do. May be a fault on board?
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30 Jan 2017 11:12 #86956
by backtime
Replied by backtime on topic 6i25 + 7i77 + 7i76 + 7i84 I/O port configuration
I have another question, what is the correct firmware to load, i found two bit files, 5i25_7i76_7i77.bit and 5i25_7i77_7i76.bit, I think I have put the 5i25_7i77_7i76.bit file, is the correct firmware? I have 7i76 on P2 and 7i77 on P3.
Thanks
Thanks
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30 Jan 2017 15:20 #86972
by PCW
Replied by PCW on topic 6i25 + 7i77 + 7i76 + 7i84 I/O port configuration
5i25_7i77_7i76.bit is correct for a 7I77 on P3
You may have a bad/damaged 6I25 or bad/damaged 7I77
You might try the other 5i25_7i76_7i77.bit firmware and swap the 7I77 / 7I76
to determine if the problem is in the 7I77 or 6i25
( note, when changing firmware, you need to do a mesaflash "reload" before the new firmware can be used )
You may have a bad/damaged 6I25 or bad/damaged 7I77
You might try the other 5i25_7i76_7i77.bit firmware and swap the 7I77 / 7I76
to determine if the problem is in the 7I77 or 6i25
( note, when changing firmware, you need to do a mesaflash "reload" before the new firmware can be used )
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