[SOLVED] 7i90 25Mhz oscillator on Dev-Board

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11 Mar 2021 09:56 - 11 Mar 2021 22:13 #201787 by pauluzs
Currently i'm trying to adapt the 7i90 firmware on a xc6slx16 FT(G)256 Dev-Board
So i already changed:
  • The matching pinout in the .ucf file
  • The package type in the.xise file
  • The pincount and fpga size in the i90_x9card file

The thing that is not quite clear to me is : Where and which clock settings to changed, since the board has a 25Mhz oscillator instead the 50Mhz on the original board. Which clocks and/or setting should be changed, and what are they used for?
I found the following:

i90_x9card.vhd > IDROMConst.vhd
  • constant ClockHigh90: integer := 200000000;
  • constant ClockMed90: integer := 100000000;
  • constant ClockLow90: integer := 100000000

7i90spi.ucf
  • TIMESPEC "TS_CLK" = PERIOD "CLK" 19.9 ns HIGH 50 %;
  • TIMESPEC "TS_COM_SPICLK" = PERIOD "COM_SPICLK" 9 ns HIGH 50 %;

TopGCSPIHostMot2.vhd
  • signal fclk : std_logic;
    signal clkfx0: std_logic;
    signal clk0_0: std_logic;
    signal clklow : std_logic;
    signal clkfx1: std_logic;
    signal clk0_1: std_logic;

  • clklow => clklow, -- I/O clock
    clkmed => clklow, -- Processor clock
    clkhigh => fclk, -- PWM clock

  • ClockMultH : DCM
    generic map (
    CLKDV_DIVIDE => 2.0,
    CLKFX_DIVIDE => 2,
    CLKFX_MULTIPLY => 8, -- 8 FOR 200 MHz
    CLKIN_DIVIDE_BY_2 => FALSE,
    CLKIN_PERIOD => 20.0,

  • ClockMultM : DCM
    generic map (
    CLKDV_DIVIDE => 2.0,
    CLKFX_DIVIDE => 2,
    CLKFX_MULTIPLY => 4, -- 4 FOR 100 MHz
    CLKIN_DIVIDE_BY_2 => FALSE,
    CLKIN_PERIOD => 20.0,

  • asimplspi: entity work.simplespi8 -- configuration serial EEPROM access SPI port
    generic map
    (
    buswidth => 8,
    div => 7, -- for divide by 8 -- 12.5 MHz

Should only the clk periods be changed from 20 to 40, or should the clk dividers also be adapted?
Thanks in advance,
Last edit: 11 Mar 2021 22:13 by pauluzs.

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11 Mar 2021 15:45 - 11 Mar 2021 15:52 #201825 by PCW
You would change

ClockMultH CLKFX_MULTIPLY to 16
ClockMultM CLKFX_MULTIPLY to 8

TIMESPEC "TS_CLK" = PERIOD "CLK" 39.8 ns HIGH 50 %;

and both clock periods to 40
Last edit: 11 Mar 2021 15:52 by PCW.
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11 Mar 2021 22:09 #201885 by pauluzs
Thanks ,

With those setting i can confirm the RV901T Led Receiving board as working having 72 5v outputs.

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26 Mar 2024 19:55 - 26 Mar 2024 19:56 #296831 by ago_tm
Hello pauluzs,

Thanks ,

With those setting i can confirm the RV901T Led Receiving board as working having 72 5v outputs.


Could you kindly share the final changes you did for the hostmot2 xilinx sources or take a look at my github.com/golyakoff/hostmot2-rv901t-7i90/commits/master ? I tried to follow your instruction but get stucked...

It builds but SPI I see garbage on the SPI MISO: here are the details... forum.linuxcnc.org/38-general-linuxcnc-q...king?start=10#296830.

Thank you in advance!
Last edit: 26 Mar 2024 19:56 by ago_tm.

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