MESA 7i76+7i89 Watchdog timeout

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10 Mar 2022 15:52 #236857 by Faggan
Hello,

I am in the process of building a new machine and I hit an obstacle i cant google my way out of. 

I want to run a Mesa 6i25 (as 5i25) with a 7i76 and 7i89. The 7i76 with the 5i25_7i76x2 firmware works fine on its own. I made a config with pncconf to test the 7i76. But when I flash to 5i25_7i76_7i89 and update the pncconf to a 7i76+7i77 I have issues. 

When I launch the CNC application it cant find "hm2_5i25.1.watchdog.timeout_ns". I suspected that the issue may be that pncconf sets the config to expect a 7i77 since i picked that. But for encoder signals i cant see a reference to the board type in the hal file. Only on in/outputs. 

Running mesaflash --device 5i25 --readhmid tells me there is only one watchdog in the configuration. But removing the watchdog line in hal results in errors further down the file instead (hm2_5i25.1.read not found etc..). 

I don't know where to start looking. I cant exclude that the DB25 connection is faulty somehow. But the power LED on the 7i89 comes on and according to the manual its switched by the power supplied from the 6i25 so something is working at least. 

I have looked through the config files and cant find any reference to the board type. Are there other files hidden somewhere that point to what board is being used or could this be a firmware error? 

Any help is greatly appreciated!

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10 Mar 2022 16:43 #236861 by PCW
Replied by PCW on topic MESA 7i76+7i89 Watchdog timeout
Sounds like pncconf thinks there are two FPGA cards

I would first get a working 7I76 configuration file set and then use that
as a base to add the 7I89 encoder setup (this could be copy-pasted from a
7I77 hal/ini file)

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10 Mar 2022 17:40 #236866 by tommylight

When I launch the CNC application it cant find "hm2_5i25.1.watchdog.timeout_ns". !

If you have only one card in the PC, i think it should be:
hm2_5i25.0.watchdog.timeout_ns
Notice the 0.

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10 Mar 2022 18:08 - 10 Mar 2022 18:10 #236868 by Faggan

Sounds like pncconf thinks there are two FPGA cards

I would first get a working 7I76 configuration file set and then use that
as a base to add the 7I89 encoder setup (this could be copy-pasted from a
7I77 hal/ini file)

Oh, I see. Well it thinks that because I told it there was. I didnt realize the "mesa1 PCI/ Eth0/ Parport Card" parameter was referring to a second FPGA. 

If you have only one card in the PC, i think it should be:
hm2_5i25.0.watchdog.timeout_ns
Notice the 0.

Yes, I assumed that the watchdog was carried to the IO cards and not the FPGA. By extension I thought the 0 would be 7i76 and 1 would then be 7i89 in my case. Live and learn!

But that leads me onto another question then. How would I know the signal address for the encoders. The inputs and outputs refer to the board in question hm2_5i25.0.7i76.0.0.input-16 for example. But the encoders dont contain the board name in the address structure (IE hm2_5i25.0.encoder.00.xxxx). How can I find out which encoder is which?
Last edit: 10 Mar 2022 18:10 by Faggan. Reason: Bad formating

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10 Mar 2022 18:15 #236869 by PCW
Replied by PCW on topic MESA 7i76+7i89 Watchdog timeout
Pretty sure the 7i76+7i89 firmware maps the encoders so encoder 0 through 7
are on the 7I89 (and the 7I76 spindle encoder is encoder 8 )

You can verify with :

sudo mesaflash --device 5i25 --readhmid

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10 Mar 2022 18:19 - 10 Mar 2022 18:19 #236870 by Faggan
Ok. When i run that i get (among other things):

IO Connections for P3
Pin#  I/O   Pri. func    Sec. func       Chan      Pin func        Pin Dir

 1      0   IOPort       StepGen          0        Dir/Table2      (Out)
14      1   IOPort       StepGen          0        Step/Table1     (Out)
 2      2   IOPort       StepGen          1        Dir/Table2      (Out)
15      3   IOPort       StepGen          1        Step/Table1     (Out)
 3      4   IOPort       StepGen          2        Dir/Table2      (Out)
16      5   IOPort       StepGen          2        Step/Table1     (Out)
 4      6   IOPort       StepGen          3        Dir/Table2      (Out)
17      7   IOPort       StepGen          3        Step/Table1     (Out)
 5      8   IOPort       StepGen          4        Dir/Table2      (Out)
 6      9   IOPort       StepGen          4        Step/Table1     (Out)
 7     10   IOPort       SSerial          0        TXData0         (Out)
 8     11   IOPort       SSerial          0        RXData0         (In)
 9     12   IOPort       SSerial          0        TXData1         (Out)
10     13   IOPort       SSerial          0        RXData1         (In)
11     14   IOPort       MuxedQCount      4        MuxQ-IDX        (In)
12     15   IOPort       MuxedQCount      4        MuxQ-B          (In)
13     16   IOPort       MuxedQCount      4        MuxQ-A          (In)

IO Connections for P2
Pin#  I/O   Pri. func    Sec. func       Chan      Pin func        Pin Dir

 1     17   IOPort       MuxedQCount      0        MuxQ-A          (In)
14     18   IOPort       MuxedQCount      0        MuxQ-B          (In)
 2     19   IOPort       MuxedQCount      0        MuxQ-IDX        (In)
15     20   IOPort       MuxedQCount      1        MuxQ-A          (In)
 3     21   IOPort       MuxedQCount      1        MuxQ-B          (In)
16     22   IOPort       MuxedQCount      1        MuxQ-IDX        (In)
 4     23   IOPort       MuxedQCount      2        MuxQ-A          (In)
17     24   IOPort       MuxedQCount      2        MuxQ-B          (In)
 5     25   IOPort       MuxedQCount      2        MuxQ-IDX        (In)
 6     26   IOPort       MuxedQCount      3        MuxQ-A          (In)
 7     27   IOPort       MuxedQCount      3        MuxQ-B          (In)
 8     28   IOPort       MuxedQCount      3        MuxQ-IDX        (In)
 9     29   IOPort       MuxedQCountSel   0        MuxSel0         (Out)
10     30   IOPort       None           
11     31   IOPort       SSerial          0        RXData3         (In)
12     32   IOPort       SSerial          0        TXData3         (Out)
13     33   IOPort       SSerial          0        TXEn3           (Out)


But isnt the 7i89 supposed to have 8 encoders?
Last edit: 10 Mar 2022 18:19 by Faggan.

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10 Mar 2022 18:24 - 10 Mar 2022 18:31 #236871 by PCW
Replied by PCW on topic MESA 7i76+7i89 Watchdog timeout
It does, encoders 0..7

Muxed encoders combine even/odd inputs on a single pin
so each muxed encoder pin connects to two encoder counters.
(so muxed encoder 0's pins are for encoders 0 and 1,
muxed encoder 1's pins are for encoders 2 and 3 etc)
Last edit: 10 Mar 2022 18:31 by PCW.

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10 Mar 2022 18:44 #236874 by Faggan
I wont pretend I understood that fully. Im sorry..

When you say "Pin" you mean physical or software?

What would that look like in address format then? 
Physical encoder 0 on 7i89: hm2_5i25.0.encoder.00.xxx
Physical encoder 1 on 7i89: hm2_5i25.0.encoder.10.xxx
Physical encoder 2 on 7i89: hm2_5i25.0.encoder.01.xxx
Physical encoder 3 on 7i89: hm2_5i25.0.encoder.11.xxx

Like that?

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10 Mar 2022 19:10 #236879 by PCW
Replied by PCW on topic MESA 7i76+7i89 Watchdog timeout
That looks about right, but you don't need to guess:

run LinuxCNC and then in a terminal type:

halcmd show all hm2

for a list of all hardware pins/parameters

You can also redirect the output to a file for hal file copy/paste purposes:

halcmd show all hm2 > hardware.txt

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10 Mar 2022 21:28 #236893 by Faggan
Thats great!

Thank you for the help this will get me moving for a while. 

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