Adding 7i95T configuration to PnCConf
06 Oct 2023 08:17 #282429
by merongi
Adding 7i95T configuration to PnCConf was created by merongi
Hi,
I'm trying to add 7i95T configuration to PnCConf. Istarted with "ADDING_A_MESA_CARD.md" and made through most of the changes on private_data.py
It seems stepgen part are working. But GPIO seems odd. I added 30 GPIO (24 In/6 Out in 7i95T) and GPIO numbers start from "048" and it generate hal entry aswhere mesact2 created following working hal line
I'm not sure what have I done wrong. Any help would be appreciated.
Here are my structures added.
I'm trying to add 7i95T configuration to PnCConf. Istarted with "ADDING_A_MESA_CARD.md" and made through most of the changes on private_data.py
It seems stepgen part are working. But GPIO seems odd. I added 30 GPIO (24 In/6 Out in 7i95T) and GPIO numbers start from "048" and it generate hal entry as
net home-x <= hm2_7i95.0.gpio.048.innet joint-0-home jjoint.0.home-sw-in <= hm2_7i95.0.inmux.00.input-18I'm not sure what have I done wrong. Any help would be appreciated.
Here are my structures added.
'7i95':{'DRIVER':'hm2_eth','PINS_PER_CONNECTOR':24,'TOTAL_CONNECTORS':4,'TAB_NUMS':[1,2,3,4],'TAB_NAMES':['TB3/TB4','TB1/TB2','TB5','TB6']}, ['7i95t-Internal Data', '7i95', '7i95t_d', '7i95t', 'hm2_eth',
6, #5 max encoders
3, #6 num pins per encoder
0, #7 max resolver gens
0, #8 num pins per resolver gen
0, #9 max num pwmgen
0, #10 num pins per pwmgen
0, #11 max num of tppwmgens
0, #12 num pins per tppwmgen
6, #13 max num of stepgen
2, #14 num pins per stepgen
2, #15 max smart serial
2, #16 num of channels
[],0,0,0,0,0,0,0, #discovered sserial devices and spare 18~24
1, #25 has watchdog
30,#26 max GPIO
33, #27 low freq rate
200, #28 hi freq rate
[1, 2, 3, 4], #29 available connector numbers
# TAB 1
[S.STEPB,0],[S.STEPA,0],[S.STEPB,1],[S.STEPA,1],[S.STEPB,2],[S.STEPA,2],[S.STEPB,3],[S.STEPA,3],
[S.STEPB,4],[S.STEPA,4],[S.STEPB,5],[S.STEPA,5],[S.RXDATA0,0],[S.TXDATA0,0],[S.RXDATA1,0],[S.TXDATA1,0],
[S.TXEN0,0],[S.TXEN1,0],[S.NUSED,0],[S.NUSED,0],[S.NUSED,0],[S.NUSED,0],[S.NUSED,0],[S.NUSED,0],
# TAB 2
[S.ENCI,0],[S.ENCB,0],[S.ENCA,0],[S.ENCI,1],[S.ENCB,1],[S.ENCA,1],
[S.ENCI,2],[S.ENCB,2],[S.ENCA,2],[S.ENCI,3],[S.ENCB,3],[S.ENCA,3],
[S.ENCI,4],[S.ENCB,4],[S.ENCA,4],[S.ENCI,5],[S.ENCB,5],[S.ENCA,5],
[S.NUSED,0],[S.NUSED,0],[S.NUSED,0],[S.NUSED,0],[S.NUSED,0],[S.NUSED,0],
# TAB 3
[S.GPIOI, 0],[S.GPIOI, 0],[S.GPIOI, 0],[S.GPIOI, 0],[S.GPIOI, 0],[S.GPIOI, 0],[S.GPIOI, 0],[S.GPIOI, 0],
[S.GPIOI, 0],[S.GPIOI, 0],[S.GPIOI, 0],[S.GPIOI, 0],[S.GPIOI, 0],[S.GPIOI, 0],[S.GPIOI, 0],[S.GPIOI, 0],
[S.GPIOI, 0],[S.GPIOI, 0],[S.GPIOI, 0],[S.GPIOI, 0],[S.GPIOI, 0],[S.GPIOI, 0],[S.GPIOI, 0],[S.GPIOI, 0],
# TAB 4
[S.GPIOI, 0],[S.GPIOI, 0],[S.GPIOI, 0],[S.GPIOI, 0],[S.GPIOI, 0],[S.GPIOI, 0],[S.NUSED,0],[S.NUSED,0],
[S.NUSED,0], [S.NUSED,0], [S.NUSED,0], [S.NUSED,0], [S.NUSED,0], [S.NUSED,0], [S.NUSED,0],[S.NUSED,0],
[S.NUSED,0], [S.NUSED,0], [S.NUSED,0], [S.NUSED,0], [S.NUSED,0], [S.NUSED,0], [S.NUSED,0],[S.NUSED,0],],Please Log in or Create an account to join the conversation.
07 Oct 2023 22:47 #282520
by cmorley
Replied by cmorley on topic Adding 7i95T configuration to PnCConf
take a look at pncconf.py
def make_pinname
I think that adjusts pin numbers
def make_pinname
I think that adjusts pin numbers
Please Log in or Create an account to join the conversation.
09 Oct 2023 08:45 #282593
by merongi
Replied by merongi on topic Adding 7i95T configuration to PnCConf
Ok. It took quite some time to figure out the pin mappings in private_data are not physical connector map. So six encoders actually should be mapped into MXEx.
But on the other hand, INM has to be enumerated to actual input pin number instead of exact pin mapping. I'm still confused the concept but it works for now.
The only problem is that INM0 is translated into
hm2_7i95.0.inm.00.input-%02d
But it crashes LCNC as it can't find "inm" port.
So I had to add mapping them as
hm2_7i95.0.inmux.00.input-%02d
as MesaCT does, then it works with LCNC.
Is this typical? or "inm" configuration is never tested?
Also, looking for a way to add different serial vfd (nowforever). Is there a configurable way? or it has to be added into source code? I tried and it involves bunch of glades and buildHAL code update.
But on the other hand, INM has to be enumerated to actual input pin number instead of exact pin mapping. I'm still confused the concept but it works for now.
The only problem is that INM0 is translated into
hm2_7i95.0.inm.00.input-%02d
But it crashes LCNC as it can't find "inm" port.
So I had to add mapping them as
hm2_7i95.0.inmux.00.input-%02d
as MesaCT does, then it works with LCNC.
Is this typical? or "inm" configuration is never tested?
Also, looking for a way to add different serial vfd (nowforever). Is there a configurable way? or it has to be added into source code? I tried and it involves bunch of glades and buildHAL code update.
The following user(s) said Thank You: tommylight
Please Log in or Create an account to join the conversation.
11 Oct 2023 04:37 #282722
by merongi
Replied by merongi on topic Adding 7i95T configuration to PnCConf
What would be the way to contribute back these changes into LCNC?
Git clone and commit to pull request?
BTW, is "inm" correct for other board and only 7i95 uses "inmux" for the muxed inputs?
Git clone and commit to pull request?
BTW, is "inm" correct for other board and only 7i95 uses "inmux" for the muxed inputs?
Please Log in or Create an account to join the conversation.
11 Oct 2023 14:02 - 11 Oct 2023 14:03 #282752
by PCW
Replied by PCW on topic Adding 7i95T configuration to PnCConf
inm is used on the 7I96S
inm can actually can be used on any FPGA card
but its in all standard 7I96S firmware
The 7I95,7I95T,7I97,7C80, and 7I36 all use inmux
inm can actually can be used on any FPGA card
but its in all standard 7I96S firmware
The 7I95,7I95T,7I97,7C80, and 7I36 all use inmux
Last edit: 11 Oct 2023 14:03 by PCW.
Please Log in or Create an account to join the conversation.
Moderators: cmorley
Time to create page: 0.152 seconds