Mesa: Digital Filters

signal FilterReg: std_logic_vector(7 downto 0) := std_logic_vector(to_unsigned(integer(defaultfilter),8)); signal FilterCount: std_logic_vector(7 downto 0); signal RXDataD: std_logic; signal RXDataFilt: std_logic;

/* http://freeby.mesanet.com/regmap The PktUARTrMode register is used for setting and checking the PktUARTr's operation mode, timing, and status Bit 31..30 Unused Bit 29..22 Filter Register Bit 21 FrameBuffer has data Bits 20..16 Frames received Bits 15..8 InterFrame delay in bit times Bit 7 Receive Logic active, not an error Bit 6 RXMask Bit 5 Unused Bit 4 RCFIFO Error Bit 3 RXEnable (must be set to receive packets) Bit 2 RXMask Enable (enables input data masking when transmitting) Bit 1 Overrun error (no stop bit when expected) (sticky) Bit 0 False Start bit error (sticky) */ if (rx_mode >= 0) { // read filter settings from rx register before setting new values r += hm2->llio->read(hm2->llio, inst->rx_mode_addr, &buff, sizeof(u32)); buff = (((u32)rx_mode) & 0xffff) | (buff & (0xFF << 22)); r += hm2->llio->write(hm2->llio, inst->rx_mode_addr, &buff, sizeof(u32)); }