Mesa 7i96 Inputs

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8 years 4 months ago #111513 by thadwald
Mesa 7i96 Inputs was created by thadwald
Can anyone tell me if the following is the correct way to address the input pins on the Mesa 7i96 boards:

input zero:
hm2_7i96.0.gpio.000.in

input one:
hm2_7i96.0.gpio.001.in

...

The board has only 0-11 broken out on terminal blocks, but in HALShow, I can see up to 050

Thanks

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8 years 4 months ago #111516 by PCW
Replied by PCW on topic Mesa 7i96 Inputs
Yes, standard firmware maps GPIO 0..10 to 7I96 TB3 inputs 0..10

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8 years 4 months ago #111527 by thadwald
Replied by thadwald on topic Mesa 7i96 Inputs
Thanks!

Are gpio 11 to 50 broken out on the board?

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8 years 4 months ago #111529 by PCW
Replied by PCW on topic Mesa 7i96 Inputs
With HM2 firmware, all I/O pins have GPIO capability so even pins normally used for things like stepgenerators can be used as GPIO, so the GPIO 0..50 represent all I/O pins including the expansion connector I/O. If you run mesaflash with the readhmid option you can get a listing of the I/O mapping.

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8 years 4 months ago #111530 by thadwald
Replied by thadwald on topic Mesa 7i96 Inputs

PCW wrote: If you run mesaflash with the readhmid option you can get a listing of the I/O mapping.


That is exactly what I was looking for. Thanks!

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8 years 4 months ago #111532 by PCW
Replied by PCW on topic Mesa 7i96 Inputs
I should mention that this needs to be the latest version of mesaflash that "knows" about the 7I96 pinout
Code:
Configuration Name: HOSTMOT2 General configuration information: BoardName : MESA7I96 FPGA Size: 9 KGates FPGA Pins: 144 Number of IO Ports: 3 Width of one I/O port: 17 Clock Low frequency: 100.0000 MHz Clock High frequency: 200.0000 MHz IDROM Type: 3 Instance Stride 0: 4 Instance Stride 1: 64 Register Stride 0: 256 Register Stride 1: 256 Modules in configuration: Module: DPLL There are 1 of DPLL in configuration Version: 0 Registers: 7 BaseAddress: 7000 ClockFrequency: 100.000 MHz Register Stride: 256 bytes Instance Stride: 4 bytes Module: WatchDog There are 1 of WatchDog in configuration Version: 0 Registers: 3 BaseAddress: 0C00 ClockFrequency: 100.000 MHz Register Stride: 256 bytes Instance Stride: 4 bytes Module: IOPort There are 3 of IOPort in configuration Version: 0 Registers: 5 BaseAddress: 1000 ClockFrequency: 100.000 MHz Register Stride: 256 bytes Instance Stride: 4 bytes Module: StepGen There are 5 of StepGen in configuration Version: 2 Registers: 10 BaseAddress: 2000 ClockFrequency: 100.000 MHz Register Stride: 256 bytes Instance Stride: 4 bytes Module: QCount There are 1 of QCount in configuration Version: 2 Registers: 5 BaseAddress: 3000 ClockFrequency: 100.000 MHz Register Stride: 256 bytes Instance Stride: 4 bytes Module: SSerial There are 2 of SSerial in configuration Version: 0 Registers: 6 BaseAddress: 5B00 ClockFrequency: 100.000 MHz Register Stride: 256 bytes Instance Stride: 64 bytes Module: SSR There are 1 of SSR in configuration Version: 0 Registers: 2 BaseAddress: 7D00 ClockFrequency: 100.000 MHz Register Stride: 256 bytes Instance Stride: 4 bytes Module: LED There are 1 of LED in configuration Version: 0 Registers: 1 BaseAddress: 0200 ClockFrequency: 100.000 MHz Register Stride: 256 bytes Instance Stride: 4 bytes Configuration pin-out: IO Connections for TB3 Pin# I/O Pri. func Sec. func Chan Pin func Pin Dir 1 0 IOPort None 14 1 IOPort None 2 2 IOPort None 15 3 IOPort None 3 4 IOPort None 16 5 IOPort None 4 6 IOPort None 17 7 IOPort None 5 8 IOPort None 6 9 IOPort None 7 10 IOPort None 8 11 IOPort SSR 0 Out-00 (Out) 9 12 IOPort SSR 0 Out-01 (Out) 10 13 IOPort SSR 0 Out-02 (Out) 11 14 IOPort SSR 0 Out-03 (Out) 12 15 IOPort SSR 0 Out-04 (Out) 13 16 IOPort SSR 0 Out-05 (Out) IO Connections for TB1/TB2 Pin# I/O Pri. func Sec. func Chan Pin func Pin Dir 1 17 IOPort StepGen 0 Step/Table1 (Out) 14 18 IOPort StepGen 0 Dir/Table2 (Out) 2 19 IOPort StepGen 1 Step/Table1 (Out) 15 20 IOPort StepGen 1 Dir/Table2 (Out) 3 21 IOPort StepGen 2 Step/Table1 (Out) 16 22 IOPort StepGen 2 Dir/Table2 (Out) 4 23 IOPort StepGen 3 Step/Table1 (Out) 17 24 IOPort StepGen 3 Dir/Table2 (Out) 5 25 IOPort StepGen 4 Step/Table1 (Out) 6 26 IOPort StepGen 4 Dir/Table2 (Out) 7 27 IOPort QCount 0 Quad-A (In) 8 28 IOPort QCount 0 Quad-B (In) 9 29 IOPort QCount 0 Quad-IDX (In) 10 30 IOPort SSerial 0 RXData0 (In) 11 31 IOPort SSerial 0 TXData0 (Out) 12 32 IOPort SSerial 0 TXEn0 (Out) 13 33 IOPort SSR 0 AC Ref (Out) IO Connections for P1 Pin# I/O Pri. func Sec. func Chan Pin func Pin Dir 1 34 IOPort SSerial 0 RXData1 (In) 14 35 IOPort SSerial 0 RXData2 (In) 2 36 IOPort None 15 37 IOPort None 3 38 IOPort SSerial 0 TXData1 (Out) 16 39 IOPort SSerial 0 TXData2 (Out) 4 40 IOPort None 17 41 IOPort None 5 42 IOPort SSerial 1 RXData0 (In) 6 43 IOPort SSerial 1 RXData1 (In) 7 44 IOPort None 8 45 IOPort None 9 46 IOPort SSerial 1 TXData0 (Out) 10 47 IOPort SSerial 1 TXData1 (Out) 11 48 IOPort None 12 49 IOPort None 13 50 IOPort None

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