Flash a XC6SLX9 dev board as a 7i90HD

NET "CLK" TNM_NET = "CLK"; TIMESPEC "TS_CLK" = PERIOD "CLK" 19.9 ns HIGH 50 %; NET "COM_SPICLK" TNM_NET = "COM_SPICLK"; TIMESPEC "TS_COM_SPICLK" = PERIOD "COM_SPICLK" 9 ns HIGH 50 %; OFFSET = OUT 12 ns AFTER "COM_SPICLK" ; OFFSET = IN 8 ns BEFORE "COM_SPICLK" ; NET "COM_SPICLK" LOC ="P50" | IOSTANDARD = LVTTL; NET "COM_SPIIN" LOC ="P56" | IOSTANDARD = LVTTL; NET "COM_SPIOUT" LOC ="P57" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = FAST ; NET "COM_SPICS" LOC ="P58" | IOSTANDARD = LVTTL; NET "TEST0" LOC ="P59" | IOSTANDARD = LVTTL; NET "RECONFIG" LOC ="P67" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; NET "SPICS" LOC ="P38" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; NET "SPIIN" LOC ="P65" | IOSTANDARD = LVTTL; NET "SPIOUT" LOC ="P64" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; NET "SPICLK" LOC ="P70" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; NET "NINIT" LOC ="P39" | IOSTANDARD = LVTTL | DRIVE = 12 | SLEW = SLOW ; NET "CLK" LOC ="P55" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; NET "LEDS<1>" LOC ="P87" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ; NET "LEDS<0>" LOC ="P88" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ; NET "IOBITS<0>" LOC ="P14" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; NET "IOBITS<1>" LOC ="P15" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; NET "IOBITS<2>" LOC ="P16" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; NET "IOBITS<3>" LOC ="P17" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; NET "IOBITS<4>" LOC ="P21" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; NET "IOBITS<5>" LOC ="P22" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; NET "IOBITS<6>" LOC ="P23" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; NET "IOBITS<7>" LOC ="P24" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; NET "IOBITS<8>" LOC ="P26" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; NET "IOBITS<9>" LOC ="P27" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; NET "IOBITS<10>" LOC ="P29" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; NET "IOBITS<11>" LOC ="P30" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; NET "IOBITS<12>" LOC ="P32" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; NET "IOBITS<13>" LOC ="P33" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; NET "IOBITS<14>" LOC ="P34" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; NET "IOBITS<15>" LOC ="P35" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; NET "IOBITS<16>" LOC ="P40" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; NET "IOBITS<17>" LOC ="P41" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; NET "IOBITS<18>" LOC ="P43" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; NET "IOBITS<19>" LOC ="P44" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; NET "IOBITS<20>" LOC ="P45" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; NET "IOBITS<21>" LOC ="P46" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; NET "IOBITS<22>" LOC ="P48" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; NET "IOBITS<23>" LOC ="P51" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; NET "IOBITS<24>" LOC ="P12" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; NET "IOBITS<25>" LOC ="P11" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; NET "IOBITS<26>" LOC ="P10" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; NET "IOBITS<27>" LOC ="P9" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; NET "IOBITS<28>" LOC ="P8" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; NET "IOBITS<29>" LOC ="P7" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; NET "IOBITS<30>" LOC ="P6" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; NET "IOBITS<31>" LOC ="P5" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; NET "IOBITS<32>" LOC ="P2" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; NET "IOBITS<33>" LOC ="P1" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; NET "IOBITS<34>" LOC ="P141" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; NET "IOBITS<35>" LOC ="P142" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; NET "IOBITS<36>" LOC ="P139" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; NET "IOBITS<37>" LOC ="P140" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; NET "IOBITS<38>" LOC ="P137" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; NET "IOBITS<39>" LOC ="P138" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; NET "IOBITS<40>" LOC ="P133" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; NET "IOBITS<41>" LOC ="P134" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; NET "IOBITS<42>" LOC ="P131" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; NET "IOBITS<43>" LOC ="P132" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; NET "IOBITS<44>" LOC ="P126" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; NET "IOBITS<45>" LOC ="P127" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; NET "IOBITS<46>" LOC ="P121" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; NET "IOBITS<47>" LOC ="P124" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; NET "IOBITS<48>" LOC ="P119" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; NET "IOBITS<49>" LOC ="P120" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; NET "IOBITS<50>" LOC ="P117" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; NET "IOBITS<51>" LOC ="P118" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; NET "IOBITS<52>" LOC ="P115" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; NET "IOBITS<53>" LOC ="P116" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; NET "IOBITS<54>" LOC ="P112" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; NET "IOBITS<55>" LOC ="P114" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; NET "IOBITS<56>" LOC ="P105" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; NET "IOBITS<57>" LOC ="P111" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; NET "IOBITS<58>" LOC ="P101" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; NET "IOBITS<59>" LOC ="P102" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; NET "IOBITS<60>" LOC ="P99" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; NET "IOBITS<61>" LOC ="P100" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; NET "IOBITS<62>" LOC ="P97" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; NET "IOBITS<63>" LOC ="P98" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; NET "IOBITS<64>" LOC ="P94" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; NET "IOBITS<65>" LOC ="P95" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; NET "IOBITS<66>" LOC ="P92" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; NET "IOBITS<67>" LOC ="P93" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; NET "IOBITS<68>" LOC ="P74" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; NET "IOBITS<69>" LOC ="P78" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; NET "IOBITS<70>" LOC ="P79" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; NET "IOBITS<71>" LOC ="P80" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; #NET "DONE" LOC ="P71" ; #NET "RDWR" LOC ="P47" ; #NET "PROGRAM" LOC ="P37" ; #NET "M0" LOC ="P69" ; #NET "M1" LOC ="P60" ; #NET "FPGATMS" LOC ="P107" ; #NET "FPGATDI" LOC ="P110" ; #NET "FPGATDO" LOC ="P106" ; #NET "FPGACLK" LOC ="P109" ; #NET "HSWAPEN" LOC ="P144" ; #NET "MISCCLK" LOC ="P143" ; #NET "HOST5" LOC ="P59" ;

IOPortTag & x"00" & StepGenTag & StepGenStepPin, -- I/O 00 TX0 IOPortTag & x"00" & StepGenTag & StepGenDirPin, -- I/O 01 TX1 IOPortTag & x"01" & StepGenTag & StepGenStepPin, -- I/O 02 TX2 IOPortTag & x"01" & StepGenTag & StepGenDirPin, -- I/O 03 TX3 IOPortTag & x"02" & StepGenTag & StepGenStepPin, -- I/O 04 TX4 IOPortTag & x"02" & StepGenTag & StepGenDirPin, -- I/O 05 TX5 IOPortTag & x"03" & StepGenTag & StepGenStepPin, -- I/O 06 TX6 IOPortTag & x"03" & StepGenTag & StepGenDirPin, -- I/O 07 TX7 IOPortTag & x"04" & StepGenTag & StepGenStepPin, -- I/O 08 TX8 IOPortTag & x"04" & StepGenTag & StepGenDirPin, -- I/O 09 TX9 IOPortTag & x"05" & StepGenTag & StepGenStepPin, -- I/O 10 TX10 IOPortTag & x"05" & StepGenTag & StepGenDirPin, -- I/O 11 TX11 IOPortTag & x"06" & StepGenTag & StepGenStepPin, -- I/O 12 TX12 IOPortTag & x"06" & StepGenTag & StepGenDirPin, -- I/O 13 TX13 IOPortTag & x"07" & StepGenTag & StepGenStepPin, -- I/O 14 TX14 IOPortTag & x"07" & StepGenTag & StepGenDirPin, -- I/O 15 TX15 IOPortTag & x"08" & StepGenTag & StepGenStepPin, -- I/O 16 TX16 IOPortTag & x"08" & StepGenTag & StepGenDirPin, -- I/O 17 TX17 IOPortTag & x"09" & StepGenTag & StepGenStepPin, -- I/O 18 TX18 IOPortTag & x"09" & StepGenTag & StepGenDirPin, -- I/O 19 TX19 IOPortTag & x"10" & StepGenTag & StepGenStepPin, -- I/O 20 TX20 IOPortTag & x"10" & StepGenTag & StepGenDirPin, -- I/O 21 TX21 IOPortTag & x"11" & StepGenTag & StepGenStepPin, -- I/O 22 TX22 IOPortTag & x"11" & StepGenTag & StepGenDirPin, -- I/O 23 TX23

Started : "Synthesize - XST". Running xst... Command Line: xst -intstyle ise -ifn "C:/Users/Younes/Desktop/hostmot2/TopGCSPIHostMot2.xst" -ofn "C:/Users/Younes/Desktop/hostmot2/TopGCSPIHostMot2.syr" Reading design: TopGCSPIHostMot2.prj INFO:Xst - Part-select index evaluated to out of bound value may lead to incorrect synthesis results; it is recommended not to use them in RTL ========================================================================= * HDL Parsing * ========================================================================= Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\IDROMConst.vhd" into library work Parsing package <IDROMConst>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\PIN_SVST2_4_7I47_72.vhd" into library work Parsing package <PIN_SVST2_4_7I47_72>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\i90_x9card.vhd" into library work Parsing package <i90_x9card>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\log2.vhd" into library work Parsing package <log2>. Parsing package body <log2>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\dpram.vhd" into library work Parsing entity <dpram>. Parsing architecture <syn> of entity <dpram>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\adpram.vhd" into library work Parsing entity <adpram>. Parsing architecture <syn> of entity <adpram>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\waveram.vhd" into library work Parsing entity <waveram>. Parsing architecture <syn> of entity <waveram>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\uartx8.vhd" into library work Parsing entity <uartx8>. Parsing architecture <Behavioral> of entity <uartx8>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\uartr8.vhd" into library work Parsing entity <uartr8>. Parsing architecture <Behavioral> of entity <uartr8>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\twidrom.vhd" into library work Parsing entity <twidrom>. Parsing architecture <syn> of entity <twidrom>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\syncwavegen.vhd" into library work Parsing entity <syncwavegen>. Parsing architecture <behavioral> of entity <syncwavegen>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\sslbprom43.vhd" into library work Parsing entity <sslbp>. Parsing architecture <syn> of entity <sslbp>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\sslbpram.vhd" into library work Parsing entity <sslbpram>. Parsing architecture <syn> of entity <sslbpram>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\sine16.vhd" into library work Parsing entity <sine16>. Parsing architecture <syn> of entity <sine16>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\resrom.vhd" into library work Parsing entity <resrom>. Parsing architecture <syn> of entity <resrom>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\resolverdaq2.vhd" into library work Parsing entity <resolverdaq2>. Parsing architecture <behavioral> of entity <resolverdaq2>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\OutputInteg.vhd" into library work Parsing entity <OutputInteg>. Parsing architecture <Behavioral> of entity <outputinteg>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\oneofndecode.vhd" into library work Parsing package <oneofndecode>. Parsing package body <oneofndecode>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\decodedstrobe.vhd" into library work Parsing package <decodedstrobe>. Parsing package body <decodedstrobe>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\d8o8sqws.vhd" into library work Parsing entity <DumbAss8sqws>. Parsing architecture <Behavioral> of entity <dumbass8sqws>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\b32qcondmac2ws.vhd" into library work Parsing entity <Big32v2>. Parsing architecture <Behavioral> of entity <big32v2>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\xfrmrout.vhd" into library work Parsing entity <xfrmrout>. Parsing architecture <Behavioral> of entity <xfrmrout>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\wordrb.vhd" into library work Parsing entity <wordrb>. Parsing architecture <behavioral> of entity <wordrb>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\wordpr.vhd" into library work Parsing entity <wordpr>. Parsing architecture <behavioral> of entity <wordpr>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\wavegen.vhd" into library work Parsing entity <wavegen>. Parsing architecture <behavioral> of entity <wavegen>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\watchdog.vhd" into library work Parsing entity <watchdog>. Parsing architecture <Behavioral> of entity <watchdog>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\ubrategend.vhd" into library work Parsing entity <rategend>. Parsing architecture <Behavioral> of entity <rategend>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\ubrategen.vhd" into library work Parsing entity <rategen>. Parsing architecture <Behavioral> of entity <rategen>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\uartx.vhd" into library work Parsing entity <uartx>. Parsing architecture <Behavioral> of entity <uartx>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\uartr.vhd" into library work Parsing entity <uartr>. Parsing architecture <Behavioral> of entity <uartr>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\twiddle.vhd" into library work Parsing entity <twiddle>. Parsing architecture <Behavioral> of entity <twiddle>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\timestampd.vhd" into library work Parsing entity <timestampd>. Parsing architecture <Behavioral> of entity <timestampd>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\timestamp.vhd" into library work Parsing entity <timestamp>. Parsing architecture <Behavioral> of entity <timestamp>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\threephasepwm.vhd" into library work Parsing entity <threephasepwm>. Parsing architecture <behavioral> of entity <threephasepwm>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\sserialwa.vhd" into library work Parsing entity <sserialwa>. Parsing architecture <Behavioral> of entity <sserialwa>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\srl16delay.vhd" into library work Parsing entity <srl16delay>. Parsing architecture <Behavioral> of entity <srl16delay>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\simplessi.vhd" into library work Parsing entity <SimpleSSI>. Parsing architecture <Behavioral> of entity <simplessi>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\simplespix.vhd" into library work Parsing entity <simplespi>. Parsing architecture <behavioral> of entity <simplespi>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\simpledsad.vhd" into library work Parsing entity <simpledsad>. Parsing architecture <behavioral> of entity <simpledsad>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\scalertimer.vhd" into library work Parsing entity <scalertimer>. Parsing architecture <Behavioral> of entity <scalertimer>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\scalercounter.vhd" into library work Parsing entity <scalercounter>. Parsing architecture <Behavioral> of entity <scalercounter>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\resolver.vhd" into library work Parsing entity <resolver>. Parsing architecture <dataflow> of entity <resolver>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\qcountersfpd.vhd" into library work Parsing entity <qcounterpd>. Parsing architecture <behavioral> of entity <qcounterpd>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\qcountersfp.vhd" into library work Parsing entity <qcounterp>. Parsing architecture <behavioral> of entity <qcounterp>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\qcountersfd.vhd" into library work Parsing entity <qcounterd>. Parsing architecture <behavioral> of entity <qcounterd>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\qcountersf.vhd" into library work Parsing entity <qcounter>. Parsing architecture <behavioral> of entity <qcounter>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\qcounterateskd.vhd" into library work Parsing entity <qcounterateskd>. Parsing architecture <Behavioral> of entity <qcounterateskd>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\qcounteratesk.vhd" into library work Parsing entity <qcounteratesk>. Parsing architecture <Behavioral> of entity <qcounteratesk>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\qcounterated.vhd" into library work Parsing entity <qcounterated>. Parsing architecture <Behavioral> of entity <qcounterated>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\qcounterate.vhd" into library work Parsing entity <qcounterate>. Parsing architecture <Behavioral> of entity <qcounterate>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\pwmrefh.vhd" into library work Parsing entity <pwmrefh>. Parsing architecture <behavioral> of entity <pwmrefh>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\pwmpdmgenh.vhd" into library work Parsing entity <pwmpdmgenh>. Parsing architecture <behavioral> of entity <pwmpdmgenh>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\pktuartx.vhd" into library work Parsing entity <pktuartx>. Parsing architecture <Behavioral> of entity <pktuartx>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\pktuartr.vhd" into library work Parsing entity <pktuartr>. Parsing architecture <Behavioral> of entity <pktuartr>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\PinExists.vhd" into library work Parsing package <PinExists>. Parsing package body <PinExists>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\OutputPinsPerModule.vhd" into library work Parsing package <OutputPinsPerModule>. Parsing package body <OutputPinsPerModule>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\NumberOfModules.vhd" into library work Parsing package <NumberOfModules>. Parsing package body <NumberOfModules>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\ModuleExists.vhd" into library work Parsing package <ModuleExists>. Parsing package body <ModuleExists>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\MaxPinsPerModule.vhd" into library work Parsing package <MaxPinsPerModule>. Parsing package body <MaxPinsPerModule>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\MaxOutputPinsPerModule.vhd" into library work Parsing package <MaxOutputPinsPerModule>. Parsing package body <MaxOutputPinsPerModule>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\MaxIOPinsPerModule.vhd" into library work Parsing package <MaxIOPinsPerModule>. Parsing package body <MaxIOPinsPerModule>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\MaxInputPinsPerModule.vhd" into library work Parsing package <MaxInputPinsPerModule>. Parsing package body <MaxInputPinsPerModule>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\kubstepgenzid.vhd" into library work Parsing entity <stepgenid>. Parsing architecture <Behavioral> of entity <stepgenid>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\kubstepgenzi.vhd" into library work Parsing entity <stepgeni>. Parsing architecture <Behavioral> of entity <stepgeni>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\kubstepgenzd.vhd" into library work Parsing entity <stepgend>. Parsing architecture <Behavioral> of entity <stepgend>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\kubstepgenz.vhd" into library work Parsing entity <stepgen>. Parsing architecture <Behavioral> of entity <stepgen>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\irqlogics.vhd" into library work Parsing entity <irqlogics>. Parsing architecture <Behavioral> of entity <irqlogics>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\InputPinsPerModule.vhd" into library work Parsing package <InputPinsPerModule>. Parsing package body <InputPinsPerModule>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\inmuxm.vhd" into library work Parsing entity <inmuxm>. Parsing architecture <behavioral> of entity <inmuxm>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\inm.vhd" into library work Parsing entity <inm>. Parsing architecture <behavioral> of entity <inm>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\idrom.vhd" into library work Parsing entity <IDROM>. Parsing architecture <syn> of entity <idrom>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\hostmotid.vhd" into library work Parsing entity <hostmotid>. Parsing architecture <Behavioral> of entity <hostmotid>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\hmtimers.vhd" into library work Parsing entity <hm2dpll>. Parsing architecture <behavioral> of entity <hm2dpll>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\GetModuleHint.vhd" into library work Parsing package <GetModuleHint>. Parsing package body <GetModuleHint>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\fanucabs.vhd" into library work Parsing entity <FanucAbs>. Parsing architecture <Behavioral> of entity <fanucabs>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\drqlogic.vhd" into library work Parsing entity <dmdrqlogic>. Parsing architecture <Behavioral> of entity <dmdrqlogic>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\dpainter.vhd" into library work Parsing entity <dpainterd>. Parsing architecture <Behavioral> of entity <dpainterd>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\daqfifo16.vhd" into library work Parsing entity <DAQFIFO16>. Parsing architecture <Behavioral> of entity <daqfifo16>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\cpdrive.vhd" into library work Parsing entity <cpdrive>. Parsing architecture <Behavioral> of entity <cpdrive>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\CountPinsInRange.vhd" into library work Parsing package <CountPinsInRange>. Parsing package body <CountPinsInRange>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\bufferedspi.vhd" into library work Parsing entity <bufferedspi>. Parsing architecture <behavioral> of entity <bufferedspi>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\boutreg.vhd" into library work Parsing entity <boutreg>. Parsing architecture <Behavioral> of entity <boutreg>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\biss.vhd" into library work Parsing entity <biss>. Parsing architecture <Behavioral> of entity <biss>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\binosc.vhd" into library work Parsing entity <binosc>. Parsing architecture <Behavioral> of entity <binosc>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\simplespi8x.vhd" into library work Parsing entity <simplespi8>. Parsing architecture <behavioral> of entity <simplespi8>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\hostmot2.vhd" into library work Parsing entity <HostMot2>. Parsing architecture <dataflow> of entity <hostmot2>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\fixicap.vhd" into library work Parsing package <FixICap>. Parsing package body <fixicap>. Parsing VHDL file "C:\Users\Younes\Desktop\hostmot2\TopGCSPIHostMot2.vhd" into library work Parsing entity <TopGCSPIHostMot2>. ERROR:HDLCompiler:69 - "C:\Users\Younes\Desktop\hostmot2\TopGCSPIHostMot2.vhd" Line 166: <ledcount> is not declared. ERROR:HDLCompiler:69 - "C:\Users\Younes\Desktop\hostmot2\TopGCSPIHostMot2.vhd" Line 167: <iowidth> is not declared. ERROR:HDLCompiler:854 - "C:\Users\Younes\Desktop\hostmot2\TopGCSPIHostMot2.vhd" Line 144: Unit <topgcspihostmot2> ignored due to previous errors. Parsing architecture <Behavioral> of entity <topgcspihostmot2>. ERROR:HDLCompiler:374 - "C:\Users\Younes\Desktop\hostmot2\TopGCSPIHostMot2.vhd" Line 182: Entity <topgcspihostmot2> is not yet compiled. ERROR:HDLCompiler:69 - "C:\Users\Younes\Desktop\hostmot2\TopGCSPIHostMot2.vhd" Line 184: <std_logic_vector> is not declared. ERROR:HDLCompiler:69 - "C:\Users\Younes\Desktop\hostmot2\TopGCSPIHostMot2.vhd" Line 185: <std_logic_vector> is not declared. ERROR:HDLCompiler:69 - "C:\Users\Younes\Desktop\hostmot2\TopGCSPIHostMot2.vhd" Line 187: <real> is not declared. ERROR:HDLCompiler:69 - "C:\Users\Younes\Desktop\hostmot2\TopGCSPIHostMot2.vhd" Line 188: <std_logic_vector> is not declared. ERROR:HDLCompiler:69 - "C:\Users\Younes\Desktop\hostmot2\TopGCSPIHostMot2.vhd" Line 189: <std_logic_vector> is not declared. ERROR:HDLCompiler:69 - "C:\Users\Younes\Desktop\hostmot2\TopGCSPIHostMot2.vhd" Line 190: <std_logic_vector> is not declared. ERROR:HDLCompiler:69 - "C:\Users\Younes\Desktop\hostmot2\TopGCSPIHostMot2.vhd" Line 191: <std_logic> is not declared. ERROR:HDLCompiler:69 - "C:\Users\Younes\Desktop\hostmot2\TopGCSPIHostMot2.vhd" Line 192: <std_logic> is not declared. ERROR:HDLCompiler:69 - "C:\Users\Younes\Desktop\hostmot2\TopGCSPIHostMot2.vhd" Line 193: <std_logic> is not declared. ERROR:HDLCompiler:69 - "C:\Users\Younes\Desktop\hostmot2\TopGCSPIHostMot2.vhd" Line 194: <std_logic> is not declared. ERROR:HDLCompiler:69 - "C:\Users\Younes\Desktop\hostmot2\TopGCSPIHostMot2.vhd" Line 196: <std_logic> is not declared. ERROR:HDLCompiler:69 - "C:\Users\Younes\Desktop\hostmot2\TopGCSPIHostMot2.vhd" Line 197: <std_logic> is not declared. ERROR:HDLCompiler:69 - "C:\Users\Younes\Desktop\hostmot2\TopGCSPIHostMot2.vhd" Line 198: <std_logic> is not declared. ERROR:HDLCompiler:69 - "C:\Users\Younes\Desktop\hostmot2\TopGCSPIHostMot2.vhd" Line 199: <std_logic> is not declared. ERROR:HDLCompiler:69 - "C:\Users\Younes\Desktop\hostmot2\TopGCSPIHostMot2.vhd" Line 201: <std_logic> is not declared. Sorry, too many errors.. --> Total memory usage is 4501408 kilobytes Number of errors : 19 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 1 ( 0 filtered) Process "Synthesize - XST" failed