7i80DB-16 and Xilinx ISE, error on synthesize

vladimirzvu
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6 years 11 months ago #150241 by vladimirzvu

7i80DB-16 and Xilinx ISE, error on synthesize was created by vladimirzvu

Dear all,

I'm not sure if this is the right place, but I downloaded the support zip archive for the 7i80DB-16. I'm now trying to build bitfiles for the card and have downloaded the Xilinx ISE 14.5. When trying to build the PIN_JUSTIO.vhd configuration i get the following error:

Warning: Spoiler!

WARNING:HDLCompiler:1369 - "C:\Users\A1\Downloads\7i80\7i80\configs\hostmot2\source\hostmot2.vhd" Line 2423: Possible infinite loop; process does not have a wait statement
WARNING:HDLCompiler:1369 - "C:\Users\A1\Downloads\7i80\7i80\configs\hostmot2\source\hostmot2.vhd" Line 2450: Possible infinite loop; process does not have a wait statement
ERROR:HDLCompiler:1728 - "C:\Users\A1\Downloads\7i80\7i80\configs\hostmot2\source\hostmot2.vhd" Line 3541: Type error near shiftdiv ; current type unsigned; expected type std_logic_vector
ERROR:HDLCompiler:432 - "C:\Users\A1\Downloads\7i80\7i80\configs\hostmot2\source\hostmot2.vhd" Line 3539: Formal <asize> has no actual or default value.
INFO:HDLCompiler:1408 - "C:\Users\A1\Downloads\7i80\7i80\configs\hostmot2\source\xy2mod.vhd" Line 78. asize is declared here
INFO:HDLCompiler:1408 - "C:\Users\A1\Downloads\7i80\7i80\configs\hostmot2\source\xy2mod.vhd" Line 79. rsize is declared here
ERROR:HDLCompiler:1314 - "C:\Users\A1\Downloads\7i80\7i80\configs\hostmot2\source\hostmot2.vhd" Line 3551: Formal port/generic <loadvelx> is not declared in <xy2mod>
INFO:HDLCompiler:1408 - "C:\Users\A1\Downloads\7i80\7i80\configs\hostmot2\source\xy2mod.vhd" Line 88. loadvelox is declared here
INFO:HDLCompiler:1408 - "C:\Users\A1\Downloads\7i80\7i80\configs\hostmot2\source\xy2mod.vhd" Line 89. loadveloy is declared here
INFO:HDLCompiler:1408 - "C:\Users\A1\Downloads\7i80\7i80\configs\hostmot2\source\xy2mod.vhd" Line 90. loadposx is declared here
INFO:HDLCompiler:1408 - "C:\Users\A1\Downloads\7i80\7i80\configs\hostmot2\source\xy2mod.vhd" Line 91. loadposy is declared here
INFO:HDLCompiler:1408 - "C:\Users\A1\Downloads\7i80\7i80\configs\hostmot2\source\xy2mod.vhd" Line 92. loadmode is declared here
INFO:HDLCompiler:1408 - "C:\Users\A1\Downloads\7i80\7i80\configs\hostmot2\source\xy2mod.vhd" Line 93. loadtimersel is declared here
INFO:HDLCompiler:1408 - "C:\Users\A1\Downloads\7i80\7i80\configs\hostmot2\source\xy2mod.vhd" Line 94. readaccelx is declared here
INFO:HDLCompiler:1408 - "C:\Users\A1\Downloads\7i80\7i80\configs\hostmot2\source\xy2mod.vhd" Line 95. readaccely is declared here
INFO:HDLCompiler:1408 - "C:\Users\A1\Downloads\7i80\7i80\configs\hostmot2\source\xy2mod.vhd" Line 96. readvelox is declared here
INFO:HDLCompiler:1408 - "C:\Users\A1\Downloads\7i80\7i80\configs\hostmot2\source\xy2mod.vhd" Line 97. readveloy is declared here
INFO:HDLCompiler:1408 - "C:\Users\A1\Downloads\7i80\7i80\configs\hostmot2\source\xy2mod.vhd" Line 98. readposx is declared here
INFO:HDLCompiler:1408 - "C:\Users\A1\Downloads\7i80\7i80\configs\hostmot2\source\xy2mod.vhd" Line 99. readposy is declared here
INFO:HDLCompiler:1408 - "C:\Users\A1\Downloads\7i80\7i80\configs\hostmot2\source\xy2mod.vhd" Line 100. readmode is declared here
INFO:HDLCompiler:1408 - "C:\Users\A1\Downloads\7i80\7i80\configs\hostmot2\source\xy2mod.vhd" Line 101. readtimersel is declared here
INFO:HDLCompiler:1408 - "C:\Users\A1\Downloads\7i80\7i80\configs\hostmot2\source\xy2mod.vhd" Line 102. timers is declared here
INFO:HDLCompiler:1408 - "C:\Users\A1\Downloads\7i80\7i80\configs\hostmot2\source\xy2mod.vhd" Line 107. status is declared here
ERROR:HDLCompiler:1728 - "C:\Users\A1\Downloads\7i80\7i80\configs\hostmot2\source\hostmot2.vhd" Line 3579: Type error near shiftdiv ; current type unsigned; expected type std_logic_vector
ERROR:HDLCompiler:432 - "C:\Users\A1\Downloads\7i80\7i80\configs\hostmot2\source\hostmot2.vhd" Line 3577: Formal <asize> has no actual or default value.
INFO:HDLCompiler:1408 - "C:\Users\A1\Downloads\7i80\7i80\configs\hostmot2\source\xy2mod.vhd" Line 78. asize is declared here
INFO:HDLCompiler:1408 - "C:\Users\A1\Downloads\7i80\7i80\configs\hostmot2\source\xy2mod.vhd" Line 79. rsize is declared here
ERROR:HDLCompiler:1314 - "C:\Users\A1\Downloads\7i80\7i80\configs\hostmot2\source\hostmot2.vhd" Line 3589: Formal port/generic <loadvelx> is not declared in <xy2mod>
INFO:HDLCompiler:1408 - "C:\Users\A1\Downloads\7i80\7i80\configs\hostmot2\source\xy2mod.vhd" Line 88. loadvelox is declared here
INFO:HDLCompiler:1408 - "C:\Users\A1\Downloads\7i80\7i80\configs\hostmot2\source\xy2mod.vhd" Line 89. loadveloy is declared here
INFO:HDLCompiler:1408 - "C:\Users\A1\Downloads\7i80\7i80\configs\hostmot2\source\xy2mod.vhd" Line 90. loadposx is declared here
INFO:HDLCompiler:1408 - "C:\Users\A1\Downloads\7i80\7i80\configs\hostmot2\source\xy2mod.vhd" Line 91. loadposy is declared here
INFO:HDLCompiler:1408 - "C:\Users\A1\Downloads\7i80\7i80\configs\hostmot2\source\xy2mod.vhd" Line 92. loadmode is declared here
INFO:HDLCompiler:1408 - "C:\Users\A1\Downloads\7i80\7i80\configs\hostmot2\source\xy2mod.vhd" Line 93. loadtimersel is declared here
INFO:HDLCompiler:1408 - "C:\Users\A1\Downloads\7i80\7i80\configs\hostmot2\source\xy2mod.vhd" Line 94. readaccelx is declared here
INFO:HDLCompiler:1408 - "C:\Users\A1\Downloads\7i80\7i80\configs\hostmot2\source\xy2mod.vhd" Line 95. readaccely is declared here
INFO:HDLCompiler:1408 - "C:\Users\A1\Downloads\7i80\7i80\configs\hostmot2\source\xy2mod.vhd" Line 96. readvelox is declared here
INFO:HDLCompiler:1408 - "C:\Users\A1\Downloads\7i80\7i80\configs\hostmot2\source\xy2mod.vhd" Line 97. readveloy is declared here
INFO:HDLCompiler:1408 - "C:\Users\A1\Downloads\7i80\7i80\configs\hostmot2\source\xy2mod.vhd" Line 98. readposx is declared here
INFO:HDLCompiler:1408 - "C:\Users\A1\Downloads\7i80\7i80\configs\hostmot2\source\xy2mod.vhd" Line 99. readposy is declared here
INFO:HDLCompiler:1408 - "C:\Users\A1\Downloads\7i80\7i80\configs\hostmot2\source\xy2mod.vhd" Line 100. readmode is declared here
INFO:HDLCompiler:1408 - "C:\Users\A1\Downloads\7i80\7i80\configs\hostmot2\source\xy2mod.vhd" Line 101. readtimersel is declared here
INFO:HDLCompiler:1408 - "C:\Users\A1\Downloads\7i80\7i80\configs\hostmot2\source\xy2mod.vhd" Line 102. timers is declared here
INFO:HDLCompiler:1408 - "C:\Users\A1\Downloads\7i80\7i80\configs\hostmot2\source\xy2mod.vhd" Line 107. status is declared here
ERROR:HDLCompiler:854 - "C:\Users\A1\Downloads\7i80\7i80\configs\hostmot2\source\hostmot2.vhd" Line 146: Unit <dataflow> ignored due to previous errors.
VHDL file C:\Users\A1\Downloads\7i80\7i80\configs\hostmot2\source\hostmot2.vhd ignored due to errors
-->

Total memory usage is 235932 kilobytes

Number of errors : 7 ( 0 filtered)
Number of warnings : 2 ( 0 filtered)
Number of infos : 0 ( 0 filtered)

Process "Synthesize - XST" failed

What needs to be fixed?

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PCW
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Platinum Member

6 years 11 months ago #150243 by PCW

Replied by PCW on topic 7i80DB-16 and Xilinx ISE, error on synthesize

One source file is out of sync
You can download the zip file again (it was updated last Friday)
or use this updated source file:

Attachment not found

(rename to xy2mod.vhd)

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