halcmd show doesn't match Mesa readhmid (missing encoders & step generator)

halcmd show all | grep 7i76 26 s32 OUT 2098000000 hm2_7i76e.0.0.debug 26 bit OUT FALSE hm2_7i76e.0.7i76.0.0.input-00 26 bit OUT TRUE hm2_7i76e.0.7i76.0.0.input-00-not 26 bit OUT FALSE hm2_7i76e.0.7i76.0.0.input-01 26 bit OUT TRUE hm2_7i76e.0.7i76.0.0.input-01-not 26 bit OUT FALSE hm2_7i76e.0.7i76.0.0.input-02 26 bit OUT TRUE hm2_7i76e.0.7i76.0.0.input-02-not 26 bit OUT FALSE hm2_7i76e.0.7i76.0.0.input-03 26 bit OUT TRUE hm2_7i76e.0.7i76.0.0.input-03-not 26 bit OUT FALSE hm2_7i76e.0.7i76.0.0.input-04 26 bit OUT TRUE hm2_7i76e.0.7i76.0.0.input-04-not 26 bit OUT FALSE hm2_7i76e.0.7i76.0.0.input-05 26 bit OUT TRUE hm2_7i76e.0.7i76.0.0.input-05-not 26 bit OUT FALSE hm2_7i76e.0.7i76.0.0.input-06 26 bit OUT TRUE hm2_7i76e.0.7i76.0.0.input-06-not 26 bit OUT FALSE hm2_7i76e.0.7i76.0.0.input-07 26 bit OUT TRUE hm2_7i76e.0.7i76.0.0.input-07-not 26 bit OUT FALSE hm2_7i76e.0.7i76.0.0.input-08 26 bit OUT TRUE hm2_7i76e.0.7i76.0.0.input-08-not 26 bit OUT FALSE hm2_7i76e.0.7i76.0.0.input-09 26 bit OUT TRUE hm2_7i76e.0.7i76.0.0.input-09-not 26 bit OUT FALSE hm2_7i76e.0.7i76.0.0.input-10 26 bit OUT TRUE hm2_7i76e.0.7i76.0.0.input-10-not 26 bit OUT FALSE hm2_7i76e.0.7i76.0.0.input-11 26 bit OUT TRUE hm2_7i76e.0.7i76.0.0.input-11-not 26 bit OUT FALSE hm2_7i76e.0.7i76.0.0.input-12 26 bit OUT TRUE hm2_7i76e.0.7i76.0.0.input-12-not 26 bit OUT FALSE hm2_7i76e.0.7i76.0.0.input-13 26 bit OUT TRUE hm2_7i76e.0.7i76.0.0.input-13-not 26 bit OUT FALSE hm2_7i76e.0.7i76.0.0.input-14 26 bit OUT TRUE hm2_7i76e.0.7i76.0.0.input-14-not 26 bit OUT FALSE hm2_7i76e.0.7i76.0.0.input-15 26 bit OUT TRUE hm2_7i76e.0.7i76.0.0.input-15-not 26 bit OUT FALSE hm2_7i76e.0.7i76.0.0.input-16 26 bit OUT TRUE hm2_7i76e.0.7i76.0.0.input-16-not 26 bit OUT FALSE hm2_7i76e.0.7i76.0.0.input-17 26 bit OUT TRUE hm2_7i76e.0.7i76.0.0.input-17-not 26 bit OUT FALSE hm2_7i76e.0.7i76.0.0.input-18 26 bit OUT TRUE hm2_7i76e.0.7i76.0.0.input-18-not 26 bit OUT FALSE hm2_7i76e.0.7i76.0.0.input-19 26 bit OUT TRUE hm2_7i76e.0.7i76.0.0.input-19-not 26 bit OUT FALSE hm2_7i76e.0.7i76.0.0.input-20 26 bit OUT TRUE hm2_7i76e.0.7i76.0.0.input-20-not 26 bit OUT FALSE hm2_7i76e.0.7i76.0.0.input-21 26 bit OUT TRUE hm2_7i76e.0.7i76.0.0.input-21-not 26 bit OUT FALSE hm2_7i76e.0.7i76.0.0.input-22 26 bit OUT TRUE hm2_7i76e.0.7i76.0.0.input-22-not 26 bit OUT FALSE hm2_7i76e.0.7i76.0.0.input-23 26 bit OUT TRUE hm2_7i76e.0.7i76.0.0.input-23-not 26 bit OUT FALSE hm2_7i76e.0.7i76.0.0.input-24 26 bit OUT TRUE hm2_7i76e.0.7i76.0.0.input-24-not 26 bit OUT FALSE hm2_7i76e.0.7i76.0.0.input-25 26 bit OUT TRUE hm2_7i76e.0.7i76.0.0.input-25-not 26 bit OUT FALSE hm2_7i76e.0.7i76.0.0.input-26 26 bit OUT TRUE hm2_7i76e.0.7i76.0.0.input-26-not 26 bit OUT FALSE hm2_7i76e.0.7i76.0.0.input-27 26 bit OUT TRUE hm2_7i76e.0.7i76.0.0.input-27-not 26 bit OUT FALSE hm2_7i76e.0.7i76.0.0.input-28 26 bit OUT TRUE hm2_7i76e.0.7i76.0.0.input-28-not 26 bit OUT FALSE hm2_7i76e.0.7i76.0.0.input-29 26 bit OUT TRUE hm2_7i76e.0.7i76.0.0.input-29-not 26 bit OUT FALSE hm2_7i76e.0.7i76.0.0.input-30 26 bit OUT TRUE hm2_7i76e.0.7i76.0.0.input-30-not 26 bit OUT FALSE hm2_7i76e.0.7i76.0.0.input-31 26 bit OUT TRUE hm2_7i76e.0.7i76.0.0.input-31-not 26 bit IN FALSE hm2_7i76e.0.7i76.0.0.output-00 26 bit IN FALSE hm2_7i76e.0.7i76.0.0.output-01 26 bit IN FALSE hm2_7i76e.0.7i76.0.0.output-02 26 bit IN FALSE hm2_7i76e.0.7i76.0.0.output-03 26 bit IN FALSE hm2_7i76e.0.7i76.0.0.output-04 26 bit IN FALSE hm2_7i76e.0.7i76.0.0.output-05 26 bit IN FALSE hm2_7i76e.0.7i76.0.0.output-06 26 bit IN FALSE hm2_7i76e.0.7i76.0.0.output-07 26 bit IN FALSE hm2_7i76e.0.7i76.0.0.output-08 26 bit IN FALSE hm2_7i76e.0.7i76.0.0.output-09 26 bit IN FALSE hm2_7i76e.0.7i76.0.0.output-10 26 bit IN FALSE hm2_7i76e.0.7i76.0.0.output-11 26 bit IN FALSE hm2_7i76e.0.7i76.0.0.output-12 26 bit IN FALSE hm2_7i76e.0.7i76.0.0.output-13 26 bit IN FALSE hm2_7i76e.0.7i76.0.0.output-14 26 bit IN FALSE hm2_7i76e.0.7i76.0.0.output-15 26 bit IN FALSE hm2_7i76e.0.7i76.0.0.spindir 26 bit IN FALSE hm2_7i76e.0.7i76.0.0.spinena 26 float IN 0 hm2_7i76e.0.7i76.0.0.spinout 26 float IN -50 hm2_7i76e.0.dpll.01.timer-us 26 float IN 100 hm2_7i76e.0.dpll.02.timer-us 26 float IN 100 hm2_7i76e.0.dpll.03.timer-us 26 float IN 100 hm2_7i76e.0.dpll.04.timer-us 26 float IN 1 hm2_7i76e.0.dpll.base-freq-khz 26 u32 OUT 0x0000002A hm2_7i76e.0.dpll.ddsize 26 float OUT 31.49437 hm2_7i76e.0.dpll.phase-error-us 26 u32 IN 0x00400000 hm2_7i76e.0.dpll.plimit 26 u32 OUT 0x00000018 hm2_7i76e.0.dpll.prescale 26 u32 IN 0x000007D0 hm2_7i76e.0.dpll.time-const 26 s32 OUT 0 hm2_7i76e.0.encoder.00.count 26 s32 OUT 0 hm2_7i76e.0.encoder.00.count-latched 26 bit I/O FALSE hm2_7i76e.0.encoder.00.index-enable <=> spindle-index-enable 26 bit OUT FALSE hm2_7i76e.0.encoder.00.input-a 26 bit OUT TRUE hm2_7i76e.0.encoder.00.input-b 26 bit OUT TRUE hm2_7i76e.0.encoder.00.input-index 26 bit IN FALSE hm2_7i76e.0.encoder.00.latch-enable 26 bit IN FALSE hm2_7i76e.0.encoder.00.latch-polarity 26 float OUT 0 hm2_7i76e.0.encoder.00.position ==> spindle-revs 26 float OUT 0 hm2_7i76e.0.encoder.00.position-latched 26 bit OUT FALSE hm2_7i76e.0.encoder.00.quad-error 26 bit IN FALSE hm2_7i76e.0.encoder.00.quad-error-enable 26 s32 OUT 1 hm2_7i76e.0.encoder.00.rawcounts 26 s32 OUT 1 hm2_7i76e.0.encoder.00.rawlatch 26 bit IN FALSE hm2_7i76e.0.encoder.00.reset 26 float OUT 0 hm2_7i76e.0.encoder.00.velocity ==> spindle-vel-fb-rps 26 float OUT 0 hm2_7i76e.0.encoder.00.velocity-rpm 26 u32 IN 0x007F2815 hm2_7i76e.0.encoder.muxed-sample-frequency 26 u32 IN 0x00000000 hm2_7i76e.0.encoder.muxed-skew 26 s32 IN -1 hm2_7i76e.0.encoder.timer-number 26 bit OUT FALSE hm2_7i76e.0.gpio.000.in 26 bit OUT TRUE hm2_7i76e.0.gpio.000.in_not 26 bit OUT FALSE hm2_7i76e.0.gpio.001.in 26 bit OUT TRUE hm2_7i76e.0.gpio.001.in_not 26 bit OUT FALSE hm2_7i76e.0.gpio.002.in 26 bit OUT TRUE hm2_7i76e.0.gpio.002.in_not 26 bit OUT FALSE hm2_7i76e.0.gpio.003.in 26 bit OUT TRUE hm2_7i76e.0.gpio.003.in_not 26 bit OUT FALSE hm2_7i76e.0.gpio.004.in 26 bit OUT TRUE hm2_7i76e.0.gpio.004.in_not 26 bit OUT FALSE hm2_7i76e.0.gpio.005.in 26 bit OUT TRUE hm2_7i76e.0.gpio.005.in_not 26 bit OUT FALSE hm2_7i76e.0.gpio.006.in 26 bit OUT TRUE hm2_7i76e.0.gpio.006.in_not 26 bit OUT FALSE hm2_7i76e.0.gpio.007.in 26 bit OUT TRUE hm2_7i76e.0.gpio.007.in_not 26 bit OUT FALSE hm2_7i76e.0.gpio.008.in 26 bit OUT TRUE hm2_7i76e.0.gpio.008.in_not 26 bit OUT FALSE hm2_7i76e.0.gpio.009.in 26 bit OUT TRUE hm2_7i76e.0.gpio.009.in_not 26 bit OUT TRUE hm2_7i76e.0.gpio.010.in 26 bit OUT FALSE hm2_7i76e.0.gpio.010.in_not 26 bit OUT TRUE hm2_7i76e.0.gpio.011.in 26 bit OUT FALSE hm2_7i76e.0.gpio.011.in_not 26 bit OUT TRUE hm2_7i76e.0.gpio.012.in 26 bit OUT FALSE hm2_7i76e.0.gpio.012.in_not 26 bit IN FALSE hm2_7i76e.0.gpio.012.out 26 bit OUT TRUE hm2_7i76e.0.gpio.013.in 26 bit OUT FALSE hm2_7i76e.0.gpio.013.in_not 26 bit IN FALSE hm2_7i76e.0.gpio.013.out 26 bit OUT FALSE hm2_7i76e.0.gpio.014.in 26 bit OUT TRUE hm2_7i76e.0.gpio.014.in_not 26 bit IN FALSE hm2_7i76e.0.gpio.014.out 26 bit OUT FALSE hm2_7i76e.0.gpio.015.in 26 bit OUT TRUE hm2_7i76e.0.gpio.015.in_not 26 bit IN FALSE hm2_7i76e.0.gpio.015.out 26 bit OUT FALSE hm2_7i76e.0.gpio.016.in 26 bit OUT TRUE hm2_7i76e.0.gpio.016.in_not 26 bit IN FALSE hm2_7i76e.0.gpio.016.out 26 bit OUT TRUE hm2_7i76e.0.gpio.017.in 26 bit OUT FALSE hm2_7i76e.0.gpio.017.in_not 26 bit IN FALSE hm2_7i76e.0.gpio.017.out 26 bit OUT TRUE hm2_7i76e.0.gpio.018.in 26 bit OUT FALSE hm2_7i76e.0.gpio.018.in_not 26 bit IN FALSE hm2_7i76e.0.gpio.018.out 26 bit OUT TRUE hm2_7i76e.0.gpio.019.in 26 bit OUT FALSE hm2_7i76e.0.gpio.019.in_not 26 bit IN FALSE hm2_7i76e.0.gpio.019.out 26 bit OUT TRUE hm2_7i76e.0.gpio.020.in 26 bit OUT FALSE hm2_7i76e.0.gpio.020.in_not 26 bit IN FALSE hm2_7i76e.0.gpio.020.out 26 bit OUT TRUE hm2_7i76e.0.gpio.021.in 26 bit OUT FALSE hm2_7i76e.0.gpio.021.in_not 26 bit IN FALSE hm2_7i76e.0.gpio.021.out 26 bit OUT TRUE hm2_7i76e.0.gpio.022.in 26 bit OUT FALSE hm2_7i76e.0.gpio.022.in_not 26 bit IN FALSE hm2_7i76e.0.gpio.022.out 26 bit OUT TRUE hm2_7i76e.0.gpio.023.in 26 bit OUT FALSE hm2_7i76e.0.gpio.023.in_not 26 bit IN FALSE hm2_7i76e.0.gpio.023.out 26 bit OUT TRUE hm2_7i76e.0.gpio.024.in 26 bit OUT FALSE hm2_7i76e.0.gpio.024.in_not 26 bit IN FALSE hm2_7i76e.0.gpio.024.out 26 bit OUT TRUE hm2_7i76e.0.gpio.025.in 26 bit OUT FALSE hm2_7i76e.0.gpio.025.in_not 26 bit IN FALSE hm2_7i76e.0.gpio.025.out 26 bit OUT TRUE hm2_7i76e.0.gpio.026.in 26 bit OUT FALSE hm2_7i76e.0.gpio.026.in_not 26 bit IN FALSE hm2_7i76e.0.gpio.026.out 26 bit OUT TRUE hm2_7i76e.0.gpio.027.in 26 bit OUT FALSE hm2_7i76e.0.gpio.027.in_not 26 bit IN FALSE hm2_7i76e.0.gpio.027.out 26 bit OUT TRUE hm2_7i76e.0.gpio.028.in 26 bit OUT FALSE hm2_7i76e.0.gpio.028.in_not 26 bit IN FALSE hm2_7i76e.0.gpio.028.out 26 bit OUT TRUE hm2_7i76e.0.gpio.029.in 26 bit OUT FALSE hm2_7i76e.0.gpio.029.in_not 26 bit IN FALSE hm2_7i76e.0.gpio.029.out 26 bit OUT TRUE hm2_7i76e.0.gpio.030.in 26 bit OUT FALSE hm2_7i76e.0.gpio.030.in_not 26 bit IN FALSE hm2_7i76e.0.gpio.030.out 26 bit OUT TRUE hm2_7i76e.0.gpio.031.in 26 bit OUT FALSE hm2_7i76e.0.gpio.031.in_not 26 bit IN FALSE hm2_7i76e.0.gpio.031.out 26 bit OUT TRUE hm2_7i76e.0.gpio.032.in 26 bit OUT FALSE hm2_7i76e.0.gpio.032.in_not 26 bit IN FALSE hm2_7i76e.0.gpio.032.out 26 bit OUT TRUE hm2_7i76e.0.gpio.033.in 26 bit OUT FALSE hm2_7i76e.0.gpio.033.in_not 26 bit IN FALSE hm2_7i76e.0.gpio.033.out 26 bit OUT TRUE hm2_7i76e.0.gpio.034.in 26 bit OUT FALSE hm2_7i76e.0.gpio.034.in_not 26 bit OUT FALSE hm2_7i76e.0.gpio.035.in 26 bit OUT TRUE hm2_7i76e.0.gpio.035.in_not 26 bit OUT TRUE hm2_7i76e.0.gpio.036.in 26 bit OUT FALSE hm2_7i76e.0.gpio.036.in_not 26 bit OUT FALSE hm2_7i76e.0.gpio.037.in 26 bit OUT TRUE hm2_7i76e.0.gpio.037.in_not 26 bit IN FALSE hm2_7i76e.0.gpio.037.out 26 bit OUT FALSE hm2_7i76e.0.gpio.038.in 26 bit OUT TRUE hm2_7i76e.0.gpio.038.in_not 26 bit IN FALSE hm2_7i76e.0.gpio.038.out 26 bit OUT TRUE hm2_7i76e.0.gpio.039.in 26 bit OUT FALSE hm2_7i76e.0.gpio.039.in_not 26 bit IN FALSE hm2_7i76e.0.gpio.039.out 26 bit OUT FALSE hm2_7i76e.0.gpio.040.in 26 bit OUT TRUE hm2_7i76e.0.gpio.040.in_not 26 bit IN FALSE hm2_7i76e.0.gpio.040.out 26 bit OUT FALSE hm2_7i76e.0.gpio.041.in 26 bit OUT TRUE hm2_7i76e.0.gpio.041.in_not 26 bit IN FALSE hm2_7i76e.0.gpio.041.out 26 bit OUT FALSE hm2_7i76e.0.gpio.042.in 26 bit OUT TRUE hm2_7i76e.0.gpio.042.in_not 26 bit IN FALSE hm2_7i76e.0.gpio.042.out 26 bit OUT FALSE hm2_7i76e.0.gpio.043.in 26 bit OUT TRUE hm2_7i76e.0.gpio.043.in_not 26 bit IN FALSE hm2_7i76e.0.gpio.043.out 26 bit OUT FALSE hm2_7i76e.0.gpio.044.in 26 bit OUT TRUE hm2_7i76e.0.gpio.044.in_not 26 bit IN FALSE hm2_7i76e.0.gpio.044.out 26 bit OUT FALSE hm2_7i76e.0.gpio.045.in 26 bit OUT TRUE hm2_7i76e.0.gpio.045.in_not 26 bit IN FALSE hm2_7i76e.0.gpio.045.out 26 bit OUT TRUE hm2_7i76e.0.gpio.046.in 26 bit OUT FALSE hm2_7i76e.0.gpio.046.in_not 26 bit OUT TRUE hm2_7i76e.0.gpio.047.in 26 bit OUT FALSE hm2_7i76e.0.gpio.047.in_not 26 bit IN FALSE hm2_7i76e.0.gpio.047.out 26 bit OUT TRUE hm2_7i76e.0.gpio.048.in 26 bit OUT FALSE hm2_7i76e.0.gpio.048.in_not 26 bit IN FALSE hm2_7i76e.0.gpio.048.out 26 bit OUT TRUE hm2_7i76e.0.gpio.049.in 26 bit OUT FALSE hm2_7i76e.0.gpio.049.in_not 26 bit IN FALSE hm2_7i76e.0.gpio.049.out 26 bit OUT TRUE hm2_7i76e.0.gpio.050.in 26 bit OUT FALSE hm2_7i76e.0.gpio.050.in_not 26 bit IN FALSE hm2_7i76e.0.gpio.050.out 26 bit IN FALSE hm2_7i76e.0.led.CR01 26 bit IN FALSE hm2_7i76e.0.led.CR02 26 bit IN FALSE hm2_7i76e.0.led.CR03 26 bit IN FALSE hm2_7i76e.0.led.CR04 26 bit OUT FALSE hm2_7i76e.0.packet-error 26 bit OUT FALSE hm2_7i76e.0.packet-error-exceeded 26 s32 OUT 0 hm2_7i76e.0.packet-error-level 26 s32 OUT 0 hm2_7i76e.0.read-request.time 26 s32 OUT 202216 hm2_7i76e.0.read.time 26 u32 OUT 0x00000000 hm2_7i76e.0.sserial.port-0.fault-count 26 u32 OUT 0x00000003 hm2_7i76e.0.sserial.port-0.port_state 26 u32 OUT 0x00000000 hm2_7i76e.0.sserial.port-0.port_state2 26 u32 OUT 0x00000000 hm2_7i76e.0.sserial.port-0.port_state3 26 bit IN TRUE hm2_7i76e.0.sserial.port-0.run 26 bit IN TRUE hm2_7i76e.0.stepgen.00.control-type 26 s32 OUT 0 hm2_7i76e.0.stepgen.00.counts 26 float OUT 0 hm2_7i76e.0.stepgen.00.dbg_err_at_match 26 float OUT 0 hm2_7i76e.0.stepgen.00.dbg_ff_vel 26 float OUT 0 hm2_7i76e.0.stepgen.00.dbg_pos_minus_prev_cmd 26 float OUT 0 hm2_7i76e.0.stepgen.00.dbg_s_to_match 26 s32 OUT 0 hm2_7i76e.0.stepgen.00.dbg_step_rate 26 float OUT 0 hm2_7i76e.0.stepgen.00.dbg_vel_error 26 bit IN FALSE hm2_7i76e.0.stepgen.00.enable <== x-enable 26 float IN 0 hm2_7i76e.0.stepgen.00.position-cmd 26 float OUT 0 hm2_7i76e.0.stepgen.00.position-fb ==> x-pos-fb 26 float IN 0 hm2_7i76e.0.stepgen.00.velocity-cmd <== x-output 26 float OUT 0 hm2_7i76e.0.stepgen.00.velocity-fb 26 bit IN TRUE hm2_7i76e.0.stepgen.01.control-type 26 s32 OUT 0 hm2_7i76e.0.stepgen.01.counts 26 float OUT 0 hm2_7i76e.0.stepgen.01.dbg_err_at_match 26 float OUT 0 hm2_7i76e.0.stepgen.01.dbg_ff_vel 26 float OUT 0 hm2_7i76e.0.stepgen.01.dbg_pos_minus_prev_cmd 26 float OUT 0 hm2_7i76e.0.stepgen.01.dbg_s_to_match 26 s32 OUT 0 hm2_7i76e.0.stepgen.01.dbg_step_rate 26 float OUT 0 hm2_7i76e.0.stepgen.01.dbg_vel_error 26 bit IN FALSE hm2_7i76e.0.stepgen.01.enable <== y-enable 26 float IN 0 hm2_7i76e.0.stepgen.01.position-cmd 26 float OUT 0 hm2_7i76e.0.stepgen.01.position-fb ==> y-pos-fb 26 float IN 0 hm2_7i76e.0.stepgen.01.velocity-cmd <== y-output 26 float OUT 0 hm2_7i76e.0.stepgen.01.velocity-fb 26 bit IN TRUE hm2_7i76e.0.stepgen.02.control-type 26 s32 OUT 0 hm2_7i76e.0.stepgen.02.counts 26 float OUT 0 hm2_7i76e.0.stepgen.02.dbg_err_at_match 26 float OUT 0 hm2_7i76e.0.stepgen.02.dbg_ff_vel 26 float OUT 0 hm2_7i76e.0.stepgen.02.dbg_pos_minus_prev_cmd 26 float OUT 0 hm2_7i76e.0.stepgen.02.dbg_s_to_match 26 s32 OUT 0 hm2_7i76e.0.stepgen.02.dbg_step_rate 26 float OUT 0 hm2_7i76e.0.stepgen.02.dbg_vel_error 26 bit IN FALSE hm2_7i76e.0.stepgen.02.enable <== z-enable 26 float IN 0 hm2_7i76e.0.stepgen.02.position-cmd 26 float OUT 0 hm2_7i76e.0.stepgen.02.position-fb ==> z-pos-fb 26 float IN 0 hm2_7i76e.0.stepgen.02.velocity-cmd <== z-output 26 float OUT 0 hm2_7i76e.0.stepgen.02.velocity-fb 26 bit IN FALSE hm2_7i76e.0.stepgen.03.control-type 26 s32 OUT 0 hm2_7i76e.0.stepgen.03.counts 26 float OUT 0 hm2_7i76e.0.stepgen.03.dbg_err_at_match 26 float OUT 0 hm2_7i76e.0.stepgen.03.dbg_ff_vel 26 float OUT 0 hm2_7i76e.0.stepgen.03.dbg_pos_minus_prev_cmd 26 float OUT 0 hm2_7i76e.0.stepgen.03.dbg_s_to_match 26 s32 OUT 0 hm2_7i76e.0.stepgen.03.dbg_step_rate 26 float OUT 0 hm2_7i76e.0.stepgen.03.dbg_vel_error 26 bit IN FALSE hm2_7i76e.0.stepgen.03.enable 26 float IN 0 hm2_7i76e.0.stepgen.03.position-cmd 26 float OUT 0 hm2_7i76e.0.stepgen.03.position-fb 26 float IN 0 hm2_7i76e.0.stepgen.03.velocity-cmd 26 float OUT 0 hm2_7i76e.0.stepgen.03.velocity-fb 26 bit IN FALSE hm2_7i76e.0.stepgen.04.control-type 26 s32 OUT 0 hm2_7i76e.0.stepgen.04.counts 26 float OUT 0 hm2_7i76e.0.stepgen.04.dbg_err_at_match 26 float OUT 0 hm2_7i76e.0.stepgen.04.dbg_ff_vel 26 float OUT 0 hm2_7i76e.0.stepgen.04.dbg_pos_minus_prev_cmd 26 float OUT 0 hm2_7i76e.0.stepgen.04.dbg_s_to_match 26 s32 OUT 0 hm2_7i76e.0.stepgen.04.dbg_step_rate 26 float OUT 0 hm2_7i76e.0.stepgen.04.dbg_vel_error 26 bit IN FALSE hm2_7i76e.0.stepgen.04.enable 26 float IN 0 hm2_7i76e.0.stepgen.04.position-cmd 26 float OUT 0 hm2_7i76e.0.stepgen.04.position-fb 26 float IN 0 hm2_7i76e.0.stepgen.04.velocity-cmd 26 float OUT 0 hm2_7i76e.0.stepgen.04.velocity-fb 26 s32 IN 1 hm2_7i76e.0.stepgen.timer-number 26 bit I/O FALSE hm2_7i76e.0.watchdog.has_bit 26 s32 OUT 20398 hm2_7i76e.0.write.time <=> hm2_7i76e.0.encoder.00.index-enable <== hm2_7i76e.0.encoder.00.position <== hm2_7i76e.0.encoder.00.velocity ==> hm2_7i76e.0.stepgen.00.enable ==> hm2_7i76e.0.stepgen.00.velocity-cmd <== hm2_7i76e.0.stepgen.00.position-fb ==> hm2_7i76e.0.stepgen.01.enable ==> hm2_7i76e.0.stepgen.01.velocity-cmd <== hm2_7i76e.0.stepgen.01.position-fb ==> hm2_7i76e.0.stepgen.02.enable ==> hm2_7i76e.0.stepgen.02.velocity-cmd <== hm2_7i76e.0.stepgen.02.position-fb 26 u32 RO 0x00000000 hm2_7i76e.0.7i76.0.0.analogin0 26 u32 RO 0x00000000 hm2_7i76e.0.7i76.0.0.analogin1 26 u32 RO 0x00000000 hm2_7i76e.0.7i76.0.0.analogin2 26 u32 RO 0x00000000 hm2_7i76e.0.7i76.0.0.analogin3 26 u32 RO 0x00000000 hm2_7i76e.0.7i76.0.0.encmode0 26 u32 RO 0x00000000 hm2_7i76e.0.7i76.0.0.encmode1 26 u32 RO 0x00005440 hm2_7i76e.0.7i76.0.0.fieldvoltage 26 u32 RW 0x00000001 hm2_7i76e.0.7i76.0.0.hwrevision 26 u32 RW 0x00000009 hm2_7i76e.0.7i76.0.0.nvbaudrate 26 u32 RO 0x00000000 hm2_7i76e.0.7i76.0.0.nvencmode0 26 u32 RO 0x00000000 hm2_7i76e.0.7i76.0.0.nvencmode1 26 u32 RO 0x1A000094 hm2_7i76e.0.7i76.0.0.nvunitnumber 26 u32 RO 0x00000032 hm2_7i76e.0.7i76.0.0.nvwatchdogtimeout 26 bit RW FALSE hm2_7i76e.0.7i76.0.0.output-00-invert 26 bit RW FALSE hm2_7i76e.0.7i76.0.0.output-01-invert 26 bit RW FALSE hm2_7i76e.0.7i76.0.0.output-02-invert 26 bit RW FALSE hm2_7i76e.0.7i76.0.0.output-03-invert 26 bit RW FALSE hm2_7i76e.0.7i76.0.0.output-04-invert 26 bit RW FALSE hm2_7i76e.0.7i76.0.0.output-05-invert 26 bit RW FALSE hm2_7i76e.0.7i76.0.0.output-06-invert 26 bit RW FALSE hm2_7i76e.0.7i76.0.0.output-07-invert 26 bit RW FALSE hm2_7i76e.0.7i76.0.0.output-08-invert 26 bit RW FALSE hm2_7i76e.0.7i76.0.0.output-09-invert 26 bit RW FALSE hm2_7i76e.0.7i76.0.0.output-10-invert 26 bit RW FALSE hm2_7i76e.0.7i76.0.0.output-11-invert 26 bit RW FALSE hm2_7i76e.0.7i76.0.0.output-12-invert 26 bit RW FALSE hm2_7i76e.0.7i76.0.0.output-13-invert 26 bit RW FALSE hm2_7i76e.0.7i76.0.0.output-14-invert 26 bit RW FALSE hm2_7i76e.0.7i76.0.0.output-15-invert 26 bit RW FALSE hm2_7i76e.0.7i76.0.0.spindir-invert 26 bit RW FALSE hm2_7i76e.0.7i76.0.0.spinena-invert 26 float RW 100 hm2_7i76e.0.7i76.0.0.spinout-maxlim 26 float RW 0 hm2_7i76e.0.7i76.0.0.spinout-minlim 26 float RW 100 hm2_7i76e.0.7i76.0.0.spinout-scalemax 26 u32 RW 0x0000000E hm2_7i76e.0.7i76.0.0.swrevision 26 bit RW FALSE hm2_7i76e.0.encoder.00.counter-mode 26 bit RW TRUE hm2_7i76e.0.encoder.00.filter 26 bit RW FALSE hm2_7i76e.0.encoder.00.index-invert 26 bit RW FALSE hm2_7i76e.0.encoder.00.index-mask 26 bit RW FALSE hm2_7i76e.0.encoder.00.index-mask-invert 26 float RW 4 hm2_7i76e.0.encoder.00.scale 26 bit RW FALSE hm2_7i76e.0.encoder.00.sel0.invert_output 26 bit RW FALSE hm2_7i76e.0.encoder.00.sel0.is_opendrain 26 float RW 0.5 hm2_7i76e.0.encoder.00.vel-timeout 26 bit RW FALSE hm2_7i76e.0.gpio.012.invert_output 26 bit RW FALSE hm2_7i76e.0.gpio.012.is_opendrain 26 bit RW FALSE hm2_7i76e.0.gpio.012.is_output 26 bit RW FALSE hm2_7i76e.0.gpio.013.invert_output 26 bit RW FALSE hm2_7i76e.0.gpio.013.is_opendrain 26 bit RW FALSE hm2_7i76e.0.gpio.013.is_output 26 bit RW FALSE hm2_7i76e.0.gpio.014.invert_output 26 bit RW FALSE hm2_7i76e.0.gpio.014.is_opendrain 26 bit RW FALSE hm2_7i76e.0.gpio.014.is_output 26 bit RW FALSE hm2_7i76e.0.gpio.015.invert_output 26 bit RW FALSE hm2_7i76e.0.gpio.015.is_opendrain 26 bit RW FALSE hm2_7i76e.0.gpio.015.is_output 26 bit RW FALSE hm2_7i76e.0.gpio.016.invert_output 26 bit RW FALSE hm2_7i76e.0.gpio.016.is_opendrain 26 bit RW FALSE hm2_7i76e.0.gpio.016.is_output 26 bit RW FALSE hm2_7i76e.0.gpio.017.invert_output 26 bit RW FALSE hm2_7i76e.0.gpio.017.is_opendrain 26 bit RW FALSE hm2_7i76e.0.gpio.017.is_output 26 bit RW FALSE hm2_7i76e.0.gpio.018.invert_output 26 bit RW FALSE hm2_7i76e.0.gpio.018.is_opendrain 26 bit RW FALSE hm2_7i76e.0.gpio.018.is_output 26 bit RW FALSE hm2_7i76e.0.gpio.019.invert_output 26 bit RW FALSE hm2_7i76e.0.gpio.019.is_opendrain 26 bit RW FALSE hm2_7i76e.0.gpio.019.is_output 26 bit RW FALSE hm2_7i76e.0.gpio.020.invert_output 26 bit RW FALSE hm2_7i76e.0.gpio.020.is_opendrain 26 bit RW FALSE hm2_7i76e.0.gpio.020.is_output 26 bit RW FALSE hm2_7i76e.0.gpio.021.invert_output 26 bit RW FALSE hm2_7i76e.0.gpio.021.is_opendrain 26 bit RW FALSE hm2_7i76e.0.gpio.021.is_output 26 bit RW FALSE hm2_7i76e.0.gpio.022.invert_output 26 bit RW FALSE hm2_7i76e.0.gpio.022.is_opendrain 26 bit RW FALSE hm2_7i76e.0.gpio.022.is_output 26 bit RW FALSE hm2_7i76e.0.gpio.023.invert_output 26 bit RW FALSE hm2_7i76e.0.gpio.023.is_opendrain 26 bit RW FALSE hm2_7i76e.0.gpio.023.is_output 26 bit RW FALSE hm2_7i76e.0.gpio.024.invert_output 26 bit RW FALSE hm2_7i76e.0.gpio.024.is_opendrain 26 bit RW FALSE hm2_7i76e.0.gpio.024.is_output 26 bit RW FALSE hm2_7i76e.0.gpio.025.invert_output 26 bit RW FALSE hm2_7i76e.0.gpio.025.is_opendrain 26 bit RW FALSE hm2_7i76e.0.gpio.025.is_output 26 bit RW FALSE hm2_7i76e.0.gpio.026.invert_output 26 bit RW FALSE hm2_7i76e.0.gpio.026.is_opendrain 26 bit RW FALSE hm2_7i76e.0.gpio.026.is_output 26 bit RW FALSE hm2_7i76e.0.gpio.027.invert_output 26 bit RW FALSE hm2_7i76e.0.gpio.027.is_opendrain 26 bit RW FALSE hm2_7i76e.0.gpio.027.is_output 26 bit RW FALSE hm2_7i76e.0.gpio.028.invert_output 26 bit RW FALSE hm2_7i76e.0.gpio.028.is_opendrain 26 bit RW FALSE hm2_7i76e.0.gpio.028.is_output 26 bit RW FALSE hm2_7i76e.0.gpio.029.invert_output 26 bit RW FALSE hm2_7i76e.0.gpio.029.is_opendrain 26 bit RW FALSE hm2_7i76e.0.gpio.029.is_output 26 bit RW FALSE hm2_7i76e.0.gpio.030.invert_output 26 bit RW FALSE hm2_7i76e.0.gpio.030.is_opendrain 26 bit RW FALSE hm2_7i76e.0.gpio.030.is_output 26 bit RW FALSE hm2_7i76e.0.gpio.031.invert_output 26 bit RW FALSE hm2_7i76e.0.gpio.031.is_opendrain 26 bit RW FALSE hm2_7i76e.0.gpio.031.is_output 26 bit RW FALSE hm2_7i76e.0.gpio.032.invert_output 26 bit RW FALSE hm2_7i76e.0.gpio.032.is_opendrain 26 bit RW FALSE hm2_7i76e.0.gpio.032.is_output 26 bit RW FALSE hm2_7i76e.0.gpio.033.invert_output 26 bit RW FALSE hm2_7i76e.0.gpio.033.is_opendrain 26 bit RW FALSE hm2_7i76e.0.gpio.033.is_output 26 bit RW FALSE hm2_7i76e.0.gpio.037.invert_output 26 bit RW FALSE hm2_7i76e.0.gpio.037.is_opendrain 26 bit RW FALSE hm2_7i76e.0.gpio.037.is_output 26 bit RW FALSE hm2_7i76e.0.gpio.038.invert_output 26 bit RW FALSE hm2_7i76e.0.gpio.038.is_opendrain 26 bit RW FALSE hm2_7i76e.0.gpio.038.is_output 26 bit RW FALSE hm2_7i76e.0.gpio.039.invert_output 26 bit RW FALSE hm2_7i76e.0.gpio.039.is_opendrain 26 bit RW FALSE hm2_7i76e.0.gpio.039.is_output 26 bit RW FALSE hm2_7i76e.0.gpio.040.invert_output 26 bit RW FALSE hm2_7i76e.0.gpio.040.is_opendrain 26 bit RW FALSE hm2_7i76e.0.gpio.040.is_output 26 bit RW FALSE hm2_7i76e.0.gpio.041.invert_output 26 bit RW FALSE hm2_7i76e.0.gpio.041.is_opendrain 26 bit RW FALSE hm2_7i76e.0.gpio.041.is_output 26 bit RW FALSE hm2_7i76e.0.gpio.042.invert_output 26 bit RW FALSE hm2_7i76e.0.gpio.042.is_opendrain 26 bit RW FALSE hm2_7i76e.0.gpio.042.is_output 26 bit RW FALSE hm2_7i76e.0.gpio.043.invert_output 26 bit RW FALSE hm2_7i76e.0.gpio.043.is_opendrain 26 bit RW FALSE hm2_7i76e.0.gpio.043.is_output 26 bit RW FALSE hm2_7i76e.0.gpio.044.invert_output 26 bit RW FALSE hm2_7i76e.0.gpio.044.is_opendrain 26 bit RW FALSE hm2_7i76e.0.gpio.044.is_output 26 bit RW FALSE hm2_7i76e.0.gpio.045.invert_output 26 bit RW FALSE hm2_7i76e.0.gpio.045.is_opendrain 26 bit RW FALSE hm2_7i76e.0.gpio.045.is_output 26 bit RW FALSE hm2_7i76e.0.gpio.047.invert_output 26 bit RW FALSE hm2_7i76e.0.gpio.047.is_opendrain 26 bit RW FALSE hm2_7i76e.0.gpio.047.is_output 26 bit RW FALSE hm2_7i76e.0.gpio.048.invert_output 26 bit RW FALSE hm2_7i76e.0.gpio.048.is_opendrain 26 bit RW FALSE hm2_7i76e.0.gpio.048.is_output 26 bit RW FALSE hm2_7i76e.0.gpio.049.invert_output 26 bit RW FALSE hm2_7i76e.0.gpio.049.is_opendrain 26 bit RW FALSE hm2_7i76e.0.gpio.049.is_output 26 bit RW FALSE hm2_7i76e.0.gpio.050.invert_output 26 bit RW FALSE hm2_7i76e.0.gpio.050.is_opendrain 26 bit RW FALSE hm2_7i76e.0.gpio.050.is_output 26 bit RW FALSE hm2_7i76e.0.io_error 26 s32 RO 1 hm2_7i76e.0.packet-error-decrement 26 s32 RW 2 hm2_7i76e.0.packet-error-increment 26 s32 RW 10 hm2_7i76e.0.packet-error-limit 26 s32 RW 80 hm2_7i76e.0.packet-read-timeout 26 s32 RW 0 hm2_7i76e.0.read-request.tmax 26 bit RO FALSE hm2_7i76e.0.read-request.tmax-increased 26 s32 RW 349786 hm2_7i76e.0.read.tmax 26 bit RO FALSE hm2_7i76e.0.read.tmax-increased 26 bit RW FALSE hm2_7i76e.0.sserial.00.tx0.invert_output 26 bit RW FALSE hm2_7i76e.0.sserial.00.tx0.is_opendrain 26 u32 RW 0x00000001 hm2_7i76e.0.sserial.port-0.fault-dec 26 u32 RW 0x0000000A hm2_7i76e.0.sserial.port-0.fault-inc 26 u32 RW 0x000000C8 hm2_7i76e.0.sserial.port-0.fault-lim 26 bit RW FALSE hm2_7i76e.0.stepgen.00.direction.invert_output 26 bit RW FALSE hm2_7i76e.0.stepgen.00.direction.is_opendrain 26 u32 RW 0x00002710 hm2_7i76e.0.stepgen.00.dirhold 26 u32 RW 0x00002710 hm2_7i76e.0.stepgen.00.dirsetup 26 float RW 37.5 hm2_7i76e.0.stepgen.00.maxaccel 26 float RW 1.25 hm2_7i76e.0.stepgen.00.maxvel 26 float RW 200 hm2_7i76e.0.stepgen.00.position-scale 26 bit RW FALSE hm2_7i76e.0.stepgen.00.step.invert_output 26 bit RW FALSE hm2_7i76e.0.stepgen.00.step.is_opendrain 26 u32 RW 0x00000000 hm2_7i76e.0.stepgen.00.step_type 26 u32 RW 0x00001388 hm2_7i76e.0.stepgen.00.steplen 26 u32 RW 0x00001388 hm2_7i76e.0.stepgen.00.stepspace 26 u32 RW 0x00000000 hm2_7i76e.0.stepgen.00.table-data-0 26 u32 RW 0x00000000 hm2_7i76e.0.stepgen.00.table-data-1 26 u32 RW 0x00000000 hm2_7i76e.0.stepgen.00.table-data-2 26 u32 RW 0x00000000 hm2_7i76e.0.stepgen.00.table-data-3 26 bit RW FALSE hm2_7i76e.0.stepgen.01.direction.invert_output 26 bit RW FALSE hm2_7i76e.0.stepgen.01.direction.is_opendrain 26 u32 RW 0x00002710 hm2_7i76e.0.stepgen.01.dirhold 26 u32 RW 0x00002710 hm2_7i76e.0.stepgen.01.dirsetup 26 float RW 37.5 hm2_7i76e.0.stepgen.01.maxaccel 26 float RW 1.25 hm2_7i76e.0.stepgen.01.maxvel 26 float RW 200 hm2_7i76e.0.stepgen.01.position-scale 26 bit RW FALSE hm2_7i76e.0.stepgen.01.step.invert_output 26 bit RW FALSE hm2_7i76e.0.stepgen.01.step.is_opendrain 26 u32 RW 0x00000000 hm2_7i76e.0.stepgen.01.step_type 26 u32 RW 0x00001388 hm2_7i76e.0.stepgen.01.steplen 26 u32 RW 0x00001388 hm2_7i76e.0.stepgen.01.stepspace 26 u32 RW 0x00000000 hm2_7i76e.0.stepgen.01.table-data-0 26 u32 RW 0x00000000 hm2_7i76e.0.stepgen.01.table-data-1 26 u32 RW 0x00000000 hm2_7i76e.0.stepgen.01.table-data-2 26 u32 RW 0x00000000 hm2_7i76e.0.stepgen.01.table-data-3 26 bit RW FALSE hm2_7i76e.0.stepgen.02.direction.invert_output 26 bit RW FALSE hm2_7i76e.0.stepgen.02.direction.is_opendrain 26 u32 RW 0x00002710 hm2_7i76e.0.stepgen.02.dirhold 26 u32 RW 0x00002710 hm2_7i76e.0.stepgen.02.dirsetup 26 float RW 37.5 hm2_7i76e.0.stepgen.02.maxaccel 26 float RW 1.25 hm2_7i76e.0.stepgen.02.maxvel 26 float RW 200 hm2_7i76e.0.stepgen.02.position-scale 26 bit RW FALSE hm2_7i76e.0.stepgen.02.step.invert_output 26 bit RW FALSE hm2_7i76e.0.stepgen.02.step.is_opendrain 26 u32 RW 0x00000000 hm2_7i76e.0.stepgen.02.step_type 26 u32 RW 0x00001388 hm2_7i76e.0.stepgen.02.steplen 26 u32 RW 0x00001388 hm2_7i76e.0.stepgen.02.stepspace 26 u32 RW 0x00000000 hm2_7i76e.0.stepgen.02.table-data-0 26 u32 RW 0x00000000 hm2_7i76e.0.stepgen.02.table-data-1 26 u32 RW 0x00000000 hm2_7i76e.0.stepgen.02.table-data-2 26 u32 RW 0x00000000 hm2_7i76e.0.stepgen.02.table-data-3 26 bit RW FALSE hm2_7i76e.0.stepgen.03.direction.invert_output 26 bit RW FALSE hm2_7i76e.0.stepgen.03.direction.is_opendrain 26 u32 RW 0x00027FF6 hm2_7i76e.0.stepgen.03.dirhold 26 u32 RW 0x00027FF6 hm2_7i76e.0.stepgen.03.dirsetup 26 float RW 1 hm2_7i76e.0.stepgen.03.maxaccel 26 float RW 0 hm2_7i76e.0.stepgen.03.maxvel 26 float RW 1 hm2_7i76e.0.stepgen.03.position-scale 26 bit RW FALSE hm2_7i76e.0.stepgen.03.step.invert_output 26 bit RW FALSE hm2_7i76e.0.stepgen.03.step.is_opendrain 26 u32 RW 0x00000000 hm2_7i76e.0.stepgen.03.step_type 26 u32 RW 0x00027FF6 hm2_7i76e.0.stepgen.03.steplen 26 u32 RW 0x00027FF6 hm2_7i76e.0.stepgen.03.stepspace 26 u32 RW 0x00000000 hm2_7i76e.0.stepgen.03.table-data-0 26 u32 RW 0x00000000 hm2_7i76e.0.stepgen.03.table-data-1 26 u32 RW 0x00000000 hm2_7i76e.0.stepgen.03.table-data-2 26 u32 RW 0x00000000 hm2_7i76e.0.stepgen.03.table-data-3 26 bit RW FALSE hm2_7i76e.0.stepgen.04.direction.invert_output 26 bit RW FALSE hm2_7i76e.0.stepgen.04.direction.is_opendrain 26 u32 RW 0x00027FF6 hm2_7i76e.0.stepgen.04.dirhold 26 u32 RW 0x00027FF6 hm2_7i76e.0.stepgen.04.dirsetup 26 float RW 1 hm2_7i76e.0.stepgen.04.maxaccel 26 float RW 0 hm2_7i76e.0.stepgen.04.maxvel 26 float RW 1 hm2_7i76e.0.stepgen.04.position-scale 26 bit RW FALSE hm2_7i76e.0.stepgen.04.step.invert_output 26 bit RW FALSE hm2_7i76e.0.stepgen.04.step.is_opendrain 26 u32 RW 0x00000000 hm2_7i76e.0.stepgen.04.step_type 26 u32 RW 0x00027FF6 hm2_7i76e.0.stepgen.04.steplen 26 u32 RW 0x00027FF6 hm2_7i76e.0.stepgen.04.stepspace 26 u32 RW 0x00000000 hm2_7i76e.0.stepgen.04.table-data-0 26 u32 RW 0x00000000 hm2_7i76e.0.stepgen.04.table-data-1 26 u32 RW 0x00000000 hm2_7i76e.0.stepgen.04.table-data-2 26 u32 RW 0x00000000 hm2_7i76e.0.stepgen.04.table-data-3 26 u32 RW 0x004C4B40 hm2_7i76e.0.watchdog.timeout_ns 26 s32 RW 109726 hm2_7i76e.0.write.tmax 26 bit RO FALSE hm2_7i76e.0.write.tmax-increased hm2_7i76e.0.encoder.00.sel0.invert_output hm2_7i76e.0.gpio.046.invert_output hm2_7i76e.0.encoder.00.sel0.is_opendrain hm2_7i76e.0.gpio.046.is_opendrain hm2_7i76e.0.sserial.00.tx0.invert_output hm2_7i76e.0.gpio.010.invert_output hm2_7i76e.0.sserial.00.tx0.is_opendrain hm2_7i76e.0.gpio.010.is_opendrain hm2_7i76e.0.stepgen.00.direction.invert_output hm2_7i76e.0.gpio.000.invert_output hm2_7i76e.0.stepgen.00.direction.is_opendrain hm2_7i76e.0.gpio.000.is_opendrain hm2_7i76e.0.stepgen.00.step.invert_output hm2_7i76e.0.gpio.001.invert_output hm2_7i76e.0.stepgen.00.step.is_opendrain hm2_7i76e.0.gpio.001.is_opendrain hm2_7i76e.0.stepgen.01.direction.invert_output hm2_7i76e.0.gpio.002.invert_output hm2_7i76e.0.stepgen.01.direction.is_opendrain hm2_7i76e.0.gpio.002.is_opendrain hm2_7i76e.0.stepgen.01.step.invert_output hm2_7i76e.0.gpio.003.invert_output hm2_7i76e.0.stepgen.01.step.is_opendrain hm2_7i76e.0.gpio.003.is_opendrain hm2_7i76e.0.stepgen.02.direction.invert_output hm2_7i76e.0.gpio.004.invert_output hm2_7i76e.0.stepgen.02.direction.is_opendrain hm2_7i76e.0.gpio.004.is_opendrain hm2_7i76e.0.stepgen.02.step.invert_output hm2_7i76e.0.gpio.005.invert_output hm2_7i76e.0.stepgen.02.step.is_opendrain hm2_7i76e.0.gpio.005.is_opendrain hm2_7i76e.0.stepgen.03.direction.invert_output hm2_7i76e.0.gpio.006.invert_output hm2_7i76e.0.stepgen.03.direction.is_opendrain hm2_7i76e.0.gpio.006.is_opendrain hm2_7i76e.0.stepgen.03.step.invert_output hm2_7i76e.0.gpio.007.invert_output hm2_7i76e.0.stepgen.03.step.is_opendrain hm2_7i76e.0.gpio.007.is_opendrain hm2_7i76e.0.stepgen.04.direction.invert_output hm2_7i76e.0.gpio.008.invert_output hm2_7i76e.0.stepgen.04.direction.is_opendrain hm2_7i76e.0.gpio.008.is_opendrain hm2_7i76e.0.stepgen.04.step.invert_output hm2_7i76e.0.gpio.009.invert_output hm2_7i76e.0.stepgen.04.step.is_opendrain hm2_7i76e.0.gpio.009.is_opendrain 00026 7f36cff1475d 562d16ef8b20 YES 1 hm2_7i76e.0.read 00026 7f36cff146e9 562d16ef8b20 YES 0 hm2_7i76e.0.read-request 00026 7f36cff14606 562d16ef8b20 YES 1 hm2_7i76e.0.write 1 hm2_7i76e.0.read 11 hm2_7i76e.0.write

Configuration Name: HOSTMOT2 General configuration information: BoardName : MESA7I76 FPGA Size: 16 KGates FPGA Pins: 256 Number of IO Ports: 3 Width of one I/O port: 17 Clock Low frequency: 100.0000 MHz Clock High frequency: 200.0000 MHz IDROM Type: 3 Instance Stride 0: 4 Instance Stride 1: 64 Register Stride 0: 256 Register Stride 1: 256 Modules in configuration: Module: DPLL There are 1 of DPLL in configuration Version: 0 Registers: 7 BaseAddress: 7000 ClockFrequency: 100.000 MHz Register Stride: 256 bytes Instance Stride: 4 bytes Module: WatchDog There are 1 of WatchDog in configuration Version: 0 Registers: 3 BaseAddress: 0C00 ClockFrequency: 100.000 MHz Register Stride: 256 bytes Instance Stride: 4 bytes Module: IOPort There are 3 of IOPort in configuration Version: 0 Registers: 5 BaseAddress: 1000 ClockFrequency: 100.000 MHz Register Stride: 256 bytes Instance Stride: 4 bytes Module: StepGen There are 6 of StepGen in configuration Version: 2 Registers: 10 BaseAddress: 2000 ClockFrequency: 100.000 MHz Register Stride: 256 bytes Instance Stride: 4 bytes Module: MuxedQCount There are 10 of MuxedQCount in configuration Version: 4 Registers: 5 BaseAddress: 3600 ClockFrequency: 100.000 MHz Register Stride: 256 bytes Instance Stride: 4 bytes Module: MuxedQCountSel There are 1 of MuxedQCountSel in configuration Version: 0 Registers: 0 BaseAddress: 0000 ClockFrequency: 100.000 MHz Register Stride: 256 bytes Instance Stride: 4 bytes Module: SSerial There are 1 of SSerial in configuration Version: 0 Registers: 6 BaseAddress: 5B00 ClockFrequency: 100.000 MHz Register Stride: 256 bytes Instance Stride: 64 bytes Module: LED There are 1 of LED in configuration Version: 0 Registers: 1 BaseAddress: 0200 ClockFrequency: 100.000 MHz Register Stride: 256 bytes Instance Stride: 4 bytes Configuration pin-out: IO Connections for on-card Pin# I/O Pri. func Sec. func Chan Pin func Pin Dir 1 0 IOPort StepGen 0 Dir/Table2 (Out) 14 1 IOPort StepGen 0 Step/Table1 (Out) 2 2 IOPort StepGen 1 Dir/Table2 (Out) 15 3 IOPort StepGen 1 Step/Table1 (Out) 3 4 IOPort StepGen 2 Dir/Table2 (Out) 16 5 IOPort StepGen 2 Step/Table1 (Out) 4 6 IOPort StepGen 3 Dir/Table2 (Out) 17 7 IOPort StepGen 3 Step/Table1 (Out) 5 8 IOPort StepGen 4 Dir/Table2 (Out) 6 9 IOPort StepGen 4 Step/Table1 (Out) 7 10 IOPort SSerial 0 TXData1 (Out) 8 11 IOPort SSerial 0 RXData1 (In) 9 12 IOPort SSerial 0 TXData2 (Out) 10 13 IOPort SSerial 0 RXData2 (In) 11 14 IOPort MuxedQCount 4 MuxQ-IDX (In) 12 15 IOPort MuxedQCount 4 MuxQ-B (In) 13 16 IOPort MuxedQCount 4 MuxQ-A (In) IO Connections for P1 Pin# I/O Pri. func Sec. func Chan Pin func Pin Dir 1 17 IOPort None 14 18 IOPort None 2 19 IOPort None 15 20 IOPort None 3 21 IOPort None 16 22 IOPort StepGen 5 Step/Table1 (Out) 4 23 IOPort None 17 24 IOPort StepGen 5 Dir/Table2 (Out) 5 25 IOPort None 6 26 IOPort None 7 27 IOPort None 8 28 IOPort None 9 29 IOPort None 10 30 IOPort None 11 31 IOPort None 12 32 IOPort None 13 33 IOPort None IO Connections for P2 Pin# I/O Pri. func Sec. func Chan Pin func Pin Dir 1 34 IOPort MuxedQCount 0 MuxQ-A (In) 14 35 IOPort MuxedQCount 0 MuxQ-B (In) 2 36 IOPort MuxedQCount 0 MuxQ-IDX (In) 15 37 IOPort MuxedQCount 1 MuxQ-A (In) 3 38 IOPort MuxedQCount 1 MuxQ-B (In) 16 39 IOPort MuxedQCount 1 MuxQ-IDX (In) 4 40 IOPort MuxedQCount 2 MuxQ-A (In) 17 41 IOPort MuxedQCount 2 MuxQ-B (In) 5 42 IOPort MuxedQCount 2 MuxQ-IDX (In) 6 43 IOPort MuxedQCount 3 MuxQ-A (In) 7 44 IOPort MuxedQCount 3 MuxQ-B (In) 8 45 IOPort MuxedQCount 3 MuxQ-IDX (In) 9 46 IOPort MuxedQCountSel 0 MuxSel0 (Out) 10 47 IOPort None 11 48 IOPort SSerial 0 RXData3 (In) 12 49 IOPort SSerial 0 TXData3 (Out) 13 50 IOPort SSerial 0 TXEn3 (Out)

library IEEE; use IEEE.std_logic_1164.all; -- defines std_logic types use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics -- http://www.mesanet.com -- -- This program is is licensed under a disjunctive dual license giving you -- the choice of one of the two following sets of free software/open source -- licensing terms: -- -- * GNU General Public License (GPL), version 2.0 or later -- * 3-clause BSD License -- -- -- The GNU GPL License: -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -- -- -- The 3-clause BSD License: -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- * Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- -- * Redistributions in binary form must reproduce the above -- copyright notice, this list of conditions and the following -- disclaimer in the documentation and/or other materials -- provided with the distribution. -- -- * Neither the name of Mesa Electronics nor the names of its -- contributors may be used to endorse or promote products -- derived from this software without specific prior written -- permission. -- -- -- Disclaimer: -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- use work.IDROMConst.all; package PIN_7i76x1_7i89x2D_x15ABOB_51 is constant ModuleID : ModuleIDType :=( (HM2DPLLTag, x"00", ClockLowTag, x"01", HM2DPLLBaseRateAddr&PadT, HM2DPLLNumRegs, x"00", HM2DPLLMPBitMask), (WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask), (IOPortTag, x"00", ClockLowTag, x"03", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask), (StepGenTag, x"02", ClockLowTag, x"06", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask), (MuxedQcountTag, MQCRev, ClockLowTag, x"0A", MuxedQcounterAddr&PadT, MuxedQCounterNumRegs,x"00", MuxedQCounterMPBitMask), (MuxedQCountSelTag, x"00", ClockLowTag, x"01", NullAddr&PadT, x"00", x"00", x"00000000"), (SSerialTag, x"00", ClockLowTag, x"01", SSerialCommandAddr&PadT, SSerialNumRegs, x"10", SSerialMPBitMask), (LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000") ); constant PinDesc : PinDescType :=( -- Base func sec unit sec func sec pin IOPortTag & x"00" & StepGenTag & StepGenDirPin, -- I/O 00 embedded 7I76 IOPortTag & x"00" & StepGenTag & StepGenStepPin, -- I/O 01 IOPortTag & x"01" & StepGenTag & StepGenDirPin, -- I/O 02 IOPortTag & x"01" & StepGenTag & StepGenStepPin, -- I/O 03 IOPortTag & x"02" & StepGenTag & StepGenDirPin, -- I/O 04 IOPortTag & x"02" & StepGenTag & StepGenStepPin, -- I/O 05 IOPortTag & x"03" & StepGenTag & StepGenDirPin, -- I/O 06 IOPortTag & x"03" & StepGenTag & StepGenStepPin, -- I/O 07 IOPortTag & x"04" & StepGenTag & StepGenDirPin, -- I/O 08 IOPortTag & x"04" & StepGenTag & StepGenStepPin, -- I/O 09 IOPortTag & x"00" & SSerialTag & SSerialTX0Pin, -- I/O 10 IOPortTag & x"00" & SSerialTag & SSerialRX0Pin, -- I/O 11 IOPortTag & x"00" & SSerialTag & SSerialTX1Pin, -- I/O 12 IOPortTag & x"00" & SSerialTag & SSerialRX1Pin, -- I/O 13 IOPortTag & x"04" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 14 IOPortTag & x"04" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 15 IOPortTag & x"04" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 16 -- P1 -- 5ABOB pinout -- 26 HDR -- IDC DB25 IOPortTag & x"00" & NullTag & NullPin, -- I/O 01 PIN 1 PIN 1 Spindle DAC PWM IOPortTag & x"00" & NullTag & NullPin, -- I/O 02 PIN 2 PIN 14 just GPIO IOPortTag & x"00" & NullTag & NullPin, -- I/O 03 PIN 3 PIN 2 just GPIO IOPortTag & x"00" & NullTag & NullPin, -- I/O 04 PIN 4 PIN 15 just GPIO IOPortTag & x"00" & NullTag & NullPin, -- I/O 05 PIN 5 PIN 3 just GPIO IOPortTag & x"05" & StepGenTag & StepGenStepPin, -- I/O 06 PIN 6 PIN 16 B2 Step IOPortTag & x"00" & NullTag & NullPin, -- I/O 07 PIN 7 PIN 4 just GPIO IOPortTag & x"05" & StepGenTag & StepGenDirPin, -- I/O 08 PIN 8 PIN 17 B2 Dir IOPortTag & x"00" & NullTag & NullPin, -- I/O 09 PIN 9 PIN 5 just GPIO IOPortTag & x"00" & NullTag & NullPin, -- I/O 10 PIN 11 PIN 6 just GPIO IOPortTag & x"00" & NullTag & NullPin, -- I/O 11 PIN 13 PIN 7 just GPIO IOPortTag & x"00" & NullTag & NullPin, -- I/O 12 PIN 15 PIN 8 just GPIO IOPortTag & x"00" & NullTag & NullPin, -- I/O 13 PIN 17 PIN 9 just GPIO IOPortTag & x"00" & NullTag & NullPin, -- I/O 14 PIN 19 PIN 10 just GPIO IOPortTag & x"00" & NullTag & NullPin, -- I/O 15 PIN 21 PIN 11 just GPIO IOPortTag & x"00" & NullTag & NullPin, -- I/O 16 PIN 23 PIN 12 just GPIO IOPortTag & x"00" & NullTag & NullPin, -- I/O 33 PIN 25 PIN 13 just GPIO -- P2 HDR26 DB25 IOPortTag & x"00" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 17 PIN 1 PIN 1 IOPortTag & x"00" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 18 PIN 14 PIN 2 IOPortTag & x"00" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 19 PIN 2 PIN 3 IOPortTag & x"01" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 20 PIN 15 PIN 4 IOPortTag & x"01" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 21 PIN 3 PIN 5 IOPortTag & x"01" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 22 PIN 16 PIN 6 IOPortTag & x"02" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 23 PIN 4 PIN 7 IOPortTag & x"02" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 24 PIN 17 PIN 8 IOPortTag & x"02" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 25 PIN 5 PIN 9 IOPortTag & x"03" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 26 PIN 6 PIN 11 IOPortTag & x"03" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 27 PIN 7 PIN 13 IOPortTag & x"03" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 28 PIN 8 PIN 15 IOPortTag & x"00" & MuxedQCountSelTag & MuxedQCountSel0Pin, -- I/O 29 PIN 9 PIN 17 IOPortTag & x"00" & NullTag & NullPin, -- I/O 30 PIN 10 PIN 19 powop IOPortTag & x"00" & SSerialTag & SSerialRX2Pin, -- I/O 31 PIN 11 PIN 21 IOPortTag & x"00" & SSerialTag & SSerialTX2Pin, -- I/O 32 PIN 12 PIN 23 IOPortTag & x"00" & SSerialTag & SSerialTXEN2Pin, -- I/O 33 PIN 13 PIN 25 LIOPortTag & x"00" & SSerialTag & SSerialNTXEn1Pin, emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, emptypin,emptypin,emptypin,emptypin,emptypin, emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for IDROM v3 emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin); end package PIN_7i76x1_7i89x2D_x15ABOB_51;