7i76e Bit File Problem

mesaflash --device 7i76e --addr 10.10.10.10 --readhmid Configuration Name: HOSTMOT2 General configuration information: BoardName : MESA7I76 FPGA Size: 16 KGates FPGA Pins: 256 Number of IO Ports: 3 Width of one I/O port: 17 Clock Low frequency: 100.0000 MHz Clock High frequency: 200.0000 MHz IDROM Type: 3 Instance Stride 0: 4 Instance Stride 1: 64 Register Stride 0: 256 Register Stride 1: 256 Modules in configuration: Module: DPLL There are 1 of DPLL in configuration Version: 0 Registers: 7 BaseAddress: 7000 ClockFrequency: 100.000 MHz Register Stride: 256 bytes Instance Stride: 4 bytes Module: WatchDog There are 1 of WatchDog in configuration Version: 0 Registers: 3 BaseAddress: 0C00 ClockFrequency: 100.000 MHz Register Stride: 256 bytes Instance Stride: 4 bytes Module: IOPort There are 3 of IOPort in configuration Version: 0 Registers: 5 BaseAddress: 1000 ClockFrequency: 100.000 MHz Register Stride: 256 bytes Instance Stride: 4 bytes Module: StepGen There are 15 of StepGen in configuration Version: 2 Registers: 10 BaseAddress: 2000 ClockFrequency: 100.000 MHz Register Stride: 256 bytes Instance Stride: 4 bytes Module: QCount There are 3 of QCount in configuration Version: 2 Registers: 5 BaseAddress: 3000 ClockFrequency: 100.000 MHz Register Stride: 256 bytes Instance Stride: 4 bytes Module: SSerial There are 1 of SSerial in configuration Version: 0 Registers: 6 BaseAddress: 5A00 ClockFrequency: 100.000 MHz Register Stride: 256 bytes Instance Stride: 64 bytes Module: LED There are 1 of LED in configuration Version: 0 Registers: 1 BaseAddress: 0200 ClockFrequency: 100.000 MHz Register Stride: 256 bytes Instance Stride: 4 bytes Configuration pin-out: IO Connections for on-card Pin# I/O Pri. func Sec. func Chan Pin func Pin Dir TB2 4,5 0 IOPort StepGen 0 Dir/Table2 (Out) TB2 2,3 1 IOPort StepGen 0 Step/Table1 (Out) TB2 10,11 2 IOPort StepGen 1 Dir/Table2 (Out) TB2 8,9 3 IOPort StepGen 1 Step/Table1 (Out) TB2 16,17 4 IOPort StepGen 2 Dir/Table2 (Out) TB2 14,15 5 IOPort StepGen 2 Step/Table1 (Out) TB2 22,23 6 IOPort StepGen 3 Dir/Table2 (Out) TB2 20,21 7 IOPort StepGen 3 Step/Table1 (Out) TB3 4,5 8 IOPort StepGen 4 Dir/Table2 (Out) TB3 2,3 9 IOPort StepGen 4 Step/Table1 (Out) Internal 10 IOPort SSerial 0 TXData0 (Out) Internal 11 IOPort SSerial 0 RXData0 (In) TB3 18,19 12 IOPort SSerial 0 TXData1 (Out) TB3 16,17 13 IOPort SSerial 0 RXData1 (In) TB3 13,14 14 IOPort QCount 0 Quad-IDX (In) TB3 10,11 15 IOPort QCount 0 Quad-B (In) TB3 7,8 16 IOPort QCount 0 Quad-A (In) IO Connections for P1 Pin# I/O Pri. func Sec. func Chan Pin func Pin Dir 1 17 IOPort StepGen 5 Dir/Table2 (Out) 14 18 IOPort StepGen 5 Step/Table1 (Out) 2 19 IOPort StepGen 6 Dir/Table2 (Out) 15 20 IOPort StepGen 6 Step/Table1 (Out) 3 21 IOPort StepGen 7 Dir/Table2 (Out) 16 22 IOPort StepGen 7 Step/Table1 (Out) 4 23 IOPort StepGen 8 Dir/Table2 (Out) 17 24 IOPort StepGen 8 Step/Table1 (Out) 5 25 IOPort StepGen 9 Dir/Table2 (Out) 6 26 IOPort StepGen 9 Step/Table1 (Out) 7 27 IOPort SSerial 0 TXData2 (Out) 8 28 IOPort SSerial 0 RXData2 (In) 9 29 IOPort SSerial 0 TXData3 (Out) 10 30 IOPort SSerial 0 RXData3 (In) 11 31 IOPort QCount 1 Quad-IDX (In) 12 32 IOPort QCount 1 Quad-B (In) 13 33 IOPort QCount 1 Quad-A (In) IO Connections for P2 Pin# I/O Pri. func Sec. func Chan Pin func Pin Dir 1 34 IOPort StepGen 10 Dir/Table2 (Out) 14 35 IOPort StepGen 10 Step/Table1 (Out) 2 36 IOPort StepGen 11 Dir/Table2 (Out) 15 37 IOPort StepGen 11 Step/Table1 (Out) 3 38 IOPort StepGen 12 Dir/Table2 (Out) 16 39 IOPort StepGen 12 Step/Table1 (Out) 4 40 IOPort StepGen 13 Dir/Table2 (Out) 17 41 IOPort StepGen 13 Step/Table1 (Out) 5 42 IOPort StepGen 14 Dir/Table2 (Out) 6 43 IOPort StepGen 14 Step/Table1 (Out) 7 44 IOPort SSerial 0 TXData4 (Out) 8 45 IOPort SSerial 0 RXData4 (In) 9 46 IOPort SSerial 0 TXData5 (Out) 10 47 IOPort SSerial 0 RXData5 (In) 11 48 IOPort QCount 2 Quad-IDX (In) 12 49 IOPort QCount 2 Quad-B (In) 13 50 IOPort QCount 2 Quad-A (In)