Currently i'm trying to adapt the 7i90 firmware on a xc6slx16 FT(G)256 Dev-Board
So i already changed:
- The matching pinout in the .ucf file
- The package type in the.xise file
- The pincount and fpga size in the i90_x9card file
The thing that is not quite clear to me is : Where and which clock settings to changed, since the board has a 25Mhz oscillator instead the 50Mhz on the original board. Which clocks and/or setting should be changed, and what are they used for?
I found the following:
i90_x9card.vhd > IDROMConst.vhd
- constant ClockHigh90: integer := 200000000;
- constant ClockMed90: integer := 100000000;
- constant ClockLow90: integer := 100000000
7i90spi.ucf
- TIMESPEC "TS_CLK" = PERIOD "CLK" 19.9 ns HIGH 50 %;
- TIMESPEC "TS_COM_SPICLK" = PERIOD "COM_SPICLK" 9 ns HIGH 50 %;
TopGCSPIHostMot2.vhd
- signal fclk : std_logic;
signal clkfx0: std_logic;
signal clk0_0: std_logic;
signal clklow : std_logic;
signal clkfx1: std_logic;
signal clk0_1: std_logic;
- clklow => clklow, -- I/O clock
clkmed => clklow, -- Processor clock
clkhigh => fclk, -- PWM clock
- ClockMultH : DCM
generic map (
CLKDV_DIVIDE => 2.0,
CLKFX_DIVIDE => 2,
CLKFX_MULTIPLY => 8, -- 8 FOR 200 MHz
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 20.0,
- ClockMultM : DCM
generic map (
CLKDV_DIVIDE => 2.0,
CLKFX_DIVIDE => 2,
CLKFX_MULTIPLY => 4, -- 4 FOR 100 MHz
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 20.0,
- asimplspi: entity work.simplespi8 -- configuration serial EEPROM access SPI port
generic map
(
buswidth => 8,
div => 7, -- for divide by 8 -- 12.5 MHz
Should only the clk periods be changed from 20 to 40, or should the clk dividers also be adapted?
Thanks in advance,
