- Posts: 51
- Thank you received: 0
ColorCNC Colorlight 5A-75E/5A-75B as FPGA controller board
1 month 4 weeks ago #349173
by romanetz
Replied by romanetz on topic ColorCNC Colorlight 5A-75E/5A-75B as FPGA controller board
I'd like to share some latest information regarding current status of the project.
Support of serial port (with almost the same principle as pktuart) has been added in last pull request. Yet not approved by Peter. github.com/Peter-van-Tol/LiteX-CNC/pull/155
Support of serial port (with almost the same principle as pktuart) has been added in last pull request. Yet not approved by Peter. github.com/Peter-van-Tol/LiteX-CNC/pull/155
Please Log in to join the conversation.
2 weeks 5 days ago #350199
by romanetz
Replied by romanetz on topic ColorCNC Colorlight 5A-75E/5A-75B as FPGA controller board
Hi everyone, I wanted to share my progress on developing an EtherCAT slave for the Colorlight 5A-75E board integrated with LiteXCNC, and hopefully get some advice from the community.The basic skeleton of the firmware is ready. The board is alive and successfully responding to the master's initial requests—the physical layer and core logic are up and running. Right now, I am focusing on debugging the SII EEPROM emulation. As soon as board gets to PREOP/OP state, I will share further updates.
Please Log in to join the conversation.
2 weeks 3 days ago #350244
by romanetz
Replied by romanetz on topic ColorCNC Colorlight 5A-75E/5A-75B as FPGA controller board
Update: PREOP reached, full SII EEPROM interface workingQuick update on the Colorlight 5A-75E EtherCAT slave.Since my last post, quite a bit has moved:What works now:
CoE mailbox is not implemented on the FPGA side yet, so IgH fails on
CoE SDO upload (
PDO assign) and never reaches SAFEOP/OP.Next steps:
github.com/romanetz/liteethercat Architecture and roadmap:
in the repo.The project continues the same modular LiteX approach. Once the slave
is in OP and HAL pins react to encoder movement, I'll post a video.
- SII EEPROM emulation fully implemented and verified with IgH master
-
reads identity correctly:Code:ethercat slaves -v
- Vendor Id:
, Product code:Code:0xDEADBABECode:0x00C0FFEE
- All SII categories parsed: STRINGS, GENERAL, FMMU, SYNCM
- Vendor Id:
- AL state machine:
Code:INIT → PREOP
- IgH configures SM0/SM1 and accepts the slave in PREOP
CoE mailbox is not implemented on the FPGA side yet, so IgH fails on
CoE SDO upload (
Code:
0x1C12
- Remove CoE declaration from ESI to bypass mailbox requirement for
Phase 1 (bring-up with LinuxCNC and quadrature encoders) - Then decide: implement mailbox via VexRiscv + SOES (Phase 2), or
keep CoE-free with PDO mapping from ESI
github.com/romanetz/liteethercat Architecture and roadmap:
Code:
docs/architecture.md
is in OP and HAL pins react to encoder movement, I'll post a video.
Please Log in to join the conversation.
2 weeks 3 days ago #350245
by romanetz
Replied by romanetz on topic ColorCNC Colorlight 5A-75E/5A-75B as FPGA controller board
(venv) engin@engin:~/litex-work/liteeth/bench/ESC$ ethercat slaves -v -p 0
=== Master 0, Slave 0 ===
Device: Main
State: PREOP
Flag: E
Identity:
Vendor Id: 0xdeadbabe
Product code: 0x00c0ffee
Revision number: 0x00000001
Serial number: 0x00000000
DL information:
FMMU bit operation: no
Distributed clocks: no
Port Type Link Loop Signal NextSlave
0 MII up open yes -
1 MII down closed no -
2 N/A down closed no -
3 N/A down closed no -
Mailboxes:
Bootstrap RX: 0x0000/0, TX: 0x0000/0
Standard RX: 0x1000/128, TX: 0x1080/128
Supported protocols: CoE
General:
Group: Colorlight5A75E
Image name:
Order number:
Device name: Colorlight 5A-75E EtherCAT Device
CoE details:
Enable SDO: yes
Enable SDO Info: no
Enable PDO Assign: no
Enable PDO Configuration: no
Enable Upload at startup: no
Enable SDO complete access: no
Flags:
Enable SafeOp: no
Enable notLRW: no
Current consumption: 0 mA
=== Master 0, Slave 0 ===
Device: Main
State: PREOP
Flag: E
Identity:
Vendor Id: 0xdeadbabe
Product code: 0x00c0ffee
Revision number: 0x00000001
Serial number: 0x00000000
DL information:
FMMU bit operation: no
Distributed clocks: no
Port Type Link Loop Signal NextSlave
0 MII up open yes -
1 MII down closed no -
2 N/A down closed no -
3 N/A down closed no -
Mailboxes:
Bootstrap RX: 0x0000/0, TX: 0x0000/0
Standard RX: 0x1000/128, TX: 0x1080/128
Supported protocols: CoE
General:
Group: Colorlight5A75E
Image name:
Order number:
Device name: Colorlight 5A-75E EtherCAT Device
CoE details:
Enable SDO: yes
Enable SDO Info: no
Enable PDO Assign: no
Enable PDO Configuration: no
Enable Upload at startup: no
Enable SDO complete access: no
Flags:
Enable SafeOp: no
Enable notLRW: no
Current consumption: 0 mA
Please Log in to join the conversation.
Time to create page: 0.189 seconds
