RV901T as MESA 7i90: Custom bitstream generation with PWMTag leads to error

Still sounds like a clock setup error of some kind
maybe an introduced error in the DCM/BUFG setup
in the source.

 The SPI clock is picky because it directly drives a GCLK
that runs SPI interface logic.

The multiplied clocks are available globally  on a global clock spine
so the PWM  pinout does not matter at all.


Can you post your .ucf file?

It may be that you have a conflict between the SPI GCLK and the DCM source

Taking a look at ug382.pdf might help

Hello Peter,

PCW wrote:

Can you post your .ucf file?

Sure, here it is:
github.com/golyakoff/hostmot2-rv901t-7i9...b/master/7i90spi.ucf
(this is the complete repo of original hostmot2 with separately commited my overrides).

PCW wrote:

It may be that you have a conflict between the SPI GCLK and the DCM source

Taking a look at ug382.pdf might helpc

I started reading the manuals but not all is clear for me yet...

Did I understand the key concept right?

There are two different time domains:
1. CLK (M9) 25 MHz from the own board oscillator
2. COM_SPICLK (P59) External from RPI (24 MHz if I coerrectly remember)

...and the RPI send commands over SPI for PWM, wh8ch is driving by CLK (as you say GCLK, but I do not understand the difference). And these time domains are not synchronized and they shouldn't be... right?

Is this right?

There are at least 3 clock domains: COM_SPI_CLK, CLOCKLOW,CLOCKHIGH
Any needed synchronization is done in the firmware.

Just as a test, you might would try moving the COM_SPI GCLK pin
to another GCLK. To me this seems  like it may cause a conflict

Worst case since you cannot move the 25 MHz clock, you could try
eliminating the fclk DCM (and run everything at 100 MHz)