- Posts: 17524
- Thank you received: 0
correspondence of unused i/o pins to physical connector location?
1 year 7 months ago #324779
by PCW
Replied by PCW on topic correspondence of unused i/o pins to physical connector location?
Your table is missing the channel data, not sure why, but this is what I get:
IO Connections for TB1/TB2 -> 7I96_1
Pin# I/O Pri. func Sec. func Chan Sec. Pin func Sec. Pin Dir
TB1-2,3 17 IOPort StepGen 0 Step/Table1 (Out)
TB1-4,5 18 IOPort StepGen 0 Dir/Table2 (Out)
TB1-8,9 19 IOPort StepGen 1 Step/Table1 (Out)
TB1-10,11 20 IOPort StepGen 1 Dir/Table2 (Out)
TB1-14,15 21 IOPort StepGen 2 Step/Table1 (Out)
TB1-16,17 22 IOPort StepGen 2 Dir/Table2 (Out)
TB1-20,21 23 IOPort StepGen 3 Step/Table1 (Out)
TB1-22,23 24 IOPort StepGen 3 Dir/Table2 (Out)
TB2-2,3 25 IOPort StepGen 4 Step/Table1 (Out)
TB2-4,5 26 IOPort StepGen 4 Dir/Table2 (Out)
TB2-7,8 27 IOPort QCount 0 Quad-A (In)
TB2-10,11 28 IOPort QCount 0 Quad-B (In)
TB2-13,14 29 IOPort QCount 0 Quad-IDX (In)
TB2-16,17 30 IOPort SSerial 0 RXData0 (In)
TB2-18,19 31 IOPort SSerial 0 TXData0 (Out)
Internal-TXEn 32 IOPort SSerial 0 TXEn0 (Out)
Internal 33 IOPort SSR 0 AC Ref (Out)
Default firmware on a 7I96S is 7i96s_d.bin
IO Connections for TB1/TB2 -> 7I96_1
Pin# I/O Pri. func Sec. func Chan Sec. Pin func Sec. Pin Dir
TB1-2,3 17 IOPort StepGen 0 Step/Table1 (Out)
TB1-4,5 18 IOPort StepGen 0 Dir/Table2 (Out)
TB1-8,9 19 IOPort StepGen 1 Step/Table1 (Out)
TB1-10,11 20 IOPort StepGen 1 Dir/Table2 (Out)
TB1-14,15 21 IOPort StepGen 2 Step/Table1 (Out)
TB1-16,17 22 IOPort StepGen 2 Dir/Table2 (Out)
TB1-20,21 23 IOPort StepGen 3 Step/Table1 (Out)
TB1-22,23 24 IOPort StepGen 3 Dir/Table2 (Out)
TB2-2,3 25 IOPort StepGen 4 Step/Table1 (Out)
TB2-4,5 26 IOPort StepGen 4 Dir/Table2 (Out)
TB2-7,8 27 IOPort QCount 0 Quad-A (In)
TB2-10,11 28 IOPort QCount 0 Quad-B (In)
TB2-13,14 29 IOPort QCount 0 Quad-IDX (In)
TB2-16,17 30 IOPort SSerial 0 RXData0 (In)
TB2-18,19 31 IOPort SSerial 0 TXData0 (Out)
Internal-TXEn 32 IOPort SSerial 0 TXEn0 (Out)
Internal 33 IOPort SSR 0 AC Ref (Out)
Default firmware on a 7I96S is 7i96s_d.bin
Please Log in to join the conversation.
1 year 7 months ago #324782
by pgf
Replied by pgf on topic correspondence of unused i/o pins to physical connector location?
Oops. I've edited the table to a more convenient/compact format, and I had already edited that column out of mine, because I didn't think "Channel" was interesting (to me, at least). I hadn't realized what it represents.
Thanks.
Thanks.
Please Log in to join the conversation.
1 year 7 months ago #324793
by pgf
Replied by pgf on topic correspondence of unused i/o pins to physical connector location?
Slightly outside the original topic: pncconf lets me reconfigure what is by default an input (e.g., the Quad B i/o #28) into an output (e.g., "Machine is enabled"). Does the board really allow that? And if so, are the +/- pins for that input now complementary outputs?
paul
paul
Please Log in to join the conversation.
1 year 7 months ago #324799
by PCW
Replied by PCW on topic correspondence of unused i/o pins to physical connector location?
No, the driver will not allow that unless you disable the encoder function
and the encoder pins are always inputs on a 7I96s (hardware determined)
and the encoder pins are always inputs on a 7I96s (hardware determined)
Please Log in to join the conversation.
1 year 7 months ago #324811
by pgf
Replied by pgf on topic correspondence of unused i/o pins to physical connector location?
Thanks -- empirical evidence agrees with you.
Please Log in to join the conversation.
1 year 7 months ago #324814
by pgf
Replied by pgf on topic correspondence of unused i/o pins to physical connector location?
For future reference, is this also true of the P1 inputs -- are they also locked as inputs, assuming the default firmware?
Please Log in to join the conversation.
1 year 7 months ago #324846
by PCW
Replied by PCW on topic correspondence of unused i/o pins to physical connector location?
On bare FPGA pins (like on P1) any pin can be an input or output
_IF_ if it's secondary function is disabled (or it has no secondary function)
Secondary functions can be disabled in the hal file with the num_xxxx=N stanzas
For example, the default 7I96S firmware has just GPIO (no secondary function)
on P1 so all P1 pins can be input or output. On a more complex configuration
say 7i96s_5abobd, the P1 pins used for the second encoder inputs can only be
inputs unless you disable the second encoder in the hal file (num_encoders=1)
(this leaves the encoder on the 7I96S card itself enabled)
The hostmot2 manual page has more details
_IF_ if it's secondary function is disabled (or it has no secondary function)
Secondary functions can be disabled in the hal file with the num_xxxx=N stanzas
For example, the default 7I96S firmware has just GPIO (no secondary function)
on P1 so all P1 pins can be input or output. On a more complex configuration
say 7i96s_5abobd, the P1 pins used for the second encoder inputs can only be
inputs unless you disable the second encoder in the hal file (num_encoders=1)
(this leaves the encoder on the 7I96S card itself enabled)
The hostmot2 manual page has more details
Please Log in to join the conversation.
1 year 7 months ago #324853
by rodw
Replied by rodw on topic correspondence of unused i/o pins to physical connector location?
The inputs and outputs on TB3 are described on Page 10 of the document you shared
Please Log in to join the conversation.
1 year 7 months ago #324866
by pgf
Replied by pgf on topic correspondence of unused i/o pins to physical connector location?
Yup -- but I was asking about the TB1/TB2 pins. They're listed on the preceding pages, but only with their step/encoder/serial functions. Not as I/O pins.
Please Log in to join the conversation.
1 year 7 months ago #324905
by PCW
Replied by PCW on topic correspondence of unused i/o pins to physical connector location?
For example on TB2, if you set num_stepgens to 4, the TB2 step04/dir04 pins become
available as GPIO, but they only work as outputs because they have a buffer with its inputs
from the FPGA and outputs on TB2.
available as GPIO, but they only work as outputs because they have a buffer with its inputs
from the FPGA and outputs on TB2.
Please Log in to join the conversation.
Time to create page: 0.217 seconds
