7c81 with Raspi 4 UART connect to RS422 Port 0

Hello at all and nice to be here,

I'm working on a RPI4 with a 7c81 and I want to control the Spindle VFD via RS485.
I know there was a similar thread using the pktUART on the FPGA but what I try to achieve seems much easier.
Since the RPI TxD0 / 1 (GPIO Pin and RxD0 / 1 (GPIO Pin 10) are routed to the FPGA wouldn't it be possible to just connect them both to the SSerial Port 0?

Then I could just use hy_vfd.

I'm able to program python and C++ but VHDL is new too me.
I installed Xilinx ISE 13.4 and successfully already created a working BITFile into the Fallback space without changes.

Can you please simply put me into the direction how to connect TxD from RPI GPIO 8 to 7c81.0.Port017 as Output and RxD RPI GPIO 10 to 7c81.0.Port055 as Input?

Changing the behaviour from RS422 to RS485 will be done in Hardware with Resistors.

Thanks in advance, Harry.

It might be simpler to use a USB to RS485 converter.

hy_vfd only knows how to use ports that show up in /dev/
If the Pi UARTS are visible there then there is some chance of it working, but hy_vfd is still a user-space application, so being otherwise realtime it not much help.

Its possible and one of the reasons I connected most GPIO pins to the FPGA
but there are a few complications:

1. There doesn't seem to be any working or standard RS-485 direction control on the RPI
2 Without direction control there's no easy way to remove the RX echo of TX data
(Mesa UARTS can do this) This would likely require modifying the MODBUS driver to fix.

It might be possible to include one of the slightly shady direction control schemes that
use a re-triggerable one shot on the TX data in the FPGA. These work if the turn-around
time is at least a character time or two (and the FPGA knows or can be told the character time)

Thank you and sorry for the wall of text coming up.
You're both right...it gets complicated. For RS422 Full duplex I could go that way.
But for RS485 I would need a third GPIO TxEnable to switch direction or as PCW pointed out a shady timing....and of course it's not realtime.

Hmm, I would love to give it a try to use one RPI-GPIO as TX enable, I would take hy_vfd and expand it with a tx_enable and a timeout.

Btw, with so many RPI GPIO connected to the FPGA it's f.ex. easier to get more safety into the system with bypassing Linuxcnc to stop movements...for sure this will come up. Thank you for this.

Just as proof of concept to try this...where is it best to simply connect these three ports via the FPGA with ISE? I'm noob with FPGA:blink:

Thanks in advance.

Or maybe I should contribute to the best solution to implement it correctly via pktUART...

Probably the easiest be to modify the ucf file and add the TX/RX/TXEN lines
then have a bit of special case 7C81 (or 7C80) code that wires up the pins
(and disconnects the GPIO pin driver).

This would probably take me about 10 minutes but I likely would not get it
right the first time...

The packetUART would have the advantage or running in real time but its a fair project.
Ideally it should have a driver that uses hal_port pins for TX and RX data strings so it
becomes universal and easily accessible from hal