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- RV901T as MESA 7i90: Custom bitstream generation with PWMTag leads to error
RV901T as MESA 7i90: Custom bitstream generation with PWMTag leads to error
31 Mar 2024 20:21 #297303
by ago_tm
Hello,
I have adopted the initial pin configuration for to prepare the bitstream for RV901T: github.com/golyakoff/hostmot2-rv901t-7i9...5ec35/PIN_AGO_72.vhd.
this works fine until I try to set the number of PMW to at least 1.
I.e. this is implementing fine:
but anyway this bitstream doesn't allow to start linuxcnc:
Probably it shouldn't start as there are no PMW but it is declared... I'm not sure, anyway the goal is to have at least 1 PMV Generator. But when I change the number to x"01"...
...the error appears on the Mapping phase:
Here is the error message:
I see that Xilinx ISE tries to say me something with these words: "The clock IOB component <CLK> is placed at site <M9>... " but I don't know it well, honestly.
I tried to decrease the number of StepGens and QCounts, I even started with just 71 general I/O pins with the only "PWMAOutPin" but it doesn't work anyway. From this I make a conclusion from that the problem doesn't related to the free part of crystal but more related to the constraints.
What I understand (correct me if I wrong) all other modules are working on 100 MHz frequency, but PWM is working on 200 MHz, it is my "CLK" net and it somehow should be available to the the PWM but it doesn't.
I will appreciate for the possible suggestions.
I have adopted the initial pin configuration for to prepare the bitstream for RV901T: github.com/golyakoff/hostmot2-rv901t-7i9...5ec35/PIN_AGO_72.vhd.
this works fine until I try to set the number of PMW to at least 1.
I.e. this is implementing fine:
(PWMTag, x"00", ClockHighTag, x"00", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),but anyway this bitstream doesn't allow to start linuxcnc:
LINUXCNC - 2.9.2
Machine configuration directory is '/home/ago/linuxcnc/configs/rpi-mesa7i90-spi-test'
Machine configuration file is 'rpi-mesa7i90-spi-test.ini'
Starting LinuxCNC...
linuxcnc TPMOD=tpmod HOMEMOD=homemod EMCMOT=motmod
Note: Using POSIX realtime
Found file(REL): ./rpi-mesa7i90-spi-test.hal
hm2: loading Mesa HostMot2 driver version 0.15
probe 24000000
hm2/hm2_7i90.0: Low Level init 0.15
hm2/hm2_7i90.0: TRAM write error! (addr=0x4100, size=0, iter=0)
hm2_spi: rtapi_app_main: Input/output error (-5)
./rpi-mesa7i90-spi-test.hal:38: waitpid failed /usr/bin/rtapi_app hm2_spi
./rpi-mesa7i90-spi-test.hal:38: /usr/bin/rtapi_app exited without becoming ready
./rpi-mesa7i90-spi-test.hal:38: insmod for hm2_spi failed, returned -1
Shutting down and cleaning up LinuxCNC...
hm2_spi: not loaded
<commandline>:0: exit value: 255
<commandline>:0: rmmod failed, returned -1
hm2: unloading
<commandline>:0: unloadrt failed
Note: Using POSIX realtime
LinuxCNC terminated with an error. You can find more information in the log:
/home/ago/linuxcnc_debug.txt
and
/home/ago/linuxcnc_print.txt
as well as in the output of the shell command 'dmesg' and in the terminalProbably it shouldn't start as there are no PMW but it is declared... I'm not sure, anyway the goal is to have at least 1 PMV Generator. But when I change the number to x"01"...
(PWMTag, x"00", ClockHighTag, x"01", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),...the error appears on the Mapping phase:
Process "Map" failedHere is the error message:
Place:1115 - Unroutable Placement! A clock IOB / BUFIO clock component pair have been found that are not placed at a routable clock IOB / BUFIO site pair. The clock IOB component <CLK> is placed at site <M9>. The BUFIO component <SP6_BUFIO_INSERT_ML_BUFIO2_1> is placed at site <BUFIO2_X4Y21>. Each BUFIO site has a select set of IOBs that can drive it. If these IOBs are not used, the connection is not routable You may want to analyze why this problem exists and correct it. This placement is UNROUTABLE in PAR and therefore, this error condition should be fixed in your design. You may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a WARNING in order to generate an NCD file. This NCD file can then be used in FPGA Editor to debug the problem. A list of all the COMP.PINS used in this clock placement rule is listed below. These examples can be used directly in the .ucf file to demote this ERROR to a WARNING.
< NET "CLK" CLOCK_DEDICATED_ROUTE = FALSE; >
I see that Xilinx ISE tries to say me something with these words: "The clock IOB component <CLK> is placed at site <M9>... " but I don't know it well, honestly.
I tried to decrease the number of StepGens and QCounts, I even started with just 71 general I/O pins with the only "PWMAOutPin" but it doesn't work anyway. From this I make a conclusion from that the problem doesn't related to the free part of crystal but more related to the constraints.
What I understand (correct me if I wrong) all other modules are working on 100 MHz frequency, but PWM is working on 200 MHz, it is my "CLK" net and it somehow should be available to the the PWM but it doesn't.
I will appreciate for the possible suggestions.
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01 Apr 2024 03:09 #297326
by cornholio
Replied by cornholio on topic RV901T as MESA 7i90: Custom bitstream generation with PWMTag leads to error
I think the issue is a "banking issue".
I'd try moving the PWM pin to a pin on the same bank as the clk pin.
I had this issue when first working with SPI.
The attached file has the Pin Locations to banks.
This is just a guess based on the issues I had when first working with SPI on a dev board, but I haven't seen it when building with PWM.
Pete will have the right fix for sure.
I'd try moving the PWM pin to a pin on the same bank as the clk pin.
I had this issue when first working with SPI.
The attached file has the Pin Locations to banks.
This is just a guess based on the issues I had when first working with SPI on a dev board, but I haven't seen it when building with PWM.
Pete will have the right fix for sure.
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01 Apr 2024 03:12 #297328
by tommylight
Replied by tommylight on topic RV901T as MESA 7i90: Custom bitstream generation with PWMTag leads to error
I am failing to see how this is a LinuxCNC question or issue ?!?!
Probably should be in "computers and hardware as it is for RPI ...
Probably should be in "computers and hardware as it is for RPI ...
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01 Apr 2024 03:22 #297332
by PCW
Replied by PCW on topic RV901T as MESA 7i90: Custom bitstream generation with PWMTag leads to error
Unroutable Placement! A clock IOB / BUFIO clock component pair have been found that are not
placed at a routable clock IOB / BUFIO site pair. The clock IOB component <CLK> is placed at site
<M9>. The BUFIO component <SP6_BUFIO_INSERT_ML_BUFIO2_1> is placed at site <BUFIO2_X4Y21>
This looks to me to possibly be a .ucf file pinout error (an actual clock input is not placed at a
physical GCLK pin)
This could be the main clock or the SPI clock input on the host interface (it may also be an
error in the clock multiplier setup)
placed at a routable clock IOB / BUFIO site pair. The clock IOB component <CLK> is placed at site
<M9>. The BUFIO component <SP6_BUFIO_INSERT_ML_BUFIO2_1> is placed at site <BUFIO2_X4Y21>
This looks to me to possibly be a .ucf file pinout error (an actual clock input is not placed at a
physical GCLK pin)
This could be the main clock or the SPI clock input on the host interface (it may also be an
error in the clock multiplier setup)
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01 Apr 2024 03:42 #297335
by cornholio
Maybe "Driver Boards" would be the most appropriate section, as thta is what we are discussing. And the OP orignal thread as well.
Honestly I not too sure why another topic was need, it's all to do with getting hostmot2 firmware going on another board.
Replied by cornholio on topic RV901T as MESA 7i90: Custom bitstream generation with PWMTag leads to error
I am failing to see how this is a LinuxCNC question or issue ?!?!
Probably should be in "computers and hardware as it is for RPI ...
Maybe "Driver Boards" would be the most appropriate section, as thta is what we are discussing. And the OP orignal thread as well.
Honestly I not too sure why another topic was need, it's all to do with getting hostmot2 firmware going on another board.
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01 Apr 2024 03:48 #297336
by cornholio
The clock in on this pin.
M9 2 BR IO_L29P_GCLK3_2
I can confirm it works, twas fine when meddling with the Smart Serial stuff.
I got that message, similar anyways, when I was trying to get the SPI firmware going. After some digging, trying to understand the Xlilinx data sheets, I came to the conclusion that I need the SPI_COMM pins in the same bank as the clk on the dev board I was using. I can't say I saw the same issue with PWM but maybe I was just lucky with my choice of pins.
Replied by cornholio on topic RV901T as MESA 7i90: Custom bitstream generation with PWMTag leads to error
Unroutable Placement! A clock IOB / BUFIO clock component pair have been found that are not
placed at a routable clock IOB / BUFIO site pair. The clock IOB component <CLK> is placed at site
<M9>. The BUFIO component <SP6_BUFIO_INSERT_ML_BUFIO2_1> is placed at site <BUFIO2_X4Y21>
This looks to me to possibly be a .ucf file pinout error (an actual clock input is not placed at a
physical GCLK pin)
This could be the main clock or the SPI clock input on the host interface (it may also be an
error in the clock multiplier setup)
The clock in on this pin.
M9 2 BR IO_L29P_GCLK3_2
I can confirm it works, twas fine when meddling with the Smart Serial stuff.
I got that message, similar anyways, when I was trying to get the SPI firmware going. After some digging, trying to understand the Xlilinx data sheets, I came to the conclusion that I need the SPI_COMM pins in the same bank as the clk on the dev board I was using. I can't say I saw the same issue with PWM but maybe I was just lucky with my choice of pins.
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01 Apr 2024 07:12 - 01 Apr 2024 07:12 #297342
by ago_tm
Replied by ago_tm on topic RV901T as MESA 7i90: Custom bitstream generation with PWMTag leads to error
Hello guys,
I am very sorry, you are right - my questions are more about the hardware for linuxcnc, but not the linuxcnc itself.
I will appreciate if you could help me to move this thread to the corresponding topic (if it is possible).
From my side I promise to be more accurate in future.
I am failing to see how this is a LinuxCNC question or issue ?!?!
Probably should be in "computers and hardware as it is for RPI ...
I am very sorry, you are right - my questions are more about the hardware for linuxcnc, but not the linuxcnc itself.
I will appreciate if you could help me to move this thread to the corresponding topic (if it is possible).
From my side I promise to be more accurate in future.
Last edit: 01 Apr 2024 07:12 by ago_tm.
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01 Apr 2024 11:50 #297360
by tommylight
Replied by tommylight on topic RV901T as MESA 7i90: Custom bitstream generation with PWMTag leads to error
Moving stuff is easy, so no need to be sorry at all.
Double posting the same subject makes a mess for whoever is trying to help.
I will move this later, as i am on the phone.
Thank you.
Double posting the same subject makes a mess for whoever is trying to help.
I will move this later, as i am on the phone.
Thank you.
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01 Apr 2024 12:30 #297364
by tommylight
Replied by tommylight on topic RV901T as MESA 7i90: Custom bitstream generation with PWMTag leads to error
Moved to "driver boards".
Thank you.
Thank you.
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03 Apr 2024 19:37 - 03 Apr 2024 19:38 #297530
by ago_tm
Replied by ago_tm on topic RV901T as MESA 7i90: Custom bitstream generation with PWMTag leads to error
Hello guys,
I still trying the find a possible solution for my issue.
I do not have hard skills in fpga but I am trying to dig it deeper and will appreciate if you could help me with understanding when there is a mistake in my conclusions.
As I said before enabling of at least the only PWM out leads to error I will focus on the single pin PWMAOutPin
According to the error message and your help I see that the problem is in different sites used for PWM module clocking and the component "SP6_BUFIO_INSERT_ML_BUFIO2_1".
First problem is that I do not understand what the component it is... It looks like some kind of implicitly named component of the design. I just assume that it is something related to the PWM module.
In TopGCSPIHostMot2.vhd line 306 I found the confirmation that the PWM clock frequency should be 200 MHz:
fclk is the output of the BUFG_inst0 where the input is clkfx0, which is CLKFX endpoint of ClockMultH digital clock manager, which is
So it looks like the truth: PWM module depends on the CLK which is package pin M9 and in PlanAhead I see for it:
As I also see: clock region X1Y0 is the bottom right part of the crystal.
In UG382 I found that BUFIO2_X4Y21 is related to Bank 1:
I understand that I need to somehow create a LOC constraint.
In the Constraints Guide I found the following example:
But I do not know what it means "SP6_BUFIO_INSERT_ML_BUFIO2_1"? I can't find anything with that name in PlanAhead. If it is a primitive, how can I find it?
What location should be in my case - some free BIOB_ from clock region X1Y0, for example BIOB_SINGLE_X13Y0 or BIOB_X15Y0?
I will appreciate the further help.
I still trying the find a possible solution for my issue.
I do not have hard skills in fpga but I am trying to dig it deeper and will appreciate if you could help me with understanding when there is a mistake in my conclusions.
As I said before enabling of at least the only PWM out leads to error I will focus on the single pin PWMAOutPin
IOPortTag & x"00" & PWMTag & PWMAOutPin, -- I/O 0 PWM OUTAccording to the error message and your help I see that the problem is in different sites used for PWM module clocking and the component "SP6_BUFIO_INSERT_ML_BUFIO2_1".
First problem is that I do not understand what the component it is... It looks like some kind of implicitly named component of the design. I just assume that it is something related to the PWM module.
In TopGCSPIHostMot2.vhd line 306 I found the confirmation that the PWM clock frequency should be 200 MHz:
clkhigh => fclk, -- PWM clockfclk is the output of the BUFG_inst0 where the input is clkfx0, which is CLKFX endpoint of ClockMultH digital clock manager, which is
Oscillator's CLK (25) MHz * CLKFX_MULTIPLY (16) / CLKFX_DIVIDE (2) = 200 MHzSo it looks like the truth: PWM module depends on the CLK which is package pin M9 and in PlanAhead I see for it:
Instance: CLK_IBUFG
Net: CLK
Package pin: M9
Site type: IO_L29P_GCLK3_2
Bank: I/O Bank: 2 (Standard)
Tile: BIOB_X12Y0
Clock region: X1Y0As I also see: clock region X1Y0 is the bottom right part of the crystal.
In UG382 I found that BUFIO2_X4Y21 is related to Bank 1:
GCLK_10 <BUFIO2_X4Y21>
GCLK_6 <BUFIO2_X4Y21>I understand that I need to somehow create a LOC constraint.
In the Constraints Guide I found the following example:
INST “instance_name ” LOC=location;But I do not know what it means "SP6_BUFIO_INSERT_ML_BUFIO2_1"? I can't find anything with that name in PlanAhead. If it is a primitive, how can I find it?
What location should be in my case - some free BIOB_ from clock region X1Y0, for example BIOB_SINGLE_X13Y0 or BIOB_X15Y0?
I will appreciate the further help.
Last edit: 03 Apr 2024 19:38 by ago_tm.
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