tb6560ahq board

hallo!
does anyone know the right steplen, stepspace, dirsetup, dirhold of the cheap TB6560AHQ drive that can be found on the bay?

tried again to read and read again the pdf of the specification, but couldn't understand the right timings to setup emc.
right now i played a lot with this driver, but still don't know if i set it up correctly!
anyone know how to know the correct timings?

thanks, dab.

In the 6560AHQ data sheet I found only two important timings:
max clock frequency = 15 kHz
min clock puls width = 30 usec

But there is also a dependency from the internal chip clock and its corresponding capacitor, which is not precisely discovered.

From this values you should be on the safe side in any case with steplen = 30000.
From my own experiences a 6560AHQ in my own board (no opto) works reliable also with 20 usec and even less, but it does definitely not work with 5 usec, which is the default for stepconf. This is what you have to change in stepconf.

If you edit hal directly: remove the reset function of the puls pins and limit the stepping frequ to 15 kHz, then it should work.

All other settings I took from stepconf defaults, and I have not found any issue up to now.

Gerd

ok.
i'have read about the capacitor, but i'm not able to recognize which one is on the drive. (the normal or miniaturized?)
one strange thing is that if i use step conf, without touching anything it propose:
ST: 5000ns
SS: 5000
DH: 20000
DS: 20000

but, in my .hal file i read for each motor:
Slen: 1
SS: 0
DH: 30000
DS: 30000

there is something i don't understand, or it's an issue of stepconf?

thanks for helping, in the meanwhile i try with the values you suggest.

EDIT: i also add that with the latency test my max jitter doesn't go over 9000ns.. i think that's good!

if anyone can tell, these are my capacitors (those repeated per channel)

then, on the chip specs i've found this:
Capacitor / Oscillating Frequency / Minimum Clock Pulse Width tW(CLK) (Note 1)
1000 pF 44 kHz 90 μs (Note 2)
330 pF 130 kHz 30 μs
100 pF 400 kHz 10 μs (Note 2)

so it's probably the 470 capacitor on the driver the one we are talking of.
so i can suppose a minimum clock pulse of around 40μs...

can it be right?

For details about the stepgen parameters see:

www.linuxcnc.org/docview/html/man/man9/stepgen.9.html

Although I agree, some values seems strange. But I do not have an explanation for it.
May there is an expert to give us explanations.
Edit: I think that the hal entry of setup and hold times is the time you entered in stepconf plus the latency time.

Consider also the difference of pulse genration using reset function or not.

yes, i've tryied as you suggested to comment the lines with the reset instructions, but i didn't see any difference in moving.
about setup and hold times you are right.

understand why, but how to invert the step signals?

since by eyes and ear i can't see differences with or without the resets, where should i see improvements? in the reading of the feedback error? max speed?

dab77 wrote:

since by eyes and ear i can't see differences with or without the resets, where should i see improvements? in the reading of the feedback error? max speed?

If it works with reset its fine.
My 6560 board did not work with reset = 5000, 5 usec is too short for that device.
And I think its not a good idea to extend the reset too much.
Not sure how the real time part deals with it, but my feeling says it would borrow some cpu power.

Gerd