Laser control via 7i76e - PPI / PPMM / PWM

Basicaly it goes like this
Net some_signal_name some_function_or_pin some_other_function_or_pin
Some signal name can be any name you like laser_power
Some function or pin has to be something that exists in hal, like pwm_output
Some other function or pin is something that exists in hal to be connected to the above, like parport_pin_7 to be connected to the above pwm_output.

That seems to be my stumbling block... how does parport_pin_7 equate to 7i76e_expansion_port_pin_1?

I've seen the convention of a single reference i.e. hm2_7i76e.0.stepgen...

and the convention of a double reference i.e. hm2_7i76e.0.7i76.0.0.output...

And for the life of me I can't find info about 'wiring' a hal pin to an expansion port pin

7i76e manual has them listed, but they can change with different firmware.
Use mesaflash to list the pins.

SjCNC wrote: That seems to be my stumbling block... how does parport_pin_7 equate to 7i76e_expansion_port_pin_1?

For simple I/O the parallel port pins map to GPIO pins.
The correspondence of parallel port pins/connectors to
GPIO hal pins is as tommylight indicated, listed by the mesaflash utility:

I've seen the convention of a single reference i.e. hm2_7i76e.0.stepgen...

and the convention of a double reference i.e. hm2_7i76e.0.7i76.0.0.output...

These references are different because the first refers to hardware (a stepgen)
in the 7I76Es FPGA, but the second refers to a connected SSerial device
(the isolated field I/O section) For example, if you had a 7I73 control panel
interface connected to the 7I76E's SSerial expansion connector, you would have pins like:

hm2_7i76e.0.7i73.0.1.enc0

Full output follows, but PWM lines are here at the top

Pin# I/O Pri. func Sec. func Chan
5 25 IOPort PWM 0 PWM (Out)
6 26 IOPort PWM 0 /Enable (Out)
7 27 IOPort PWM 0 Dir (Out)

So would this be pin 5 at the FPGA?

Would I/O 25 be expansion port 1, HDR pin 09?

I'm basing that assumption on the manual, page 7 or 13/86

HDR PIN P1 Func P2 FUNC

9 IO25 IO42



shawn@hptc:~/Documents/7i76eFW$ mesaflash --device 7i76e --addr 10.10.10.10 --readhmid
Configuration Name: HOSTMOT2

General configuration information:

BoardName : MESA7I76
FPGA Size: 16 KGates
FPGA Pins: 256
Number of IO Ports: 3
Width of one I/O port: 17
Clock Low frequency: 100.0000 MHz
Clock High frequency: 200.0000 MHz
IDROM Type: 3
Instance Stride 0: 4
Instance Stride 1: 64
Register Stride 0: 256
Register Stride 1: 256

Modules in configuration:

Module: DPLL
There are 1 of DPLL in configuration
Version: 0
Registers: 7
BaseAddress: 7000
ClockFrequency: 100.000 MHz
Register Stride: 256 bytes
Instance Stride: 4 bytes

Module: WatchDog
There are 1 of WatchDog in configuration
Version: 0
Registers: 3
BaseAddress: 0C00
ClockFrequency: 100.000 MHz
Register Stride: 256 bytes
Instance Stride: 4 bytes

Module: IOPort
There are 3 of IOPort in configuration
Version: 0
Registers: 5
BaseAddress: 1000
ClockFrequency: 100.000 MHz
Register Stride: 256 bytes
Instance Stride: 4 bytes

Module: PWM
There are 1 of PWM in configuration
Version: 0
Registers: 5
BaseAddress: 4100
ClockFrequency: 200.000 MHz
Register Stride: 256 bytes
Instance Stride: 4 bytes

Module: StepGen
There are 9 of StepGen in configuration
Version: 2
Registers: 10
BaseAddress: 2000
ClockFrequency: 100.000 MHz
Register Stride: 256 bytes
Instance Stride: 4 bytes

Module: QCount
There are 2 of QCount in configuration
Version: 2
Registers: 5
BaseAddress: 3000
ClockFrequency: 100.000 MHz
Register Stride: 256 bytes
Instance Stride: 4 bytes

Module: SSerial
There are 1 of SSerial in configuration
Version: 0
Registers: 6
BaseAddress: 5B00
ClockFrequency: 100.000 MHz
Register Stride: 256 bytes
Instance Stride: 64 bytes

Module: LED
There are 1 of LED in configuration
Version: 0
Registers: 1
BaseAddress: 0200
ClockFrequency: 100.000 MHz
Register Stride: 256 bytes
Instance Stride: 4 bytes

Configuration pin-out:
IO Connections for on-card
Pin# I/O Pri. Func Sec. Func Chan Pin func Pin Dir

1 0 IOPort StepGen 0 Dir/Table2 (Out)
14 1 IOPort StepGen 0 Step/Table1 (Out)
2 2 IOPort StepGen 1 Dir/Table2 (Out)
15 3 IOPort StepGen 1 Step/Table1 (Out)
3 4 IOPort StepGen 2 Dir/Table2 (Out)
16 5 IOPort StepGen 2 Step/Table1 (Out)
4 6 IOPort StepGen 3 Dir/Table2 (Out)
17 7 IOPort StepGen 3 Step/Table1 (Out)
5 8 IOPort StepGen 4 Dir/Table2 (Out)
6 9 IOPort StepGen 4 Step/Table1 (Out)
7 10 IOPort Sserial 0 TXData0 (Out)
8 11 IOPort Sserial 0 RXData0 (In)
9 12 IOPort Sserial 0 TXData1 (Out)
10 13 IOPort Sserial 0 RXData1 (In)
11 14 IOPort Qcount 0 Quad-IDX (In)
12 15 IOPort Qcount 0 Quad-B (In)
13 16 IOPort Qcount 0 Quad-A (In)

IO Connections for P1
Pin# I/O Pri. func Sec. func Chan Pin func Pin Dir

1 17 IOPort StepGen 5 Dir/Table2 (Out)
14 18 IOPort StepGen 5 Step/Table1 (Out)
2 19 IOPort StepGen 6 Dir/Table2 (Out)
15 20 IOPort StepGen 6 Step/Table1 (Out)
3 21 IOPort StepGen 7 Dir/Table2 (Out)
16 22 IOPort StepGen 7 Step/Table1 (Out)
4 23 IOPort StepGen 8 Dir/Table2 (Out)
17 24 IOPort StepGen 8 Step/Table1 (Out)
5 25 IOPort PWM 0 PWM (Out)
6 26 IOPort PWM 0 /Enable (Out)
7 27 IOPort PWM 0 Dir (Out)
8 28 IOPort SSerial 0 TXData2 (Out)
9 29 IOPort SSerial 0 TXEn2 (Out)
10 30 IOPort SSerial 0 RXData2 (In)
11 31 IOPort QCount 1 Quad-IDX (In)
12 32 IOPort QCount 1 Quad-B (In)
13 33 IOPort QCount 1 Quad-A (In)









IO Connections for P2
Pin# I/O Pri. func Sec. func Chan Pin func Pin Dir

1 34 IOPort None
14 35 IOPort None
2 36 IOPort None
15 37 IOPort None
3 38 IOPort None
16 39 IOPort None
4 40 IOPort None
17 41 IOPort None
5 42 IOPort None
6 43 IOPort None
7 44 IOPort None
8 45 IOPort None
9 46 IOPort None
10 47 IOPort None
11 48 IOPort None
12 49 IOPort None
13 50 IOPort None

That would be pin 5 at the DB25 connector on the P1 header.