5i24+7i52s problem with Stepgen 00 and 03

i have an 5i24 and a 7I52s, and i can only get 4 out of the six stepgens to output steps. the same stepper motor works if i move it to the other ports. maybe i loaded the wrong firmware, also want to use a 7i44 on the 5i24. the 7i52 is on the p2 connector (closest to the Motherboard) and the 7i44 is on the p4 connector. i have all the encoders turned off for now but would like to use a few in the future. the machine is a small robot arm so i need at least 5 stepgens, but it is not a prodution machine so mainly for fun

thanks Jonathan Decker

Configuration Name: HOSTMOT2

General configuration information:

BoardName : MESA5I24
FPGA Size: 25 KGates
FPGA Pins: 256
Number of IO Ports: 3
Width of one I/O port: 24
Clock Low frequency: 33.3333 MHz
Clock High frequency: 200.0000 MHz
IDROM Type: 3
Instance Stride 0: 4
Instance Stride 1: 64
Register Stride 0: 256
Register Stride 1: 256

Modules in configuration:

Module: WatchDog
There are 1 of WatchDog in configuration
Version: 0
Registers: 3
BaseAddress: 0C00
ClockFrequency: 33.333 MHz
Register Stride: 256 bytes
Instance Stride: 4 bytes

Module: IOPort
There are 3 of IOPort in configuration
Version: 0
Registers: 5
BaseAddress: 1000
ClockFrequency: 33.333 MHz
Register Stride: 256 bytes
Instance Stride: 4 bytes

Module: MuxedQCount
There are 6 of MuxedQCount in configuration
Version: 3
Registers: 5
BaseAddress: 3600
ClockFrequency: 33.333 MHz
Register Stride: 256 bytes
Instance Stride: 4 bytes

Module: MuxedQCountSel
There are 1 of MuxedQCountSel in configuration
Version: 0
Registers: 0
BaseAddress: 0000
ClockFrequency: 33.333 MHz
Register Stride: 256 bytes
Instance Stride: 4 bytes

Module: StepGen
There are 6 of StepGen in configuration
Version: 2
Registers: 10
BaseAddress: 2000
ClockFrequency: 33.333 MHz
Register Stride: 256 bytes
Instance Stride: 4 bytes

Module: LED
There are 1 of LED in configuration
Version: 0
Registers: 1
BaseAddress: 0200
ClockFrequency: 33.333 MHz
Register Stride: 256 bytes
Instance Stride: 4 bytes

Configuration pin-out:

IO Connections for P4
Pin# I/O Pri. func Sec. func Chan Sec. Pin func Sec. Pin Dir

1 0 IOPort None
3 1 IOPort MuxedQCount 0 MuxQ-A (In)
5 2 IOPort MuxedQCount 0 MuxQ-B (In)
7 3 IOPort MuxedQCount 0 MuxQ-IDX (In)
9 4 IOPort MuxedQCount 1 MuxQ-A (In)
11 5 IOPort MuxedQCount 1 MuxQ-B (In)
13 6 IOPort MuxedQCount 1 MuxQ-IDX (In)
15 7 IOPort MuxedQCount 2 MuxQ-A (In)
17 8 IOPort MuxedQCount 2 MuxQ-B (In)
19 9 IOPort MuxedQCount 2 MuxQ-IDX (In)
21 10 IOPort MuxedQCountSel 0 MuxSel0 (Out)
23 11 IOPort StepGen 5 Step/Table1 (Out)
25 12 IOPort StepGen 5 Dir/Table2 (Out)
27 13 IOPort StepGen 4 Step/Table1 (Out)
29 14 IOPort StepGen 4 Dir/Table2 (Out)
31 15 IOPort StepGen 3 Step/Table1 (Out)
33 16 IOPort StepGen 3 Dir/Table2 (Out)
35 17 IOPort StepGen 2 Step/Table1 (Out)
37 18 IOPort StepGen 2 Dir/Table2 (Out)
39 19 IOPort StepGen 1 Step/Table1 (Out)
41 20 IOPort StepGen 1 Dir/Table2 (Out)
43 21 IOPort StepGen 0 Step/Table1 (Out)
45 22 IOPort StepGen 0 Dir/Table2 (Out)
47 23 IOPort None

IO Connections for P3
Pin# I/O Pri. func Sec. func Chan Sec. Pin func Sec. Pin Dir

1 24 IOPort None
3 25 IOPort None
5 26 IOPort None
7 27 IOPort None
9 28 IOPort None
11 29 IOPort None
13 30 IOPort None
15 31 IOPort None
17 32 IOPort None
19 33 IOPort None
21 34 IOPort None
23 35 IOPort None
25 36 IOPort None
27 37 IOPort None
29 38 IOPort None
31 39 IOPort None
33 40 IOPort None
35 41 IOPort None
37 42 IOPort None
39 43 IOPort None
41 44 IOPort None
43 45 IOPort None
45 46 IOPort None
47 47 IOPort None

IO Connections for P2
Pin# I/O Pri. func Sec. func Chan Sec. Pin func Sec. Pin Dir

1 48 IOPort None
3 49 IOPort None
5 50 IOPort None
7 51 IOPort None
9 52 IOPort None
11 53 IOPort None
13 54 IOPort None
15 55 IOPort None
17 56 IOPort None
19 57 IOPort None
21 58 IOPort None
23 59 IOPort None
25 60 IOPort None
27 61 IOPort None
29 62 IOPort None
31 63 IOPort None
33 64 IOPort None
35 65 IOPort None
37 66 IOPort None
39 67 IOPort None
41 68 IOPort None
43 69 IOPort None
45 70 IOPort None
47 71 IOPort None

You need to set GPIO 0 and GPIO 47 low
(7I52S manual page 10)

when i look in the show config it says both hm2_5i24.0.gpio.000.out and .047.out are false, 000.in and 047.in are true but not writable

page 10 say "To enable outputs TX0B and /TX0B, /TX0BENA must be driven low by the FPGA" and on page four says "47 (is) /TX0BENA TO 7I52S" and "43 (is) TX0B TO 7I52S", /TX0B isnt listed i assume it is the grounded pin so always low, or there is a not gate on 43 but then i would not be able to drive it low also

so guessing this would look like
setp hm2_5i24.0.gpio.043.out false
setp hm2_5i24.0.gpio.047.out true

setting them in the show config doesn't enable the drive

i got to stop reading manuals when im tired. to enable tx0B and /tx0B drive /TX0BENA Low. that makes a lot more sense but still didn't work

GPIO pins need to be set to output mode if used as outputs
(all GPIO defaults to input mode)

Something like:

setp hm2_5i24.0.gpio.043.is_output true
setp hm2_5i24.0.gpio.047.is_output true
setp hm2_5i24.0.gpio.043.out false
setp hm2_5i24.0.gpio.047.out false

(the last 2 statements are actually redundant because the output latches default to the low state)

that makes way more sense but still doesn't move the motor,

hum guess i can still test with the 4 drives and i do have a second 7i52s board if it come to it

That setup is necessary, but you may have other setup that needs to be done.

An easy way to verify the step/dir pins is to toggle the invert parameters for the
specific step/dir outputs of interest, say:

hm2_5i24.0.stepgen.03.step.invert_output

And check that the associated pin changes.

Note that you can get a 7I52S pinout of your current configuration with:

sudo mesaflash --device 5i24 --dbname1 7i52s --readhmid

(assuming you have a fairly recent version of mesaflash installed)

that did it thank you.