Biased PWM configuration

Hello,

I am configurring Mesa 5I20 board to work with Granite Devices VSD-E board. From VSD-E documentation and help from Tero I learned the following:

In VSD PWM input to commanded velocity goes as follows:

0% duty = -100% speed or torque
50% duty = 0 speed or torque
100% duty = +100% speed or torque

the relation is linear. You can interpolate this list:
0% duty = -100% speed or torque
25% duty = -50% speed or torque
50% duty = 0 speed or torque
75% duty = +50% speed or torque
100% duty = +100% speed or torque

There is paramter called pid.N.bias that may do the trick.

Please help me with the proper configuration of HOSTMOT2 and PID bias parameter to be able to drive VSE-E up-down.

Thenk you for your help,

Regards Bojan

Just occurred to me that you can also use the three phase PWM generator for biased (locked-antiphase)
PWM as it does this inherently, so no comp needed.

andypugh wrote:

boyzo wrote:

0% duty = -100% speed or torque
50% duty = 0 speed or torque
100% duty = +100% speed or torque

Setting the bias parameter to half the scale should do what you want. However, biased PWM isn't inherently very safe, as the drives will tend to run away if there is no PWM. It is entirely possible that the drives are configured such that they stop with no actual PWM input.

From VSD manual:
"0% and 100% duty cycles are theoretical references only and in practice cannot be used. Drive sets output command value to zero if PWM input is not detected (i.e. no logic transitions pass through optoisolator). To stay in valid duty cycle range, limiting input to 5%...95% range is recommended."

So it shouldn't be a problem.

From Manual pages Hostmot2 HAL Component pwmgen there's this info:
( buildbot.linuxcnc.org/doc/v2.5_branch/v2...MC2_Manual_Pages.pdf page 151/246)
(s32 rw) output-type: This emulates the output_type load-time argument to the software pwmgen component. This parameter may be changed at runtime, but most of the time you probably want to set it at startup and then leave italone. Accepted values are 1 (PWM on Out0 and Direction on Out1), 2 (Up on Out0 and Down on Out1), 3 (PDM mode, PDM on Out0 and Dir on Out1), and 4 (Direction on Out0 and PWM on Out1, "for locked antiphase").

Any idea how that mode 4 would work? I shouldn't need DIR at Out0? Couldn't find too much info about it and I'm not very familiar with this biased PWM / "locked antiphase"-thing..

I think I wouldn't be very convenient to use 3ppwmgen (outputs PWM A, PWM B, PWM C, /PWM A, /PWM B, /PWM C, Enable. The ?rst three pins are the high side drivers, the second three are their complementary low-side driver) and only use PWM A (and enable)?

To do locked antiphase with the standard PWMGEN you must add an offset component to the PID output (so you get 50% PWM with 0 error)

So if for simplicity we scale the PWM generator in percent (PWM scale set to 100), we would set the PID max output value to 45, and then use the offset component
to add 50 to the PID component output before wiring it to the PWM generator.

Now we get the desired PWM behaviour (50% duty cycle when no PID error and 5% and 95% bounds on PWM duty cycle)

The three phase PWM gen driver does the offset by itself but it will waste more hardware in the FPGA than the standard PWMGEN and has lower resolution (10 bits vs 12). The actual pinout is no problem, you just use the pins you need and the synthesiser will delete most of the unused hardware. I do think the standard PWMGEN with the offset comp is probably a better solution however (until there is driver support for locked antiphase)

Another slightly off-the-wall suggestion is to hack the PID comp so that the PID comps BIAS parameter is added after the bounding (currently its done before the bounding so cannot be used for locked antiphase offset purposes)

So should I use output-type 1 or 4?

1, mode 4 is just for our HBridge cards

PCW wrote:

To do locked antiphase with the standard PWMGEN you must add an offset component to the PID output (so you get 50% PWM with 0 error)

So if for simplicity we scale the PWM generator in percent (PWM scale set to 100), we would set the PID max output value to 45, and then use the offset component
to add 50 to the PID component output before wiring it to the PWM generator.

Now we get the desired PWM behaviour (50% duty cycle when no PID error and 5% and 95% bounds on PWM duty cycle)

The three phase PWM gen driver does the offset by itself but it will waste more hardware in the FPGA than the standard PWMGEN and has lower resolution (10 bits vs 12). The actual pinout is no problem, you just use the pins you need and the synthesiser will delete most of the unused hardware. I do think the standard PWMGEN with the offset comp is probably a better solution however (until there is driver support for locked antiphase)

Another slightly off-the-wall suggestion is to hack the PID comp so that the PID comps BIAS parameter is added after the bounding (currently its done before the bounding so cannot be used for locked antiphase offset purposes)

Hello,

Is there any new development in native support for locked antiphase PWMGEN?

Thanks B.

Not that I know of. Since its seems like a fairly uncommon option, using the offset component
probably makes the most sense.