bidirectional pins / HAL_IO

I'm trying to understand how to use i/o pins.

Assuming
    a.io is an i/o pin
    b.out is an out pin

Is it possible to drive a.io with b.out with a regular interconnection via a signal?

net sig <= b.out => a.io
   fails complaining that sig already has an out pin connected. So the 'out' portion of the i/o-pin is considered.

net sig a.io
sets sig 1
   works although I would have assumed it should fail because the docs state ("sets ... fails if ... it already has a writer") and in the previous example the 'writer' character of the i/o pin collided with b.out.

So is the consequence that the 'in' portion of an i/o-pin is only usable programmatically or with sets/gets/setp/getp and not by regular 'neting'?
What's the idea behind i/o-pins and when does it make sense to give a component an i/o-pin?

Please enlighten me

 

I would guess sets allows setting I/O pins for convenience.
(Think of sets as having I/O pin characteristics)

I/O pins are used for handshakes in some circumstances
(index enable is one example that comes to mind)

Index-enable is set by motion and cleared by the encoder hardware

I actually think it would have been better to not use an I/O pin and use
a 2 wire handshake instead for this but its a bit late for that...

The situation basically is as follows:
Component a
    has a physical control for a value v
    on an internal change of v writes v to a.io
    on an external modification of a.io calculates v=f(a.io) and writes v to a.io

Component b
    has a physical control whose value is readable on b.out
    has a physical display showing the value of b.in

So the idea - which of course fails - would be to net a and b this way
    net b-control <= b.out => a.io
    net b-display <= a.io  => b.in

Not sure how to solve it with tristate.
net sig <= tristate-bit.0.out => a.io would lead again to more than one out pin on sig, wouldn't it?

To be clear - this is more about learning more about hal than anything else.
Thus the question regarding how and in which use case i/o pins are useful considering the logical one-input-only restriction on signals.

 

net sig <= tristate-bit.0.out => a.io would lead again to more than one out pin on sig, wouldn't it?

No, because tristate-bit.0.out is an I/O pin

Okay - that's the missing piece of the puzzle.
So any number of i/o pins can be connected to a single signal and the values stay synchronized.
Thank you guys!