Mesa programming and relationship with HAL

I watched the series of HAL videos by Feral Engineer, and learned enough to implement my first logic gate in HAL... baby steps.

My understanding is that most and perhaps all? of the logic running in the FPGA on the Mesa board is pre-programmed and the HAL file just defines the links between the various pre-programmed blocks within the FPGA and LinuxCNC?

Now if I come along and add say 10 AND gates to the servo thread using HAL, do those 10 AND gates get implemented in the FPGA or are those 10 AND gates implemented as code that gets executed sequentially by Linux as part of the servo thread that I assume gets called by LinuxCNC probably via an IRQ based on the servo thread interrupt rate.

If implemented as logic in the FPGA I would expect adding a lot of logic would have very little impact on the CPU running LinuxCNC, however if implemented as code to be executed by the LinuxCNC CPU it could start to add up and effect latency.

Can anyone shed any light on the subject?

 

The only thing in hal that affects how the FPGA runs is the hm2_eth (assuming you are using an ethernet based mesa card) component.

Here is the snippet from a HAL file of mine:

loadrt hm2_eth board_ip="10.10.10.10" config="num_encoders=1 num_pwmgens=1 num_stepgens=5 sserial_port_1=11xxxxxx"
setp [HMOT](CARD0).pwmgen.pwm_frequency 20000
setp [HMOT](CARD0).pwmgen.pdm_frequency 6000000
setp [HMOT](CARD0).watchdog.timeout_ns 5000000

In my case, I have 1 encoder, 1 pwmgen, 5 stepgens and a couple serial connections that are all running on the Mesa card. Everything else is all stuff that runs on the PC. Provided you aren't doing anything crazy, I wouldn't worry about performance. All the I/O connections in your HAL file are updated at the speed of your servo thread.

Your intuition is spot on. The FPGA has hard-coded modules like stepgens and pwmgens that can be configured/used (or not), but any custom logic you add to HAL runs on the main CPU. So yes, you do have to think about the code you throw there. A couple AND gates will make no big difference, but it does add serialized computation exactly as you suspected, i.e., it does not get "moved" into the FPGA.