mesa 5i20 and DAC

Also RDY polarity must be reversed as well
because your buffer would be disabled during
the transfer if active high as shown in the chart

The DAC is not directly accessible by the mesa board. The DAC is controlled via SPI by a micro-controller I will program.
As I was focused on designing the hardware, I brewed this temporary protocol however I agree with you about using standard hand-shaking protocol.

I just reversed RDY because your schematic showed the '541 buffer which needs an active low /RDY
to enable the data to the rest of the circuit

So I have an example bitfile with these minor changes
1. Active low ready = /RDY
2. MSB flag is high for MSB (MSB sent first)

to test you will need to

1. Enable the output bits (this you can do in HAL)
2 Select alternate source for output bits of twiddler module (this you must use raw-write to 0x1204) data is 0xFFC000
3. To output data you write your 16 bit data to 0x4e00. This will start the handshaking scheme

once handshaking is started, the firmware waits for low /RDY then outputs and strobes MSB with MSB flag high
the firmware then waits for /RDY high then /RDY low. It then outputs and strobes the LSB data with MSB flag low.
The firmware the waits for /RDY high before being ready for the next cycle, started by the next host write to 0x4e00

5I20 bitfile, pinfile, and twiddle module assy source: freeby.mesanet.com/4110.ZIP

Note that the firmware puts debug codes in the dual ported HM2 RAM (read at 0x4E00)
so you can trace the handshake progress

Thank you!!!
Unfortunately I will be busy this month.
I hope to work on my milling machine in July.
I will let you know about my progress.
Cheers, Dom