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hm2/hm2_5i23.0: unknown stepgen MD:

  • jCandlish
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22 May 2013 23:33 - 22 May 2013 23:37 #34553 by jCandlish
Replied by jCandlish on topic hm2/hm2_5i23.0: unknown stepgen MD:

AUX is just the 7I47 output name for the extra isolated output. In your bitfile its just IO16 so will be GPIO16 in HAL. As cncbasher mentioned, the DIR and enable signals are part of the PWMGEN module so are not available as pins (they could be available as GPIO if the pin file was changed to just have GPIO on those pins)


AUX and DIR are sorted. I was thinking more about ENA and the line
net machine-is-enabled => hm2_5i23.0.pwmgen.00.enable

I am assuming that 'machine-is-enabled' turns on the ENA optoisolator and enables the PWM. I have the ENA optoisolator switching a relay coil that in turn switches a pair on NC contacts in the e-stop loop. I would like to know more about the logic of 'machine-is-enabled'.

Or is something like this better?
net my-synthetic-estop => hm2_5i23.0.pwmgen.00.enable

I suspect the pin 62 enumeration issue is something broken in the PINXXXX file


OK. I will check into that. But it is opaque to me. I have attached my PIN file. You can see in that file where I am toggling the StepGenFlag configuration with a comment. Both* versions seem to make the same random gliches. *By both I mean the version as you recommened and a version with x"08" rather than x"0a" for LowClockTag. That was sort of an experiment to try to understand the usage of that value. I couldn't see where you got '0a' from, as there are only 4 step/dirs on the 7i47s.

I am compiling the BIT file with Xilinx92i as documented in the wiki.

library IEEE;
use IEEE.std_logic_1164.all;  -- defines std_logic types
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
-- http://www.mesanet.com
--
-- This program is is licensed under a disjunctive dual license giving you
-- the choice of one of the two following sets of free software/open source
-- licensing terms:
--
--    * GNU General Public License (GPL), version 2.0 or later
--    * 3-clause BSD License
-- 
--
-- The GNU GPL License:
-- 
--     This program is free software; you can redistribute it and/or modify
--     it under the terms of the GNU General Public License as published by
--     the Free Software Foundation; either version 2 of the License, or
--     (at your option) any later version.
-- 
--     This program is distributed in the hope that it will be useful,
--     but WITHOUT ANY WARRANTY; without even the implied warranty of
--     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--     GNU General Public License for more details.
-- 
--     You should have received a copy of the GNU General Public License
--     along with this program; if not, write to the Free Software
--     Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-- 
-- 
-- The 3-clause BSD License:
-- 
--     Redistribution and use in source and binary forms, with or without
--     modification, are permitted provided that the following conditions
--     are met:
-- 
--   * Redistributions of source code must retain the above copyright
--     notice, this list of conditions and the following disclaimer.
-- 
--   * Redistributions in binary form must reproduce the above
--     copyright notice, this list of conditions and the following
--     disclaimer in the documentation and/or other materials
--     provided with the distribution.
-- 
--   * Neither the name of Mesa Electronics nor the names of its
--     contributors may be used to endorse or promote products
--     derived from this software without specific prior written
--     permission.
-- 
-- 
-- Disclaimer:
-- 
--     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
--     "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
--     LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
--     FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
--     COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
--     INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
--     BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
--     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
--     CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
--     LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
--     ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--     POSSIBILITY OF SUCH DAMAGE.
-- 

use work.IDROMConst.all;

package PIN_SVST_FOOBAR is
	constant ModuleID : ModuleIDType :=( 
		(WatchDogTag,	x"00",	ClockLowTag,	x"01",	WatchDogTimeAddr&PadT,	WatchDogNumRegs,	x"00",	WatchDogMPBitMask),
		(IOPortTag,	x"00",	ClockLowTag,	x"03",	PortAddr&PadT,		IOPortNumRegs,		x"00",	IOPortMPBitMask),
		(QcountTag,	x"02",	ClockLowTag,	x"08",	QcounterAddr&PadT,	QCounterNumRegs,	x"00",	QCounterMPBitMask),
		(PWMTag,	x"00",	ClockHighTag,	x"08",	PWMValAddr&PadT,	PWMNumRegs,		x"00",	PWMMPBitMask),
		(StepGenTag,	x"02",	ClockLowTag,	x"08",	StepGenRateAddr&PadT,	StepGenNumRegs,		x"00",	StepGenMPBitMask),
--              (StepGenTag, KUBStepGenRev, ClockLowTag, x"0A", StepGenRateAddr&PadT,   StepGenNumRegs,         x"00",  StepGenMPBitMask),
		(LEDTag,	x"00",	ClockLowTag,	x"01",	LEDAddr&PadT,		LEDNumRegs,		x"00",	LEDMPBitMask),
		(NullTag,	x"00",	NullTag,	x"00",	NullAddr&PadT,		x"00",			x"00",	x"00000000"),
		(NullTag,	x"00",	NullTag,	x"00",	NullAddr&PadT,		x"00",			x"00",	x"00000000"),
		(NullTag,	x"00",	NullTag,	x"00",	NullAddr&PadT,		x"00",			x"00",	x"00000000"),
		(NullTag,	x"00",	NullTag,	x"00",	NullAddr&PadT,		x"00",			x"00",	x"00000000"),
		(NullTag,	x"00",	NullTag,	x"00",	NullAddr&PadT,		x"00",			x"00",	x"00000000"),
		(NullTag,	x"00",	NullTag,	x"00",	NullAddr&PadT,		x"00",			x"00",	x"00000000"),
		(NullTag,	x"00",	NullTag,	x"00",	NullAddr&PadT,		x"00",			x"00",	x"00000000"),
		(NullTag,	x"00",	NullTag,	x"00",	NullAddr&PadT,		x"00",			x"00",	x"00000000"),
		(NullTag,	x"00",	NullTag,	x"00",	NullAddr&PadT,		x"00",			x"00",	x"00000000"),
		(NullTag,	x"00",	NullTag,	x"00",	NullAddr&PadT,		x"00",			x"00",	x"00000000"),
		(NullTag,	x"00",	NullTag,	x"00",	NullAddr&PadT,		x"00",			x"00",	x"00000000"),
		(NullTag,	x"00",	NullTag,	x"00",	NullAddr&PadT,		x"00",			x"00",	x"00000000"),
		(NullTag,	x"00",	NullTag,	x"00",	NullAddr&PadT,		x"00",			x"00",	x"00000000"),
		(NullTag,	x"00",	NullTag,	x"00",	NullAddr&PadT,		x"00",			x"00",	x"00000000"),
		(NullTag,	x"00",	NullTag,	x"00",	NullAddr&PadT,		x"00",			x"00",	x"00000000"),
		(NullTag,	x"00",	NullTag,	x"00",	NullAddr&PadT,		x"00",			x"00",	x"00000000"),
		(NullTag,	x"00",	NullTag,	x"00",	NullAddr&PadT,		x"00",			x"00",	x"00000000"),
		(NullTag,	x"00",	NullTag,	x"00",	NullAddr&PadT,		x"00",			x"00",	x"00000000"),
		(NullTag,	x"00",	NullTag,	x"00",	NullAddr&PadT,		x"00",			x"00",	x"00000000"),
		(NullTag,	x"00",	NullTag,	x"00",	NullAddr&PadT,		x"00",			x"00",	x"00000000"),
		(NullTag,	x"00",	NullTag,	x"00",	NullAddr&PadT,		x"00",			x"00",	x"00000000"),
		(NullTag,	x"00",	NullTag,	x"00",	NullAddr&PadT,		x"00",			x"00",	x"00000000"),
		(NullTag,	x"00",	NullTag,	x"00",	NullAddr&PadT,		x"00",			x"00",	x"00000000"),
		(NullTag,	x"00",	NullTag,	x"00",	NullAddr&PadT,		x"00",			x"00",	x"00000000"),
		(NullTag,	x"00",	NullTag,	x"00",	NullAddr&PadT,		x"00",			x"00",	x"00000000"),
		(NullTag,	x"00",	NullTag,	x"00",	NullAddr&PadT,		x"00",			x"00",	x"00000000")
		);
			
	constant PinDesc : PinDescType :=(
-- 	Base func  sec unit sec func 	 sec pin
        -- 7i47S
	IOPortTag & x"00" & StepGenTag & StepGenStepPin,	-- I/O 00
	IOPortTag & x"00" & StepGenTag & StepGenDirPin,		-- I/O 01	
	IOPortTag & x"01" & StepGenTag & StepGenStepPin,	-- I/O 02		
	IOPortTag & x"01" & StepGenTag & StepGenDirPin,		-- I/O 03		
	IOPortTag & x"00" & QCountTag & QCountQAPin,		-- I/O 04		
	IOPortTag & x"02" & QCountTag & QCountQAPin,		-- I/O 05		
	IOPortTag & x"00" & QCountTag & QCountQBPin,		-- I/O 06			
	IOPortTag & x"02" & QCountTag & QCountQBPin,		-- I/O 07		
	IOPortTag & x"00" & QCountTag & QCountIDXPin,		-- I/O 08		
	IOPortTag & x"02" & QCountTag & QCountIDXPin,		-- I/O 09
	IOPortTag & x"01" & QCountTag & QCountQAPin,		-- I/O 10
	IOPortTag & x"03" & QCountTag & QCountQAPin,		-- I/O 11
	IOPortTag & x"01" & QCountTag & QCountQBPin,		-- I/O 12		
	IOPortTag & x"03" & QCountTag & QCountQBPin,		-- I/O 13	
	IOPortTag & x"01" & QCountTag & QCountIDXPin,		-- I/O 14	
	IOPortTag & x"03" & QCountTag & QCountIDXPin,		-- I/O 15
	IOPortTag & x"00" & NullTag & x"00",			-- I/O 16 7I47S SPARE ISOLATED OUT
	IOPortTag & x"00" & PWMTag  & PWMBDirPin,		-- I/O 17 7I47S DIRECTION	
	IOPortTag & x"00" & PWMTag  & PWMCEnaPin,		-- I/O 18 7I47S PWMENABLE			
	IOPortTag & x"00" & PWMTag  & PWMAOutPin,		-- I/O 19 7I47S PWMOUT	
	IOPortTag & x"02" & StepGenTag & StepGenStepPin,	-- I/O 20			
	IOPortTag & x"02" & StepGenTag & StepGenDirPin,		-- I/O 21
	IOPortTag & x"03" & StepGenTag & StepGenStepPin,	-- I/O 22			
	IOPortTag & x"03" & StepGenTag & StepGenDirPin,		-- I/O 23

        -- 7i37
	IOPortTag & x"00" & NullTag & x"00",			-- I/O 24
	IOPortTag & x"00" & NullTag & x"00",			-- I/O 25
	IOPortTag & x"00" & NullTag & x"00",			-- I/O 26
	IOPortTag & x"00" & NullTag & x"00",			-- I/O 27
	IOPortTag & x"00" & NullTag & x"00",			-- I/O 28
	IOPortTag & x"00" & NullTag & x"00",			-- I/O 29
	IOPortTag & x"00" & NullTag & x"00",			-- I/O 30
	IOPortTag & x"00" & NullTag & x"00",			-- I/O 31
	IOPortTag & x"00" & NullTag & x"00",			-- I/O 32
	IOPortTag & x"00" & NullTag & x"00",			-- I/O 33
	IOPortTag & x"00" & NullTag & x"00",			-- I/O 34
	IOPortTag & x"00" & NullTag & x"00",			-- I/O 35
	IOPortTag & x"00" & NullTag & x"00",			-- I/O 36
	IOPortTag & x"00" & NullTag & x"00",			-- I/O 37
	IOPortTag & x"00" & NullTag & x"00",			-- I/O 38
	IOPortTag & x"00" & NullTag & x"00",			-- I/O 39
	IOPortTag & x"00" & NullTag & x"00",			-- I/O 40
	IOPortTag & x"00" & NullTag & x"00",			-- I/O 41
	IOPortTag & x"00" & NullTag & x"00",			-- I/O 42
	IOPortTag & x"00" & NullTag & x"00",			-- I/O 43
	IOPortTag & x"00" & NullTag & x"00",			-- I/O 44
	IOPortTag & x"00" & NullTag & x"00",			-- I/O 45
	IOPortTag & x"00" & NullTag & x"00",			-- I/O 46
	IOPortTag & x"00" & NullTag & x"00",			-- I/O 47

        -- 2x 7i29
	IOPortTag & x"05" & QCountTag & QCountQBPin,        	-- I/O 48
	IOPortTag & x"05" & QCountTag & QCountQAPin,        	-- I/O 49	
	IOPortTag & x"04" & QCountTag & QCountQBPin,        	-- I/O 50
	IOPortTag & x"04" & QCountTag & QCountQAPin,        	-- I/O 51	
	IOPortTag & x"05" & QCountTag & QCountIDXPin,       	-- I/O 52 
	IOPortTag & x"04" & QCountTag & QCountIDXPin,       	-- I/O 53 
	IOPortTag & x"05" & PWMTag & PWMAOutPin,            	-- I/O 54
	IOPortTag & x"04" & PWMTag & PWMAOutPin,            	-- I/O 55
	IOPortTag & x"05" & PWMTag & PWMBDirPin,            	-- I/O 56
	IOPortTag & x"04" & PWMTag & PWMBDirPin,            	-- I/O 57
	IOPortTag & x"05" & PWMTag & PWMCEnaPin,            	-- I/O 58
	IOPortTag & x"04" & PWMTag & PWMCEnaPin,            	-- I/O 59
	IOPortTag & x"07" & QCountTag & QCountQBPin,        	-- I/O 60
	IOPortTag & x"07" & QCountTag & QCountQAPin,        	-- I/O 61	
	IOPortTag & x"06" & QCountTag & QCountQBPin,        	-- I/O 62
	IOPortTag & x"06" & QCountTag & QCountQAPin,        	-- I/O 63	
	IOPortTag & x"07" & QCountTag & QCountIDXPin,       	-- I/O 64 
	IOPortTag & x"06" & QCountTag & QCountIDXPin,       	-- I/O 65 
	IOPortTag & x"07" & PWMTag & PWMAOutPin,            	-- I/O 66
	IOPortTag & x"06" & PWMTag & PWMAOutPin,            	-- I/O 67
	IOPortTag & x"07" & PWMTag & PWMBDirPin,            	-- I/O 68
	IOPortTag & x"06" & PWMTag & PWMBDirPin,            	-- I/O 69
	IOPortTag & x"07" & PWMTag & PWMCEnaPin,            	-- I/O 70
	IOPortTag & x"06" & PWMTag & PWMCEnaPin,           	-- I/O 71

        -- added for IDROM v3
	emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
	emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
	emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
	emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
	emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
	emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
	emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
	emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
	emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);

end package PIN_SVST_FOOBAR;


Thanks again
_jC
.
Last edit: 22 May 2013 23:37 by jCandlish. Reason: can't attach a .vhd file??? inlined!

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22 May 2013 23:53 #34557 by PCW
Replied by PCW on topic hm2/hm2_5i23.0: unknown stepgen MD:
The x"0a" was a stepgen count from a pinfile for a config with 10 stepgens
I never had a numeric value of ClockLowTag

If you see random glitches/missing pin data with a supplied bitfile,
I would suspect the driver/hardware, otherwise its still likely a error on the
IDROM creation (from the PINxxxx.vhd file) somehow

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23 May 2013 06:18 #34570 by andypugh
Replied by andypugh on topic hm2/hm2_5i23.0: unknown stepgen MD:

[
net machine-is-enabled => hm2_5i23.0.pwmgen.00.enable
I am assuming that 'machine-is-enabled' turns on the ENA optoisolator and enables the PWM. I have the ENA optoisolator switching a relay coil that in turn switches a pair on NC contacts in the e-stop loop. I would like to know more about the logic of 'machine-is-enabled'.

It doesn't have any inherent logic, it is just a signal name chosen by whoever wrote the HAL file. The logic comes from what else it is netted to.
(unless it is, then it will actually do nothing at all)

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