Mesa 7i80HD / 7i53 / 7i83 -- closed loop hal?
- westveld
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Details:
My config:
- Ubuntu 12.04 LTS 32-bit
- Followed andypugh's steps from: linuxcnc.org/index.php/english/forum/27-.../27253-7i80-and-7i77
- 3.10.4-rt1mah kernel
- latest git pull of ubc3-7i80 branch
With halrun, all the cards show up, IO works, encoders read, analog out works fine.
The hal file I'm loading:
loadrt trivkins
loadrt motmod servo_period_nsec=1000000 num_joints=3
loadrt hostmot2
loadrt hm2_eth board_ip="192.168.1.121" board_mac="00:60:1B:11:80:1A" config="num_encoders=12 num_pwmgens=18 num_stepgens=0"
loadrt pid num_chan=3
setp hm2_7i80.0.watchdog.timeout_ns 10000000
addf hm2_7i80.0.read servo-thread
addf motion-command-handler servo-thread
addf motion-controller servo-thread
addf pid.0.do-pid-calcs servo-thread
addf pid.1.do-pid-calcs servo-thread
addf pid.2.do-pid-calcs servo-thread
addf hm2_7i80.0.write servo-thread
addf hm2_7i80.0.pet_watchdog servo-thread
start
When I do a show all, I don't get anything containing pwmgen.
Is this needed to close the PID loop?
Or is it done some other way?
Thanks!
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- PCW
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something like:
net X_Axis_PID_Out hm2_7i80.0.7i83.0.0.analogout0 pid.0.output
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- PCW
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dont trust the encoders too far until I update your bitfile.
The 7I80 and 7I90 are the first cards that have a 100 MHz ClockLow
and end up with a too fast mux rate (12.5 MHz) since the mux rate divisor
was hardwired for the earlier cards with 33 or 50 MHz ClockLow
The firmware source has been patched to calculate a suitable default
divisor based on the clocklow frequency.
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- westveld
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One thing I noticed - I'm pretty sure the hm2_7i80.0.encoder.xx aren't matching the port numbers on the card.
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- westveld
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What OS / Xilinx tool / version is recommended?
Thanks again!
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- PCW
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One thing I noticed - I'm pretty sure the hm2_7i80.0.encoder.xx aren't matching the port numbers on the card.
Thats a symptom of the too high mux frequency (even/odd encoder swaps)
freeby.mesanet.com/7i80hd_25_sssv18_12.bit
should fix this issue
Up-to-date firmware source is in the 7i80.zip file (/configs/source/hostmot2.zip)
(or actually any FPGA card zip file, the hostmot2 source is the same for all)
The xilinx webpack tools run on Linux or windows
Tom-ITX has a nice tutorial for building HostMot2 bitfiles here:
tom-itx.no-ip.biz:81/~webpage/emc/xilinx...14_install_index.php
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- andypugh
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freeby.mesanet.com/7i80hd_25_sssv18_12.bit
should fix this issue
Just chiming in to point out that you flash the bit-file there with mesaflash, there is no need for thw Xilinx tools to use a bitfile, only if you want to create a bitfile.
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- ErrickW
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One thing I noticed - I'm pretty sure the hm2_7i80.0.encoder.xx aren't matching the port numbers on the card.
Thats a symptom of the too high mux frequency (even/odd encoder swaps)
freeby.mesanet.com/7i80hd_25_sssv18_12.bit
should fix this issue
Up-to-date firmware source is in the 7i80.zip file (/configs/source/hostmot2.zip)
(or actually any FPGA card zip file, the hostmot2 source is the same for all)
The xilinx webpack tools run on Linux or windows
Tom-ITX has a nice tutorial for building HostMot2 bitfiles here:
tom-itx.dyndns.org:81/~webpage/emc/xilin...14_install_index.php
The Tom-ITX tutorial web page seams to be gone. By any chance does anyone have a downloaded copy it? I have been looking for good info about building bit files.
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- andypugh
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My idea was to have a web front-end to define the bitfile layout, then a button to start a compile which eventually emailed out the bitfile. But then I started restoring an old motorbike...
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- PCW
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tom-itx.no-ip.biz:81/~webpage/emc/xilinx...14_install_index.php
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