Mesa 7i80HD / 7i53 / 7i83 -- closed loop hal?

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10 Mar 2014 08:16 #44619 by westveld
Short version - I can't figure out how to setup the PID loop for servos on this combo.

Details:

My config:
With halrun, all the cards show up, IO works, encoders read, analog out works fine.

The hal file I'm loading:
loadrt trivkins
loadrt motmod servo_period_nsec=1000000 num_joints=3
loadrt hostmot2
loadrt hm2_eth board_ip="192.168.1.121" board_mac="00:60:1B:11:80:1A" config="num_encoders=12 num_pwmgens=18 num_stepgens=0"
loadrt pid num_chan=3 
setp hm2_7i80.0.watchdog.timeout_ns 10000000
addf hm2_7i80.0.read servo-thread
addf motion-command-handler               servo-thread
addf motion-controller                    servo-thread
addf pid.0.do-pid-calcs servo-thread
addf pid.1.do-pid-calcs servo-thread
addf pid.2.do-pid-calcs servo-thread
addf hm2_7i80.0.write servo-thread
addf hm2_7i80.0.pet_watchdog servo-thread
start

When I do a show all, I don't get anything containing pwmgen.

Is this needed to close the PID loop?
Or is it done some other way?

Thanks!

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10 Mar 2014 08:52 - 10 Mar 2014 08:56 #44620 by PCW
The PID output would connect to the 7I83 analog out pins

something like:
net X_Axis_PID_Out  hm2_7i80.0.7i83.0.0.analogout0 pid.0.output
Last edit: 10 Mar 2014 08:56 by PCW.
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11 Mar 2014 03:03 - 11 Mar 2014 03:04 #44636 by PCW
BTW I found a bug in the Muxed encoders on the 7I80/7I90 so
dont trust the encoders too far until I update your bitfile.

The 7I80 and 7I90 are the first cards that have a 100 MHz ClockLow
and end up with a too fast mux rate (12.5 MHz) since the mux rate divisor
was hardwired for the earlier cards with 33 or 50 MHz ClockLow
The firmware source has been patched to calculate a suitable default
divisor based on the clocklow frequency.
Last edit: 11 Mar 2014 03:04 by PCW.

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11 Mar 2014 20:58 #44670 by westveld
Replied by westveld on topic Mesa 7i80HD / 7i53 / 7i83 -- closed loop hal?
I haven't had time to do much more testing.

One thing I noticed - I'm pretty sure the hm2_7i80.0.encoder.xx aren't matching the port numbers on the card.

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11 Mar 2014 21:40 #44671 by westveld
Replied by westveld on topic Mesa 7i80HD / 7i53 / 7i83 -- closed loop hal?
Is the firmware source available for download?

What OS / Xilinx tool / version is recommended?

Thanks again!

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11 Mar 2014 22:12 - 03 Jun 2014 21:53 #44672 by PCW

One thing I noticed - I'm pretty sure the hm2_7i80.0.encoder.xx aren't matching the port numbers on the card.


Thats a symptom of the too high mux frequency (even/odd encoder swaps)

freeby.mesanet.com/7i80hd_25_sssv18_12.bit

should fix this issue

Up-to-date firmware source is in the 7i80.zip file (/configs/source/hostmot2.zip)
(or actually any FPGA card zip file, the hostmot2 source is the same for all)

The xilinx webpack tools run on Linux or windows

Tom-ITX has a nice tutorial for building HostMot2 bitfiles here:

tom-itx.no-ip.biz:81/~webpage/emc/xilinx...14_install_index.php
Last edit: 03 Jun 2014 21:53 by PCW. Reason: update link
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11 Mar 2014 23:27 #44681 by andypugh
Replied by andypugh on topic Mesa 7i80HD / 7i53 / 7i83 -- closed loop hal?

freeby.mesanet.com/7i80hd_25_sssv18_12.bit

should fix this issue


Just chiming in to point out that you flash the bit-file there with mesaflash, there is no need for thw Xilinx tools to use a bitfile, only if you want to create a bitfile.
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03 Jun 2014 19:26 #47653 by ErrickW
Replied by ErrickW on topic Mesa 7i80HD / 7i53 / 7i83 -- closed loop hal?

One thing I noticed - I'm pretty sure the hm2_7i80.0.encoder.xx aren't matching the port numbers on the card.


Thats a symptom of the too high mux frequency (even/odd encoder swaps)

freeby.mesanet.com/7i80hd_25_sssv18_12.bit

should fix this issue

Up-to-date firmware source is in the 7i80.zip file (/configs/source/hostmot2.zip)
(or actually any FPGA card zip file, the hostmot2 source is the same for all)

The xilinx webpack tools run on Linux or windows

Tom-ITX has a nice tutorial for building HostMot2 bitfiles here:

tom-itx.dyndns.org:81/~webpage/emc/xilin...14_install_index.php


The Tom-ITX tutorial web page seams to be gone. By any chance does anyone have a downloaded copy it? I have been looking for good info about building bit files.

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03 Jun 2014 19:34 #47654 by andypugh
Replied by andypugh on topic Mesa 7i80HD / 7i53 / 7i83 -- closed loop hal?
I got as far as setting up the Xilinx web-pack on a publically accessible Amazon AWS instance. Then got distracted...

My idea was to have a web front-end to define the bitfile layout, then a button to start a compile which eventually emailed out the bitfile. But then I started restoring an old motorbike...

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03 Jun 2014 21:55 #47662 by PCW
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