7i85s Outputs and Dyn2

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01 Jan 2015 03:40 - 01 Jan 2015 07:37 #54455 by ugnx
7i85s Outputs and Dyn2 was created by ugnx
Hello

I need some help trying to figure out the output step/dir pins and encoders on the 7i85s. I don't have any LinuxCNC/Mesa experience but, giving it a try. Going through the manual it gives me TX0, /TX0 - TX7, /TX7. Looking further, it says that TX means Inverted,(-), and /TX means Non Inverted signal, (+.) Is this correct? Also, I am trying to figure out which one is Step or Dir. I went through the 5i25_7i85sx2.pin file for reference and need to know if I am even close to being correct? Also the Dyn2 has a Absolute Zero Position Index encoder Output (ZRI) can I use it for anything? Here is a link to the manual.
www.dmm-tech.com/Files/DYN2MS-01E-0814A1.pdf




7i85S
TB2 PIN FUNCTION

11, TX0 = DIR -
12, /TX0 = DIR +
13, TX1 = STEP -
14, /TX1 = STEP +
19, TX2 = DIR -
20, /TX2 = DIR +
21, TX3 = STEP -
22, /TX3 = STEP +
TB1 PIN FUNCTION
3, TX4 = DIR -
4, /TX4 = DIR +
5, TX5 = STEP -
6, /TX5 = STEP +
11, TX6 = DIR -
12, /TX6 = DIR +
13, TX7 = STEP -
14, /TX7 = STEP +
Last edit: 01 Jan 2015 07:37 by ugnx.

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01 Jan 2015 10:36 #54459 by PCW
Replied by PCW on topic 7i85s Outputs and Dyn2
That looks correct to me

The ZRI pin looks like a standard index signal (used for accurate homing)
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03 Jan 2015 04:37 #54512 by ugnx
Replied by ugnx on topic 7i85s Outputs and Dyn2
Thank you for your time and patience. I am sure I will have more questions.

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04 Jan 2015 06:45 #54530 by ugnx
Replied by ugnx on topic 7i85s Outputs and Dyn2
I am trying to figure out the stepgen parameters for the New Dyn2 Drive, steplen, stepspace, dirhold, dirsetup and dirdelay. It looks like I cant find everything I need in the Dyn2 documentation. On Page 24, in the manual, it only gives me Maximum Pulse Frequency of 500Khz and Minimum pulse width of 800us? Also, I don't know if I can run stepgen_type=2, Quadature. The manual says it will accept A/B phase quadrature with 90° phase differential. Does stepgen type2 run faster?

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04 Jan 2015 10:45 #54537 by PCW
Replied by PCW on topic 7i85s Outputs and Dyn2
well if its 500 KHz max and 800 ns minimum pulse width thats not fully specified but 1us/1us should be fine and
10 usec dir setup and hold should be good for almost any modern drive.

As far as step rates go, mode 2 is scaled differently (4 times as many steps as step/dir mode)
so output scaling must be changed accordingly if quadrature mode is used (assuming the drive counts on all quadrature edges)

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04 Jan 2015 11:15 #54538 by ugnx
Replied by ugnx on topic 7i85s Outputs and Dyn2
Ok thanks, that was 800 microseconds for width. So, 800,000ns for steplen,stepspace? How would that effect direction and hold? If understand correctly, using mode 2, the system can calculate 4x as many steps compared to mode 1? Using less resources?

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04 Jan 2015 11:34 #54539 by PCW
Replied by PCW on topic 7i85s Outputs and Dyn2
That _must_ be 800 ns (800 usec would only allow about 60 max RPM with 1250 count/rev step ratio)

No calculations are done in step generation except an addition. Theres really no advantage/disadvantage
to the various output modes except quadrature is simpler to specify. Maximum step rate is not an issue
(even the slowest card can output 8.33 MHz step rates)
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05 Jan 2015 22:54 - 05 Jan 2015 22:55 #54580 by ugnx
Replied by ugnx on topic 7i85s Outputs and Dyn2
Ok, Thank you, for some reason, I couldnt get it to work using type 0. The servo wouldn't turn and I was almost ready to give up. I switched the drive settings to A/B Phase quadature and set stepgen to type 2 and, Bam, it worked! Go figure...., the mode I was asking about and I have no clue why? I am waiting on DMM Tech for the missing parameters but what you gave me worked. Thank you for your help.
Last edit: 05 Jan 2015 22:55 by ugnx.

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