1. Hardware & Machines
  3. Driver Boards
  5. Rearranging pin assignment on mesa 5i25

Rearranging pin assignment on mesa 5i25

More
10 Oct 2015 14:20 #63649 by sirop
Rearranging pin assignment on mesa 5i25 was created by sirop
Hallo.

I sent my question already to emc-users lists . But it somehow did not get through or landed in their spam folder.
So I try it on this forum.

I have to rearrange some pins on mesa 6i25 running with 5i25 firmware.
I downloaded the Xelinx (Webpack) 14.7 .

Then I looked at PIN_DMMBOB1x2_34.vhd and PIN_PROB_RFx2_34.vhd as
these two seem to be most easily editable.

The issue which I do not really understand is the mapping between I/O
ports und PINs.
For instance, these lines from PIN_DMMBOB1x2_34.vhd :
constant PinDesc : PinDescType :=(
--  Base func  sec unit sec func sec pin -- external DB25
IOPortTag & x"00" & PWMTag & PWMAOutPin, -- I/O 00 PIN 1 Spindle DAC PWM
IOPortTag & x"00" & NullTag & NullPin, -- I/O 01 PIN 14 just GPIO
IOPortTag & x"00" & StepGenTag & StepGenDirPin, -- I/O 02 PIN 2    X Dir
IOPortTag & x"00" & NullTag & NullPin, -- I/O 03 PIN 15 just GPIO
....................
);

Why does I/O 03 correspond to PIN 15?
With other words: how arbitrary is this mapping?
Is there any tutorial about this issue?

Regards,
Boris

Please Log in or Create an account to join the conversation.

More
10 Oct 2015 21:41 - 10 Oct 2015 21:43 #63658 by PCW
Replied by PCW on topic Rearranging pin assignment on mesa 5i25
Hostmot2 firmwares GPIO pin order is mapped to the physical order in the pinout file (PINXXX.vhd)
that is, the first pin in the file is always GPIO 0, the second GPIO 1 etc. GPIO pins
are directly mapped to register bits in the firmware. They are packed, so the first connector on a 5I25
is connected to GPIO bits 0 through 16 and the second to GPIO bits 17 through 33

How these are mapped to actual physical connector pins depends on the individual card
but for cards with HDR26 and DB25 connectors. they are arranged in physical order so on a DB25
you end up with a

GPIO 0 = PIN 1
GPIO 1 = PIN 14
GPIO 2 = PIN 2
GPIO 3= PIN 15

sequence

on a 26 pin header the sequence ends up being more orderly:

GPIO 0 = PIN 1
GPIO 1 = PIN 2
GPIO 2 = PIN 3
GPIO 3 = PIN 4

At least until you run into the ground pins on the parallel port pinout
Last edit: 10 Oct 2015 21:43 by PCW.
The following user(s) said Thank You: sirop

Please Log in or Create an account to join the conversation.

More
11 Oct 2015 17:43 #63680 by sirop
Replied by sirop on topic Rearranging pin assignment on mesa 5i25
Hallo.

Thanks for your fast answer.

A my mesa card is already wired, I have to change Encoder PINs,
so that:
  • Encoder APin is connected to PIN 15,
  • Encoder BPin - to PIN 14
  • Encoder IdxPin - to PIN 16.

I called my PIN file PIN_cps5i25_32:
library IEEE;
use IEEE.std_logic_1164.all;  -- defines std_logic types
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
-- http://www.mesanet.com
--
-- This program is is licensed under a disjunctive dual license giving you
-- the choice of one of the two following sets of free software/open source
-- licensing terms:

use work.IDROMConst.all;

package PIN_cps5i25_34 is
	constant ModuleID : ModuleIDType :=( 
		(WatchDogTag,	x"00",	ClockLowTag,	x"01",	WatchDogTimeAddr&PadT,		WatchDogNumRegs,		x"00",	WatchDogMPBitMask),
		(IOPortTag,		x"00",	ClockLowTag,	x"02",	PortAddr&PadT,					IOPortNumRegs,			x"00",	IOPortMPBitMask),
		(QcountTag,		x"02",	ClockLowTag,	x"02",	QcounterAddr&PadT,			QCounterNumRegs,		x"00",	QCounterMPBitMask),
		(StepGenTag,	x"02",	ClockLowTag,	x"08",	StepGenRateAddr&PadT,		StepGenNumRegs,		x"00",	StepGenMPBitMask),
		(PWMTag,			x"00",	ClockHighTag,	x"02",	PWMValAddr&PadT,				PWMNumRegs,				x"00",	PWMMPBitMask),
		(LEDTag,			x"00",	ClockLowTag,	x"01",	LEDAddr&PadT,					LEDNumRegs,				x"00",	LEDMPBitMask),
		................................................................................................
		);
		
	
	constant PinDesc : PinDescType :=(
-- 	Base func  sec unit sec func 	 sec pin					-- external DB25
		IOPortTag & x"00" & PWMTag & PWMAOutPin,			-- I/O 00	PIN 1		Spindle DAC PWM
	--	IOPortTag & x"00" & NullTag & NullPin,					-- I/O 01	PIN 14 	just GPIO  
	        IOPortTag & x"00" & QCountTag & QCountQBPin,  		-- I/O 01	PIN 14	Input 2 (Quad B)
		IOPortTag & x"00" & StepGenTag & StepGenDirPin,		-- I/O 02	PIN 2    X Dir
	--	IOPortTag & x"00" & NullTag & NullPin,					-- I/O 03	PIN 15	just GPIO
	        IOPortTag & x"00" & QCountTag & QCountQAPin, 		-- I/O 03	PIN 15	Input 3 (Quad A)
		IOPortTag & x"00" & StepGenTag & StepGenStepPin,	-- I/O 04	PIN 3		X Step    
	--	IOPortTag & x"00" & NullTag & NullPin,					-- I/O 05	PIN 16   just GPIO
	        IOPortTag & x"00" & QCountTag & QCountIdxPin,    	        -- I/O 05	PIN 16	Input 4 (Quad Idx)
		IOPortTag & x"01" & StepGenTag & StepGenDirPin,		-- I/O 06	PIN 4		Y Dir
		IOPortTag & x"00" & NullTag & NullPin,					-- I/O 07	PIN 17	just GPIO
		IOPortTag & x"01" & StepGenTag & StepGenStepPin,	-- I/O 08	PIN 5 	Y Step
		IOPortTag & x"02" & StepGenTag & StepGenDirPin,		-- I/O 09	PIN 6		Z Dir
		IOPortTag & x"02" & StepGenTag & StepGenStepPin,	-- I/O 10	PIN 7		Z Step
		IOPortTag & x"03" & StepGenTag & StepGenDirPin,		-- I/O 11	PIN 8		A Dir
		IOPortTag & x"03" & StepGenTag & StepGenStepPin,	-- I/O 12	PIN 9		A Step
		IOPortTag & x"00" & NullTag & NullPin,					-- I/O 13	PIN 10	Input 1 just GPIO
	--	IOPortTag & x"00" & QCountTag & QCountQAPin,  		-- I/O 14	PIN 11	Input 2 (Quad A)
	        IOPortTag & x"00" & NullTag & NullPin,					-- I/O 14	PIN 11 	just GPIO 
	--	IOPortTag & x"00" & QCountTag & QCountQBPin,  		-- I/O 15	PIN 12	Input 3 (Quad B)
	        IOPortTag & x"00" & NullTag & NullPin,					-- I/O 15	PIN 12	just GPIO
	--	IOPortTag & x"00" & QCountTag & QCountIdxPin,    	        -- I/O 16	PIN 13	Input 4 (Quad Idx)
		IOPortTag & x"00" & NullTag & NullPin,					-- I/O 16	PIN 13   just GPIO
		
		
																			-- 26 HDR	-- IDC DB25	
		.............................................................................................................
		emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);

end package PIN_cps5i25_34;

Added
use work.PIN_cps5i25_34.all;
to TopPCIHostMot2 keeping
use work.i25_x9card.all;
in the card type section.

If I then rerun all, I do get many warnings. Do not know if there are of any interest to anyone, just paste the output to gist:
gist.github.com/sirop/b0b42b232c34ba4b14f8

If I just ReRun for only my file, then I get only two warnings:
WARNING:Bitgen:284 - Setting next_config_register_write to Disable will cause
   the next_config_addr, next_config_new_mode, and next_config_boot_mode options
   to be ignored and their respective register writes to be excluded from the
   bitstream.
WARNING:PhysDesignRules:2410 - This design is using one or more 9K Block RAMs
   (RAMB8BWER).  9K Block RAM initialization data, both user defined and
   default, may be incorrect and should not be used.  For more information,
   please reference Xilinx Answer Record 39999.

Seems to be ok so far.

However, I am not sure about the following two things:
  1. What does "sec unit" in PinDescType mean and is it correct to let it be x"00" for the Encoder pins?
  2. If next_config_register_write is disabled as the above cited warning says, the option "-g next_config_register_write:disable" is set by itself?

Regards,
Boris

Please Log in or Create an account to join the conversation.

More
11 Oct 2015 20:49 #63684 by PCW
Replied by PCW on topic Rearranging pin assignment on mesa 5i25
Each pin has a primary function and a secondary function
In hostmot2, the primary function is GPIO and this is always available
in all I/O pins.

Secondary functions are things like encoders, pwm, stepgens etc
the secondary unit is the instance number of the secondary unit so if you have 3 encoders for example
they would have secondary unit numbers of 0, 1,and 2

So your example pinout file has an error in that it has 2 instances of encoder 0


"-g next_config_register_write:disable" is part of the bitfile options that are set in the project file.
This option is necessary (as are a number of other bitfile options) to allow fallback to work with
bitfiles that may be loaded in arbitrary places in flash memory.

Basically its done to ignore any address setting commands in the bitfile
(and instead use the addresses that the bootblock in the flash memory sets)
The following user(s) said Thank You: sirop

Please Log in or Create an account to join the conversation.

More
15 Oct 2015 15:59 - 15 Oct 2015 16:06 #63770 by sirop
Replied by sirop on topic Rearranging pin assignment on mesa 5i25
Hallo again.

At the beginning I wanted to keep my custom firmware as simple as possible.
So I wrote:
	constant PinDesc : PinDescType :=(
-- 	Base func  sec unit sec func 	 sec pin					-- external DB25
	--	IOPortTag & x"00" & PWMTag & PWMAOutPin,				-- I/O 00	PIN 1		Spindle DAC PWM
	   IOPortTag & x"00" & NullTag & NullPin,					-- I/O 00	PIN 1 	just GPIO
	  	IOPortTag & x"00" & NullTag & NullPin,					-- I/O 01	PIN 14 	GPIO Joystick X 
	   IOPortTag & x"00" & NullTag & NullPin,		         -- I/O 02	PIN 2    GPIO Joystick Y
		IOPortTag & x"00" & NullTag & NullPin,					-- I/O 03	PIN 15	GPIO Pot1 XSens
	   IOPortTag & x"00" & NullTag & NullPin,          	-- I/O 04	PIN 3		GPIO LED1	
		IOPortTag & x"00" & NullTag & NullPin,					-- I/O 05	PIN 16   GPIO LED2
	--	IOPortTag & x"01" & StepGenTag & StepGenDirPin,		-- I/O 06	PIN 4		Y Dir
	   IOPortTag & x"00" & NullTag & NullPin,	            -- I/O 06	PIN 4	   just GPIO
		IOPortTag & x"00" & NullTag & NullPin,					-- I/O 07	PIN 17	GPIO Switch2 Right
	--	IOPortTag & x"01" & StepGenTag & StepGenStepPin,	-- I/O 08	PIN 5 	Y Step
	   IOPortTag & x"00" & NullTag & NullPin,					-- I/O 08	PIN 5	   GPIO Switch2 Left
	--	IOPortTag & x"02" & StepGenTag & StepGenDirPin,		-- I/O 09	PIN 6		Z Dir
	   IOPortTag & x"00" & NullTag & NullPin,					-- I/O 09	PIN 6	   GPIO Switch1 Right
	--	IOPortTag & x"02" & StepGenTag & StepGenStepPin,	-- I/O 10	PIN 7		Z Step
	   IOPortTag & x"00" & NullTag & NullPin,					-- I/O 10	PIN 7	   GPIO Switch2 Left
	--	IOPortTag & x"03" & StepGenTag & StepGenDirPin,		-- I/O 11	PIN 8		A Dir
	   IOPortTag & x"00" & NullTag & NullPin,					-- I/O 11	PIN 8	   just GPIO 
	--	IOPortTag & x"03" & StepGenTag & StepGenStepPin,	-- I/O 12	PIN 9		A Step
	   IOPortTag & x"00" & NullTag & NullPin,					-- I/O 12	PIN 9 	just GPIO 
		IOPortTag & x"00" & NullTag & NullPin,					-- I/O 13	PIN 10	Input 1 just GPIO
		IOPortTag & x"00" & QCountTag & QCountQBPin,  		-- I/O 14	PIN 11	Input 2 (Quad B)
		IOPortTag & x"00" & QCountTag & QCountQAPin,  		-- I/O 15	PIN 12	Input 3 (Quad A)
		IOPortTag & x"00" & QCountTag & QCountIdxPin,    	-- I/O 16	PIN 13	Input 4 (Quad Idx)
	
		
		
																			-- 26 HDR	-- IDC DB25	
	--	IOPortTag & x"01" & PWMTag & PWMAOutPin,				-- I/O 17	PIN 1		PIN 1 	Spindle DAC PWM
	   IOPortTag & x"00" & NullTag & NullPin,					-- I/O 17   PIN 1		PIN 14	just GPIO
		IOPortTag & x"00" & NullTag & NullPin,					-- I/O 18   PIN 2		PIN 14	just GPIO
	--	IOPortTag & x"04" & StepGenTag & StepGenDirPin,		-- I/O 19   PIN 3		PIN 2	   X2 Dir
	   IOPortTag & x"00" & NullTag & NullPin,					-- I/O 19   PIN 3		PIN 2	   just GPIO
		IOPortTag & x"00" & NullTag & NullPin,					-- I/O 20	PIN 4		PIN 15	just GPIO
	--	IOPortTag & x"04" & StepGenTag & StepGenStepPin,	-- I/O 21	PIN 5		PIN 3	   X2 Step   
      IOPortTag & x"00" & NullTag & NullPin,					-- I/O 21   PIN 5		PIN 2	   just GPIO	
		IOPortTag & x"00" & NullTag & NullPin,					-- I/O 22	PIN 6		PIN 16	just GPIO
	--	IOPortTag & x"05" & StepGenTag & StepGenDirPin,		-- I/O 23	PIN 7		PIN 4	   Y2 Dir
      IOPortTag & x"00" & NullTag & NullPin,					-- I/O 23   PIN 7		PIN 4	   just GPIO	
		IOPortTag & x"00" & NullTag & NullPin,					-- I/O 24	PIN 8		PIN 17	just GPIO
	--	IOPortTag & x"05" & StepGenTag & StepGenStepPin,	-- I/O 25	PIN 9		PIN 5	   Y2 Step
	   IOPortTag & x"00" & NullTag & NullPin,					-- I/O 25   PIN 9		PIN 5	   just GPIO
	--	IOPortTag & x"06" & StepGenTag & StepGenDirPin,		-- I/O 26	PIN 11	PIN 6	   Z2 Dir
	   IOPortTag & x"00" & NullTag & NullPin,					-- I/O 26   PIN 11	PIN 6	   just GPIO
	--	IOPortTag & x"06" & StepGenTag & StepGenStepPin,	-- I/O 27	PIN 13	PIN 7	   Z2 Step
	   IOPortTag & x"00" & NullTag & NullPin,					-- I/O 27   PIN 13	PIN 7	   just GPIO
	--	IOPortTag & x"07" & StepGenTag & StepGenDirPin,		-- I/O 28	PIN 15	PIN 8	   A2 Dir
	   IOPortTag & x"00" & NullTag & NullPin,					-- I/O 28   PIN 15	PIN 8	   just GPIO
	--	IOPortTag & x"07" & StepGenTag & StepGenStepPin,	-- I/O 29	PIN 17	PIN 9	   A2 Step
	   IOPortTag & x"00" & NullTag & NullPin,					-- I/O 29   PIN 17	PIN 9	   just GPIO
		IOPortTag & x"00" & NullTag & NullPin,					-- I/O 30	PIN 19	PIN 10	just GPIO
	--	IOPortTag & x"01" & QCountTag & QCountQAPin,  		-- I/O 31	PIN 21	PIN 11  	Input 2 (Quad A)
	   IOPortTag & x"00" & NullTag & NullPin,					-- I/O 31   PIN 21	PIN 11	just GPIO
	--	IOPortTag & x"01" & QCountTag & QCountQBPin,  		-- I/O 32	PIN 23	PIN 12	Input 3 (Quad B))
	   IOPortTag & x"00" & NullTag & NullPin,					-- I/O 32   PIN 23	PIN 12	just GPIO 
	--	IOPortTag & x"01" & QCountTag & QCountIdxPin,    	-- I/O 33	PIN 25	PIN 13	Input 4 (Quad Idx)
	   IOPortTag & x"00" & NullTag & NullPin,					-- I/O 33   PIN 25	PIN 13	just GPIO
		


		.............................................................................................................................................
		
		emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);

end package PIN_cps5i25_34;

As you see I left only one Encoder ( IO 14-16) and set all the other ports to GPIO.
However, I get then a compilation error:
ERROR:HDLCompiler:533 - "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25_old\configs\hostmot2\source\hostmot2\kubstepgenz.vhd" Line 340: Index 0 is out of array constraint -1 downto 0 for target localout
Netlist stepgen(32,14,0,48,32)(Behavioral) remains a blackbox, due to errors in its contents
If interested, the whole output of compilation is gist.github.com/sirop/e151100329440a8249...a5i25_withoutstepgen .

So my guess was that even If I do not to use the StepGen explicitly, the firmware needs it somehow.
Then I reverted some of my changes so that the corresponding part of my PIN vhd file looks like that now:
																		-- 26 HDR	-- IDC DB25	
	--	IOPortTag & x"01" & PWMTag & PWMAOutPin,				-- I/O 17	PIN 1		PIN 1 	Spindle DAC PWM
	        IOPortTag & x"00" & NullTag & NullPin,					-- I/O 17   PIN 1		PIN 14	just GPIO
		IOPortTag & x"00" & NullTag & NullPin,					-- I/O 18   PIN 2		PIN 14	just GPIO
		IOPortTag & x"04" & StepGenTag & StepGenDirPin,		-- I/O 19   PIN 3		PIN 2	   X2 Dir
	    -- IOPortTag & x"00" & NullTag & NullPin,					-- I/O 19   PIN 3		PIN 2	   just GPIO
		IOPortTag & x"00" & NullTag & NullPin,					-- I/O 20	PIN 4		PIN 15	just GPIO
		IOPortTag & x"04" & StepGenTag & StepGenStepPin,	-- I/O 21	PIN 5		PIN 3	   X2 Step   
          --   IOPortTag & x"00" & NullTag & NullPin,					-- I/O 21   PIN 5		PIN 2	   just GPIO	
		IOPortTag & x"00" & NullTag & NullPin,					-- I/O 22	PIN 6		PIN 16	just GPIO
		IOPortTag & x"05" & StepGenTag & StepGenDirPin,		-- I/O 23	PIN 7		PIN 4	   Y2 Dir
            -- IOPortTag & x"00" & NullTag & NullPin,					-- I/O 23   PIN 7		PIN 4	   just GPIO	
		IOPortTag & x"00" & NullTag & NullPin,					-- I/O 24	PIN 8		PIN 17	just GPIO
		IOPortTag & x"05" & StepGenTag & StepGenStepPin,	-- I/O 25	PIN 9		PIN 5	   Y2 Step
	    -- IOPortTag & x"00" & NullTag & NullPin,					-- I/O 25   PIN 9		PIN 5	   just GPIO
		IOPortTag & x"06" & StepGenTag & StepGenDirPin,		-- I/O 26	PIN 11	PIN 6	   Z2 Dir
	     -- IOPortTag & x"00" & NullTag & NullPin,					-- I/O 26   PIN 11	PIN 6	   just GPIO
	  --	IOPortTag & x"06" & StepGenTag & StepGenStepPin,	-- I/O 27	PIN 13	PIN 7	   Z2 Step
	        IOPortTag & x"00" & NullTag & NullPin,					-- I/O 27   PIN 13	PIN 7	   just GPIO
		IOPortTag & x"07" & StepGenTag & StepGenDirPin,		-- I/O 28	PIN 15	PIN 8	   A2 Dir
	  --   IOPortTag & x"00" & NullTag & NullPin,					-- I/O 28   PIN 15	PIN 8	   just GPIO
		IOPortTag & x"07" & StepGenTag & StepGenStepPin,	-- I/O 29	PIN 17	PIN 9	   A2 Step
	  --   IOPortTag & x"00" & NullTag & NullPin,					-- I/O 29   PIN 17	PIN 9	   just GPIO
		IOPortTag & x"00" & NullTag & NullPin,					-- I/O 30	PIN 19	PIN 10	just GPIO
	--	IOPortTag & x"01" & QCountTag & QCountQAPin,  		-- I/O 31	PIN 21	PIN 11  	Input 2 (Quad A)
	        IOPortTag & x"00" & NullTag & NullPin,					-- I/O 31   PIN 21	PIN 11	just GPIO
	--	IOPortTag & x"01" & QCountTag & QCountQBPin,  		-- I/O 32	PIN 23	PIN 12	Input 3 (Quad B))
	        IOPortTag & x"00" & NullTag & NullPin,					-- I/O 32   PIN 23	PIN 12	just GPIO 
	--	IOPortTag & x"01" & QCountTag & QCountIdxPin,    	        -- I/O 33	 PIN 25	PIN 13	Input 4 (Quad Idx)
	        IOPortTag & x"00" & NullTag & NullPin,					-- I/O 33   PIN 25	PIN 13	just GPIO

Then my file compiles normally with the usual warnings, already known before.

So my question would be: is my guess right and I need the StepGen functions even if I do not want to use them explicitly?
Last edit: 15 Oct 2015 16:06 by sirop.

Please Log in or Create an account to join the conversation.

More
15 Oct 2015 21:07 #63782 by PCW
Replied by PCW on topic Rearranging pin assignment on mesa 5i25
An index error like that usually indicates that you have an inconsistency between the pinout and the module ID section

That is, you have changed then number of stepgens in the pinout without a matching change in the module ID section
or vice versa.
The following user(s) said Thank You: sirop

Please Log in or Create an account to join the conversation.

More
28 Oct 2015 17:44 #64386 by sirop
Replied by sirop on topic Rearranging pin assignment on mesa 5i25
Thanks for your answers.

I made it very simple for the beginning keeping only one encoder and let all other PINs be GPIO.

I can read out the encoder position over hm2_5i25.0.encoder.00.position and velocity over hm2_5i25.0.encoder.00.velocity as well as some switches as GPIO outputs.

I wonder however why show pin in the halrun interface shows me two pins for encoder position:
halcmd: show pin
Component Pins:
  Comp   Inst Type  Dir         Value  Name                             Epsilon         Flags
    74        s32   OUT             0  hm2_5i25.0.encoder.00.count                      0
    74        s32   OUT             0  hm2_5i25.0.encoder.00.count-la                   0
    74        bit   I/O         FALSE  hm2_5i25.0.encoder.00.index-en                   0
    74        bit   OUT      FALSE  hm2_5i25.0.encoder.00.input-a                    0
    74        bit   OUT      TRUE  hm2_5i25.0.encoder.00.input-b                    0
    74        bit   OUT      TRUE  hm2_5i25.0.encoder.00.input-in                   0
    74        bit   IN          FALSE  hm2_5i25.0.encoder.00.latch-en                   0
    74        bit   IN          FALSE  hm2_5i25.0.encoder.00.latch-po                   0
    74        float OUT             0  hm2_5i25.0.encoder.00.position   0.000010        0
    74        float OUT             0  hm2_5i25.0.encoder.00.position   0.000010        0
 .....

This did not cause any error so far -- I used only the first hm2_5i25.0.encoder.00.position -- but, as said above, makes me wonder.

Please Log in or Create an account to join the conversation.

More
28 Oct 2015 18:35 - 28 Oct 2015 18:36 #64389 by PCW
Replied by PCW on topic Rearranging pin assignment on mesa 5i25
The duplicated pin is probably caused by some error in your pinout file

can you run:

sudo mesaflash --device 5i25 --readhmid > myconfig.txt

and post myconfig.txt here
Last edit: 28 Oct 2015 18:36 by PCW.
The following user(s) said Thank You: sirop

Please Log in or Create an account to join the conversation.

More
28 Oct 2015 18:45 - 28 Oct 2015 18:46 #64390 by sirop
Replied by sirop on topic Rearranging pin assignment on mesa 5i25
Ok.
:~/MESA/utils/linux/mesaflash-git$ sudo ./mesaflash --device 5i25 --readhmid
Configuration Name: HOSTMOT2

General configuration information:

  BoardName : MESA5I25
  FPGA Size: 9 KGates
  FPGA Pins: 144
  Number of IO Ports: 2
  Width of one I/O port: 17
  Clock Low frequency: 33.3333 MHz
  Clock High frequency: 200.0000 MHz
  IDROM Type: 3
  Instance Stride 0: 4
  Instance Stride 1: 64
  Register Stride 0: 256
  Register Stride 1: 256

Modules in configuration:

  Module: WatchDog
  There are 1 of WatchDog in configuration
  Version: 0
  Registers: 3
  BaseAddress: 0C00
  ClockFrequency: 33.333 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

  Module: IOPort
  There are 2 of IOPort in configuration
  Version: 0
  Registers: 5
  BaseAddress: 1000
  ClockFrequency: 33.333 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

  Module: QCount
  There are 1 of QCount in configuration
  Version: 2
  Registers: 5
  BaseAddress: 3000
  ClockFrequency: 33.333 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

  Module: LED
  There are 1 of LED in configuration
  Version: 0
  Registers: 1
  BaseAddress: 0200
  ClockFrequency: 33.333 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

Configuration pin-out:

IO Connections for P3
Pin#  I/O   Pri. func    Sec. func       Chan      Pin func        Pin Dir

 1      0   IOPort       None
14      1   IOPort       None
 2      2   IOPort       None
15      3   IOPort       None
 3      4   IOPort       None
16      5   IOPort       None
 4      6   IOPort       None
17      7   IOPort       None
 5      8   IOPort       None
 6      9   IOPort       None
 7     10   IOPort       None
 8     11   IOPort       None
 9     12   IOPort       None
10     13   IOPort       None
11     14   IOPort       QCount           0        Quad-B          (In)
12     15   IOPort       QCount           0        Quad-A          (In)
13     16   IOPort       QCount           0        Quad-IDX        (In)

IO Connections for P2
Pin#  I/O   Pri. func    Sec. func       Chan      Pin func        Pin Dir

 1     17   IOPort       None
14     18   IOPort       None
 2     19   IOPort       None
15     20   IOPort       None
 3     21   IOPort       None
16     22   IOPort       None
 4     23   IOPort       None
17     24   IOPort       None
 5     25   IOPort       None
 6     26   IOPort       None
 7     27   IOPort       None
 8     28   IOPort       None
 9     29   IOPort       None
10     30   IOPort       None
11     31   IOPort       None
12     32   IOPort       None
13     33   IOPort       None

BTW: I use github.com/micges/mesaflash.git for mesaflash as it has "--reload" option.
Last edit: 28 Oct 2015 18:46 by sirop.

Please Log in or Create an account to join the conversation.

More
28 Oct 2015 18:51 - 28 Oct 2015 19:02 #64391 by PCW
Replied by PCW on topic Rearranging pin assignment on mesa 5i25
The error appears to be that you have 2 encoders defined in
the module ID section of your pin-out file but only one
is defined the in pin-out section

Edit sorry, I misread the printout, I dont see any obvious problem.
Maybe posting your pinout source would help, but this may actually
be a hostmot2 driver bug, as I dont think there are any standard configurations
with just one encoder

BTW, you probably did not have to remove the second encoder or stepgens
to do what you wanted as you can just disable them in the hal config line
and their pins will revert to GPIO
Last edit: 28 Oct 2015 19:02 by PCW.
The following user(s) said Thank You: sirop

Please Log in or Create an account to join the conversation.

Moderators: PCW, jmelson
  1. Hardware & Machines
  3. Driver Boards
  5. Rearranging pin assignment on mesa 5i25
Time to create page: 0.123 seconds
Powered by Kunena Forum