7i92+7i77+7i74.bit file

I have a problem with 7i92, I have 7i92+7i77+7i74+3*7i84
I downloaded the 7i92+7i77+7i74D.bit from mesa to 7i92 but I couldn't communicate with 7i84 through 7i77, Only 7i77 was working.
Eventually I figured out that the .bit file is not appropriate

Configuration Name: HOSTMOT2

General configuration information:

BoardName : MESA7I92
FPGA Size: 9 KGates
FPGA Pins: 144
Number of IO Ports: 2
Width of one I/O port: 17
Clock Low frequency: 100.0000 MHz
Clock High frequency: 200.0000 MHz
IDROM Type: 3
Instance Stride 0: 4
Instance Stride 1: 64
Register Stride 0: 256
Register Stride 1: 256

Modules in configuration:

Module: DPLL
There are 1 of DPLL in configuration
Version: 0
Registers: 7
BaseAddress: 7000
ClockFrequency: 100.000 MHz
Register Stride: 256 bytes
Instance Stride: 4 bytes

Module: WatchDog
There are 1 of WatchDog in configuration
Version: 0
Registers: 3
BaseAddress: 0C00
ClockFrequency: 100.000 MHz
Register Stride: 256 bytes
Instance Stride: 4 bytes

Module: IOPort
There are 2 of IOPort in configuration
Version: 0
Registers: 5
BaseAddress: 1000
ClockFrequency: 100.000 MHz
Register Stride: 256 bytes
Instance Stride: 4 bytes

Module: MuxedQCount
There are 8 of MuxedQCount in configuration
Version: 3
Registers: 5
BaseAddress: 3600
ClockFrequency: 100.000 MHz
Register Stride: 256 bytes
Instance Stride: 4 bytes

Module: MuxedQCountSel
There are 1 of MuxedQCountSel in configuration
Version: 0
Registers: 0
BaseAddress: 0000
ClockFrequency: 100.000 MHz
Register Stride: 256 bytes
Instance Stride: 4 bytes

Module: SSerial
There are 1 of SSerial in configuration
Version: 0
Registers: 6
BaseAddress: 5B00
ClockFrequency: 100.000 MHz
Register Stride: 256 bytes
Instance Stride: 64 bytes

Module: StepGen
There are 5 of StepGen in configuration
Version: 2
Registers: 10
BaseAddress: 2000
ClockFrequency: 100.000 MHz
Register Stride: 256 bytes
Instance Stride: 4 bytes

Module: LED
There are 1 of LED in configuration
Version: 0
Registers: 1
BaseAddress: 0200
ClockFrequency: 100.000 MHz
Register Stride: 256 bytes
Instance Stride: 4 bytes

Configuration pin-out:

IO Connections for P2
Pin# I/O Pri. func Sec. func Chan Pin func Pin Dir

1 0 IOPort SSerial 0 TXEn3 (Out)
14 1 IOPort SSerial 0 TXData3 (Out)
2 2 IOPort SSerial 0 RXData3 (In)
15 3 IOPort SSerial 0 TXData2 (Out)
3 4 IOPort SSerial 0 RXData2 (In)
16 5 IOPort SSerial 0 TXData1 (Out)
4 6 IOPort SSerial 0 RXData1 (In)
17 7 IOPort MuxedQCountSel 0 MuxSel0 (Out)
5 8 IOPort MuxedQCount 0 MuxQ-A (In)
6 9 IOPort MuxedQCount 0 MuxQ-B (In)
7 10 IOPort MuxedQCount 0 MuxQ-IDX (In)
8 11 IOPort MuxedQCount 1 MuxQ-A (In)
9 12 IOPort MuxedQCount 1 MuxQ-B (In)
10 13 IOPort MuxedQCount 1 MuxQ-IDX (In)
11 14 IOPort MuxedQCount 2 MuxQ-A (In)
12 15 IOPort MuxedQCount 2 MuxQ-B (In)
13 16 IOPort MuxedQCount 2 MuxQ-IDX (In)

IO Connections for P1
Pin# I/O Pri. func Sec. func Chan Pin func Pin Dir

1 17 IOPort StepGen 0 Dir/Table2 (Out)
14 18 IOPort StepGen 0 Step/Table1 (Out)
2 19 IOPort StepGen 1 Dir/Table2 (Out)
15 20 IOPort StepGen 1 Step/Table1 (Out)
3 21 IOPort StepGen 2 Dir/Table2 (Out)
16 22 IOPort StepGen 2 Step/Table1 (Out)
4 23 IOPort StepGen 3 Dir/Table2 (Out)
17 24 IOPort StepGen 3 Step/Table1 (Out)
5 25 IOPort StepGen 4 Dir/Table2 (Out)
6 26 IOPort StepGen 4 Step/Table1 (Out)
7 27 IOPort SSerial 0 TXData4 (Out)
8 28 IOPort SSerial 0 RXData4 (In)
9 29 IOPort SSerial 0 TXData5 (Out)
10 30 IOPort SSerial 0 RXData5 (In)
11 31 IOPort MuxedQCount 3 MuxQ-IDX (In)
12 32 IOPort MuxedQCount 3 MuxQ-B (In)
13 33 IOPort MuxedQCount 3 MuxQ-A (In)

I tried to download the 5i25+7i77+7i47.bit to the 7i92 to solve the problem, but I made it even worth, I Can Not Communicate with 7i92 anymore.

Sorry for the bad bitfiles, I didnt notice that my build script failed on both the 7I76_7I74D and 7I77_7I74D so ended up
with the last successfully built bitfile in the script sequence. The reason they did not build is that those configs will not fit
in a 7I92. I have made a revised versions (that do fit) with just 6 sserial channels on the 7I74 connector. These are

freeby.mesanet.com/7i92_7i77_7i74D.bit
and
freeby.mesanet.com/7i92_7i76_7i74D.bit

( The 7i92.zip file has been updated as well)

Unfortunately, by writing an inappropriate bitfile to the 7I92
(a 5I25 bitfile) You have "bricked" the 7I92, and it can only be recovered by
reprogramming the FPGA via the JTAG connector. This requires
the XIlinx tools and a supported JTAG cable, or sending the card back to
Mesa for repair.

Sending the card back to US will cost me almost as a new one, So I installed Xilinx ISE v14.7 and found that cable ( Xilinx Platform USB Download Cable Jtag Programmer FPGA CPLD C-Mod XC2C64A M102 ) on ebay.
Is that an appropriate cable or not?
Is there any procedure to Unbrick the card myself ?

Yes it can be reprogrammed, the procedure is roughly this:

Power the 7I92, have Ethernet connected to host that can run mesaflash

Connect (hopefully working) JTAG cable

Program FPGA (NOT flash) with a working bitfile (any 7I92 bitfile will work)
using the Xilinx programming tool (Impact)

Once the FPGA has been reprogrammed and the 7I92 has started (Ethernet Link LED on),
from the machine with mesaflash run:

mesaflash --device 7i92 --write 7i92_7i77_7i74D.bit (or whatever 7i92 bitfile you want)

mesaflash --device 7i92 --write 7i92_fallback.bit --fallback

mesaflash --device 7i92 --reload