7i90 questions

PCW,

Would it be possible to get a 7i90 bit file with a couple of step gens, smart serial and a couple of encoder inputs. Needs have changed and we now need an encoder to get accurate positioning. Ill need both spi and epp. Thank you.

JR

Sure, do you have a suggested pinout?

how about ?
p1-stepgens
p2-encoders
p3- sserial

Since i managed to put spi on both sides of the 7i90 flash, what are my options for loading the new bit file. I had no luck getting mesaflash to run on a rspi3 and my desk top has no spi. I have an engineer friend who can load it from Jtag, trying to avoid the drive to the other end of the county. thanks

PCW, i know you are busy, kinda need this in the next couple days.Thanks

I'll try and get to this sometime today, it a mess here because we are moving

well, a day late and a dollar short...
freeby.mesanet.com/7i90.zip

Thanks, quick question. Can the encoder be wired right to the pins on the 7i90 board(its a 5v encoder) or is a board like a 7i33 needed?

You can wire a single ended (TTL) encoder to the 7I90
just keep it away from noisy signals

It appears that the newest version of ssi(version 3) is incompatible with the firmware on the 7i84, as i get a message about 50% of the time to upgrade the 7i84. Im having trouble with halui loading, the ssi timing out , halrun wont load the hm2-rspi driver but hal will when it is invoked from lcnc. How does one upgrade the 7i84 firmware? Any suggestions as to what is causing all of this? Prior to loading the above bit file, there were no problems except an occasional hm2 driver error.

There is no new version of SSLBP nor are there any different 7I84 firmware versions
I expect there is some signal integrity issue with the SPI bus or some thing similar
possibly a cable issue or ground loop issue. It could also be driver related since there seem to be some
SPI clock speed setting issues with the driver (running at 50 MHz for the first transfers)
If the SPI clock runs at 50 MHz you would get quite flaky results and differences in bitfiles since
you would be running right at the limits

If I get time in the next week or so I will write a version of the SPI interface that uses digital filtering on the clock
signal to make the interface less susceptible to poor signal quality, this will require a lower clock rate, perhaps 20 MHz