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.vhd file that splits 7i47 between smartserial and diffential encoders

  • jCandlish
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10 Feb 2017 16:28 #87773 by jCandlish
.vhd file that splits 7i47 between smartserial and diffential encoders was created by jCandlish
My hardware setup is as follows.
7i80hd-16
     |
    P1 ------------ P2 ----------- P3
     |               |              |
    7i48            7i47           empty
                     |
                     | -- 7i73
                     | -- 7i84

I would like to split the 7i47 card between differential encoder and smartserial ports.

a snippet from my current .vhd file looks like
package PIN_SVSS6_8_72_7i48_7i47 is
  constant ModuleID : ModuleIDType :=( 
    (WatchDogTag,       x"00",	ClockLowTag,	x"01",	WatchDogTimeAddr&PadT,		WatchDogNumRegs,	x"00",	WatchDogMPBitMask),
    (MuxedQcountTag,	MQCRev,	ClockLowTag,	x"06",	MuxedQcounterAddr&PadT,		MuxedQCounterNumRegs,   x"00",	MuxedQCounterMPBitMask),
    (MuxedQCountSelTag,	x"00",	ClockLowTag,	x"01",	NullAddr&PadT,			x"00",			x"00",	x"00000000"),
    (PWMTag,		x"00",	ClockHighTag,	x"06",	PWMValAddr&PadT,		PWMNumRegs,		x"00",	PWMMPBitMask),
    (SSerialTag,	x"00",	ClockLowTag,	x"01",	SSerialCommandAddr&PadT,	SSerialNumRegs,		x"10",	SSerialMPBitMask),
    (LEDTag,		x"00",	ClockLowTag,	x"01",	LEDAddr&PadT,			LEDNumRegs,		x"00",	LEDMPBitMask),
    (IOPortTag,		x"00",	ClockLowTag,	x"03",	PortAddr&PadT,			IOPortNumRegs,		x"00",	IOPortMPBitMask),
    (NullTag,		x"00",	NullTag,	x"00",	NullAddr&PadT,			x"00",			x"00",	x"00000000"),
    (NullTag,		x"00",	NullTag,	x"00",	NullAddr&PadT,			x"00",			x"00",	x"00000000"),
    (NullTag,		x"00",	NullTag,	x"00",	NullAddr&PadT,			x"00",			x"00",	x"00000000"),
    (NullTag,		x"00",	NullTag,	x"00",	NullAddr&PadT,			x"00",			x"00",	x"00000000"),
    (NullTag,		x"00",	NullTag,	x"00",	NullAddr&PadT,			x"00",			x"00",	x"00000000"),
    (NullTag,		x"00",	NullTag,	x"00",	NullAddr&PadT,			x"00",			x"00",	x"00000000"),
    (NullTag,		x"00",	NullTag,	x"00",	NullAddr&PadT,			x"00",			x"00",	x"00000000"),
    (NullTag,		x"00",	NullTag,	x"00",	NullAddr&PadT,			x"00",			x"00",	x"00000000"),
    (NullTag,		x"00",	NullTag,	x"00",	NullAddr&PadT,			x"00",			x"00",	x"00000000"),
    (NullTag,		x"00",	NullTag,	x"00",	NullAddr&PadT,			x"00",			x"00",	x"00000000"),
    (NullTag,		x"00",	NullTag,	x"00",	NullAddr&PadT,			x"00",			x"00",	x"00000000"),
    (NullTag,		x"00",	NullTag,	x"00",	NullAddr&PadT,			x"00",			x"00",	x"00000000"),
    (NullTag,		x"00",	NullTag,	x"00",	NullAddr&PadT,			x"00",			x"00",	x"00000000"),
    (NullTag,		x"00",	NullTag,	x"00",	NullAddr&PadT,			x"00",			x"00",	x"00000000"),
    (NullTag,		x"00",	NullTag,	x"00",	NullAddr&PadT,			x"00",			x"00",	x"00000000"),
    (NullTag,		x"00",	NullTag,	x"00",	NullAddr&PadT,			x"00",			x"00",	x"00000000"),
    (NullTag,		x"00",	NullTag,	x"00",	NullAddr&PadT,			x"00",			x"00",	x"00000000"),
    (NullTag,		x"00",	NullTag,	x"00",	NullAddr&PadT,			x"00",			x"00",	x"00000000"),
    (NullTag,		x"00",	NullTag,	x"00",	NullAddr&PadT,			x"00",			x"00",	x"00000000"),
    (NullTag,		x"00",	NullTag,	x"00",	NullAddr&PadT,			x"00",			x"00",	x"00000000"),
    (NullTag,		x"00",	NullTag,	x"00",	NullAddr&PadT,			x"00",			x"00",	x"00000000"),
    (NullTag,		x"00",	NullTag,	x"00",	NullAddr&PadT,			x"00",			x"00",	x"00000000"),
    (NullTag,		x"00",	NullTag,	x"00",	NullAddr&PadT,			x"00",			x"00",	x"00000000"),
    (NullTag,		x"00",	NullTag,	x"00",	NullAddr&PadT,			x"00",			x"00",	x"00000000"),
    (NullTag,		x"00",	NullTag,	x"00",	NullAddr&PadT,			x"00",			x"00",	x"00000000")
		);
		
	
	constant PinDesc : PinDescType :=(
-- 	Base func  sec unit sec func 	                                sec pin

        -- connector P1 -- 7i48
	IOPortTag & x"00" & PWMTag & PWMCEnaPin,   			-- I/O 00
	IOPortTag & x"00" & MuxedQCountTag & MuxedQCountQAPin,		-- I/O 01
	IOPortTag & x"00" & MuxedQCountTag & MuxedQCountQBPin,		-- I/O 02
	IOPortTag & x"00" & MuxedQCountTag & MuxedQCountIDXPin,		-- I/O 03
	IOPortTag & x"01" & MuxedQCountTag & MuxedQCountQAPin,		-- I/O 04
	IOPortTag & x"01" & MuxedQCountTag & MuxedQCountQBPin,		-- I/O 05
	IOPortTag & x"01" & MuxedQCountTag & MuxedQCountIDXPin,		-- I/O 06
	IOPortTag & x"02" & MuxedQCountTag & MuxedQCountQAPin,		-- I/O 07
	IOPortTag & x"02" & MuxedQCountTag & MuxedQCountQBPin,		-- I/O 08
	IOPortTag & x"02" & MuxedQCountTag & MuxedQCountIDXPin,		-- I/O 09
	IOPortTag & x"00" & MuxedQCountSelTag & MuxedQCountSel0Pin,	-- I/O 10
	IOPortTag & x"00" & PWMTag & PWMAOutPin,            		-- I/O 11
	IOPortTag & x"00" & PWMTag & PWMBDirPin,            		-- I/O 12
	IOPortTag & x"01" & PWMTag & PWMAOutPin,            		-- I/O 13
	IOPortTag & x"01" & PWMTag & PWMBDirPin,            		-- I/O 14
	IOPortTag & x"02" & PWMTag & PWMAOutPin,            		-- I/O 15
	IOPortTag & x"02" & PWMTag & PWMBDirPin,            		-- I/O 16
	IOPortTag & x"03" & PWMTag & PWMAOutPin,            		-- I/O 17
	IOPortTag & x"03" & PWMTag & PWMBDirPin,            		-- I/O 18
	IOPortTag & x"04" & PWMTag & PWMAOutPin,            		-- I/O 19
	IOPortTag & x"04" & PWMTag & PWMBDirPin,            		-- I/O 20
	IOPortTag & x"05" & PWMTag & PWMAOutPin,            		-- I/O 21
	IOPortTag & x"05" & PWMTag & PWMBDirPin,            		-- I/O 22
	IOPortTag & x"00" & PWMTag & PWMCEnaPin,        		-- I/O 23

        -- connector P2 -- 7i47
	IOPortTag & x"00" & SSerialTag & SSerialRX0Pin, 		-- I/O 24
	IOPortTag & x"00" & SSerialTag & SSerialRX1Pin, 		-- I/O 25
	IOPortTag & x"00" & SSerialTag & SSerialRX2Pin, 		-- I/O 26
	IOPortTag & x"00" & SSerialTag & SSerialRX3Pin, 		-- I/O 27
	IOPortTag & x"00" & SSerialTag & SSerialTX0Pin, 		-- I/O 28
	IOPortTag & x"00" & SSerialTag & SSerialTXEn0Pin,		-- I/O 29
	IOPortTag & x"00" & SSerialTag & SSerialTX1Pin,			-- I/O 30
	IOPortTag & x"00" & SSerialTag & SSerialTXEn1Pin,		-- I/O 31
	IOPortTag & x"00" & SSerialTag & SSerialTX2Pin, 		-- I/O 32
	IOPortTag & x"00" & SSerialTag & SSerialTXEn2Pin,		-- I/O 33
	IOPortTag & x"00" & SSerialTag & SSerialTX3Pin, 		-- I/O 34
	IOPortTag & x"00" & SSerialTag & SSerialTXEn3Pin,		-- I/O 35
	IOPortTag & x"00" & SSerialTag & SSerialRX4Pin, 		-- I/O 36
	IOPortTag & x"00" & SSerialTag & SSerialRX5Pin,   		-- I/O 37
	IOPortTag & x"00" & SSerialTag & SSerialRX6Pin,   		-- I/O 38
	IOPortTag & x"00" & SSerialTag & SSerialRX7Pin, 		-- I/O 39
	IOPortTag & x"00" & SSerialTag & SSerialTX4Pin,   		-- I/O 40
	IOPortTag & x"00" & SSerialTag & SSerialTXEn4Pin,		-- I/O 41
	IOPortTag & x"00" & SSerialTag & SSerialTX5Pin,			-- I/O 42
	IOPortTag & x"00" & SSerialTag & SSerialTXEn5Pin,		-- I/O 43
	IOPortTag & x"00" & SSerialTag & SSerialTX6Pin, 		-- I/O 44
	IOPortTag & x"00" & SSerialTag & SSerialTXEn6Pin,  		-- I/O 45
	IOPortTag & x"00" & SSerialTag & SSerialTX7Pin,   		-- I/O 46
	IOPortTag & x"00" & SSerialTag & SSerialTXEn7Pin,  		-- I/O 47
                                           
        -- connector P3 -- empty
	IOPortTag & x"00" & NullTag & x"00",				-- I/O 48
	IOPortTag & x"00" & NullTag & x"00",				-- I/O 49
	IOPortTag & x"00" & NullTag & x"00",				-- I/O 50
	IOPortTag & x"00" & NullTag & x"00",				-- I/O 51
	IOPortTag & x"00" & NullTag & x"00",				-- I/O 52
	IOPortTag & x"00" & NullTag & x"00",				-- I/O 53
	IOPortTag & x"00" & NullTag & x"00",				-- I/O 54
	IOPortTag & x"00" & NullTag & x"00",				-- I/O 55
	IOPortTag & x"00" & NullTag & x"00",				-- I/O 56
	IOPortTag & x"00" & NullTag & x"00",				-- I/O 57
	IOPortTag & x"00" & NullTag & x"00",				-- I/O 58
	IOPortTag & x"00" & NullTag & x"00",				-- I/O 59
	IOPortTag & x"00" & NullTag & x"00",				-- I/O 60
	IOPortTag & x"00" & NullTag & x"00",				-- I/O 61
	IOPortTag & x"00" & NullTag & x"00",				-- I/O 62
	IOPortTag & x"00" & NullTag & x"00",				-- I/O 63
	IOPortTag & x"00" & NullTag & x"00",				-- I/O 64
	IOPortTag & x"00" & NullTag & x"00",				-- I/O 65
	IOPortTag & x"00" & NullTag & x"00",				-- I/O 66
	IOPortTag & x"00" & NullTag & x"00",				-- I/O 67
	IOPortTag & x"00" & NullTag & x"00",				-- I/O 68
	IOPortTag & x"00" & NullTag & x"00",				-- I/O 69
	IOPortTag & x"00" & NullTag & x"00",				-- I/O 70
	IOPortTag & x"00" & NullTag & x"00",				-- I/O 71
																		
	emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for IDROM v3
	emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
				
	emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
	emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
	emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
	emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
	emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
	emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
	emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);

end package PIN_SVSS6_8_72_7i48_7i47;

That is probably named wrong, but I do not understand the package naming conventions???

I would like to have 4 smart serial ports (8-11), and the other ports (0-7) as differential i/o, suitable for encoder inputs.

How do I proceed?

Thanks!

.

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  • jCandlish
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10 Feb 2017 21:55 #87782 by jCandlish
Replied by jCandlish on topic .vhd file that splits 7i47 between smartserial and diffential encoders
More generally ... is there a programmatic way to set the value of the "ModuleID : ModuleIDType" array?

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10 Feb 2017 22:49 - 10 Feb 2017 22:49 #87785 by PCW
Replied by PCW on topic .vhd file that splits 7i47 between smartserial and diffential encoders
Theoretically is possible to create the module ID section from the pinout info but it would be a fair amount of trouble

Since the module ID lines are basically all just constants except the number of each module
I usually just copy/paste them from another pinout file and adjust the number of modules
Last edit: 10 Feb 2017 22:49 by PCW.

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11 Feb 2017 09:16 - 11 Feb 2017 09:19 #87806 by jCandlish
Replied by jCandlish on topic .vhd file that splits 7i47 between smartserial and diffential encoders

I usually just copy/paste them from another pinout file and adjust the number of modules


OK. Does this look correct.

File Attachment:

File Name: PIN_SVSS6_....vhd.txt
File Size:11 KB


I hand edited the "ModuleID : ModuleIDType" array, and my .vhd file successfully compiled, but with a lot of warnings.

I basically just replaced a NullTag line with:
    (QcountTag,		x"02",	ClockLowTag,	x"0C",	QcounterAddr&PadT,		QCounterNumRegs,	x"00",	QCounterMPBitMask),

Maybe all the warnings optimized away?

There were very many warnings (I think from the SSerial module) like:
WARNING:PhysDesignRules:367 - The signal
   <ahostmot2/makesserialmod.makesserials[0].asserial/processor/StackRam/Mram_RAM2_RAMD_D1_O> is incomplete. The signal does not drive any load pins in the design.

and (I think from the Encoder module):
WARNING:Xst:1710 - FF/Latch <ahostmot2/makeqcounters.nuseprobe1.makequadcounters[3].qcounterx/timestamplatch_15> (without init value) has a constant value of 0 in block <TopEthernetHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ahostmot2/makeqcounters.nuseprobe1.makequadcounters[3].qcounterx/quadbcnt_1> (without init value) has a constant value of 0 in block <TopEthernetHostMot2>. This FF/Latch will be trimmed during the optimization process.



Maybe they were overcounted in the ModuleID section???

For example, the .PIN file shows 12 Encoders, of which I only specified 9.
Modules in configuration:
  #         Tag  Ver  Clock  Cnt Regs Stride Mult Base
  0    Watchdog    0 100MHz    1    3      0    0 0x0C00
  1 MuxedQCount    3 100MHz    6    5      0    3 0x3500
  2MuxedQCountSel    0 100MHz    1    0      0    0 0x0000
  3      PWMGen    0 200MHz    6    5      0    3 0x4000
  4     SSerial    0 100MHz    1    6     16   60 0x5A00
  5         LED    0 100MHz    1    1      0    0 0x0200
  6      IOPort    0 100MHz    3    5      0   31 0x1000
  7     Encoder    2 100MHz   12    5      0    3 0x3000


PIN   IO# Module         Chan Func
P1-1    0 PWMGen            0 Enable (out)
P1-3    1 MuxedQCount       0 Muxed Phase A (in)
P1-5    2 MuxedQCount       0 Muxed Phase B (in)
P1-7    3 MuxedQCount       0 Muxed Index (in)
P1-9    4 MuxedQCount       1 Muxed Phase A (in)
P1-11   5 MuxedQCount       1 Muxed Phase B (in)
P1-13   6 MuxedQCount       1 Muxed Index (in)
P1-15   7 MuxedQCount       2 Muxed Phase A (in)
P1-17   8 MuxedQCount       2 Muxed Phase B (in)
P1-19   9 MuxedQCount       2 Muxed Index (in)
P1-21  10 MuxedQCountSel    0 Muxed Encoder Select 0 (out)
P1-23  11 PWMGen            0 PWM/Up (out)
P1-25  12 PWMGen            0 Dir/Down (out)
P1-27  13 PWMGen            1 PWM/Up (out)
P1-29  14 PWMGen            1 Dir/Down (out)
P1-31  15 PWMGen            2 PWM/Up (out)
P1-33  16 PWMGen            2 Dir/Down (out)
P1-35  17 PWMGen            3 PWM/Up (out)
P1-37  18 PWMGen            3 Dir/Down (out)
P1-39  19 PWMGen            4 PWM/Up (out)
P1-41  20 PWMGen            4 Dir/Down (out)
P1-43  21 PWMGen            5 PWM/Up (out)
P1-45  22 PWMGen            5 Dir/Down (out)
P1-47  23 PWMGen            0 Enable (out)

PIN   IO# Module         Chan Func
P2-1   24
P2-3   25
P2-5   26
P2-7   27
P2-9   28 SSerial           0 Serial Receive 0 (in)
P2-11  29 Encoder           1 Phase A (in)
P2-13  30 SSerial           0 Serial Receive 1 (in)
P2-15  31 Encoder           1 Phase B (in)
P2-17  32
P2-19  33 Encoder           1 Index (in)
P2-21  34 Encoder           0 Phase A (in)
P2-23  35 Encoder           2 Phase A (in)
P2-25  36 Encoder           0 Phase B (in)
P2-27  37 Encoder           2 Phase B (in)
P2-29  38 Encoder           0 Index (in)
P2-31  39 Encoder           2 Index (in)
P2-33  40
P2-35  41
P2-37  42
P2-39  43
P2-41  44 SSerial           0 Serial Transmit 0 (out)
P2-43  45 SSerial           0 Serial Transmit 1 (out)
P2-45  46
P2-47  47

PIN   IO# Module         Chan Func
P3-1   48
P3-3   49
P3-5   50
P3-7   51
P3-9   52
P3-11  53
P3-13  54
P3-15  55
P3-17  56
P3-19  57
P3-21  58
P3-23  59
P3-25  60
P3-27  61
P3-29  62
P3-31  63
P3-33  64
P3-35  65
P3-37  66
P3-39  67
P3-41  68
P3-43  69
P3-45  70
P3-47  71

NB: it would be nice if the forum allowed attachment of .vhd files.
Attachments:
Last edit: 11 Feb 2017 09:19 by jCandlish.

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11 Feb 2017 13:22 #87815 by PCW
Replied by PCW on topic .vhd file that splits 7i47 between smartserial and diffential encoders
One note:

Due to a LinuxCNC driver limitation you cannot mix muxed and non-muxed ancoders in one configuration
(I think this is fixed in machine kit)

The workaround is to use muxed encoders everywhere
(so your 3 muxed encoders on the 7I47 would be numbered 4,5,6
giving you real hal encoders 8,10,12 and aliased (duplicated) encoders 9,11,13)
The following user(s) said Thank You: jCandlish

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