7i92 7i77 7i74 firmware
- tommylight
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05 Nov 2017 14:44 #101351
by tommylight
7i92 7i77 7i74 firmware was created by tommylight
Hi,
There is a firmware for the above configuration but for some reason it does not work with the 7i74, the rest works fine.
Readhmid shows stepgens on the P1 connector !
Is there another firmware for that setup or am i missing something ?
7i74 to be connected to 7i70, 7i71, 7i73 and 7i84.
Regards,
Tom
There is a firmware for the above configuration but for some reason it does not work with the 7i74, the rest works fine.
Readhmid shows stepgens on the P1 connector !
Is there another firmware for that setup or am i missing something ?
7i74 to be connected to 7i70, 7i71, 7i73 and 7i84.
Regards,
Tom
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05 Nov 2017 15:05 - 05 Nov 2017 15:05 #101352
by PCW
Replied by PCW on topic 7i92 7i77 7i74 firmware
7i92_7i77_7i74D.bit works for me
Did you do a power cycle or
mesaflash --device 7i92 --addr xx.xx.xx.xx --reload
after writing the new firmware?
Did you do a power cycle or
mesaflash --device 7i92 --addr xx.xx.xx.xx --reload
after writing the new firmware?
Last edit: 05 Nov 2017 15:05 by PCW.
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05 Nov 2017 15:19 #101353
by tommylight
Replied by tommylight on topic 7i92 7i77 7i74 firmware
Hi Peter,
Yes i did several times as i am using it for the last 2 days, with that firmware. Still shows stepgens on P1!!!
7i77 works perfectly as i already have all the encoders wired to it and working.
As you might recall i have a similar setup on another machine, the only difference being 7i92 here and 5i25 there. Should make no difference.
How should the sserial_addr look like ? Already used the existing one from the working machine with 5i25, but it complaints about configured 2 addresses and only one exists.
Regards
Yes i did several times as i am using it for the last 2 days, with that firmware. Still shows stepgens on P1!!!
7i77 works perfectly as i already have all the encoders wired to it and working.
As you might recall i have a similar setup on another machine, the only difference being 7i92 here and 5i25 there. Should make no difference.
How should the sserial_addr look like ? Already used the existing one from the working machine with 5i25, but it complaints about configured 2 addresses and only one exists.
Regards
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05 Nov 2017 15:23 #101354
by PCW
Replied by PCW on topic 7i92 7i77 7i74 firmware
md5sum 7i92_7i77_7i74D.bit
e746d759d0f296e84a71a2ba0c10d5ac 7i92_7i77_7i74D.bit
mesaflash --device 7i92 --addr 10.10.10.10 --write 7i92_7i77_7i74D.bit
mesaflash --device 7i92 --addr 10.10.10.10 --reload
mesaflash --device 7i92 --addr 10.10.10.10 --readhmid
Configuration Name: HOSTMOT2
General configuration information:
BoardName : MESA7I92
FPGA Size: 9 KGates
FPGA Pins: 144
Number of IO Ports: 2
Width of one I/O port: 17
Clock Low frequency: 100.0000 MHz
Clock High frequency: 200.0000 MHz
IDROM Type: 3
Instance Stride 0: 4
Instance Stride 1: 64
Register Stride 0: 256
Register Stride 1: 256
Modules in configuration:
Module: DPLL
There are 1 of DPLL in configuration
Version: 0
Registers: 7
BaseAddress: 7000
ClockFrequency: 100.000 MHz
Register Stride: 256 bytes
Instance Stride: 4 bytes
Module: WatchDog
There are 1 of WatchDog in configuration
Version: 0
Registers: 3
BaseAddress: 0C00
ClockFrequency: 100.000 MHz
Register Stride: 256 bytes
Instance Stride: 4 bytes
Module: IOPort
There are 2 of IOPort in configuration
Version: 0
Registers: 5
BaseAddress: 1000
ClockFrequency: 100.000 MHz
Register Stride: 256 bytes
Instance Stride: 4 bytes
Module: MuxedQCount
There are 6 of MuxedQCount in configuration
Version: 3
Registers: 5
BaseAddress: 3600
ClockFrequency: 100.000 MHz
Register Stride: 256 bytes
Instance Stride: 4 bytes
Module: MuxedQCountSel
There are 1 of MuxedQCountSel in configuration
Version: 0
Registers: 0
BaseAddress: 0000
ClockFrequency: 100.000 MHz
Register Stride: 256 bytes
Instance Stride: 4 bytes
Module: SSerial
There are 2 of SSerial in configuration
Version: 0
Registers: 6
BaseAddress: 5B00
ClockFrequency: 100.000 MHz
Register Stride: 256 bytes
Instance Stride: 64 bytes
Module: LED
There are 1 of LED in configuration
Version: 0
Registers: 1
BaseAddress: 0200
ClockFrequency: 100.000 MHz
Register Stride: 256 bytes
Instance Stride: 4 bytes
Configuration pin-out:
IO Connections for P2
Pin# I/O Pri. func Sec. func Chan Pin func Pin Dir
1 0 IOPort SSerial 0 TXEn3 (Out)
14 1 IOPort SSerial 0 TXData3 (Out)
2 2 IOPort SSerial 0 RXData3 (In)
15 3 IOPort SSerial 0 TXData2 (Out)
3 4 IOPort SSerial 0 RXData2 (In)
16 5 IOPort SSerial 0 TXData1 (Out)
4 6 IOPort SSerial 0 RXData1 (In)
17 7 IOPort MuxedQCountSel 0 MuxSel0 (Out)
5 8 IOPort MuxedQCount 0 MuxQ-A (In)
6 9 IOPort MuxedQCount 0 MuxQ-B (In)
7 10 IOPort MuxedQCount 0 MuxQ-IDX (In)
8 11 IOPort MuxedQCount 1 MuxQ-A (In)
9 12 IOPort MuxedQCount 1 MuxQ-B (In)
10 13 IOPort MuxedQCount 1 MuxQ-IDX (In)
11 14 IOPort MuxedQCount 2 MuxQ-A (In)
12 15 IOPort MuxedQCount 2 MuxQ-B (In)
13 16 IOPort MuxedQCount 2 MuxQ-IDX (In)
IO Connections for P1
Pin# I/O Pri. func Sec. func Chan Pin func Pin Dir
1 17 IOPort SSerial 1 RXData1 (In)
14 18 IOPort SSerial 1 RXData2 (In)
2 19 IOPort SSerial 1 RXData3 (In)
15 20 IOPort SSerial 1 RXData4 (In)
3 21 IOPort SSerial 1 TXData1 (Out)
16 22 IOPort SSerial 1 TXData2 (Out)
4 23 IOPort SSerial 1 TXData3 (Out)
17 24 IOPort SSerial 1 TXData4 (Out)
5 25 IOPort SSerial 1 RXData5 (In)
6 26 IOPort SSerial 1 RXData6 (In)
7 27 IOPort None
8 28 IOPort None
9 29 IOPort SSerial 1 TXData5 (Out)
10 30 IOPort SSerial 1 TXData6 (Out)
11 31 IOPort None
12 32 IOPort None
13 33 IOPort None
e746d759d0f296e84a71a2ba0c10d5ac 7i92_7i77_7i74D.bit
mesaflash --device 7i92 --addr 10.10.10.10 --write 7i92_7i77_7i74D.bit
mesaflash --device 7i92 --addr 10.10.10.10 --reload
mesaflash --device 7i92 --addr 10.10.10.10 --readhmid
Configuration Name: HOSTMOT2
General configuration information:
BoardName : MESA7I92
FPGA Size: 9 KGates
FPGA Pins: 144
Number of IO Ports: 2
Width of one I/O port: 17
Clock Low frequency: 100.0000 MHz
Clock High frequency: 200.0000 MHz
IDROM Type: 3
Instance Stride 0: 4
Instance Stride 1: 64
Register Stride 0: 256
Register Stride 1: 256
Modules in configuration:
Module: DPLL
There are 1 of DPLL in configuration
Version: 0
Registers: 7
BaseAddress: 7000
ClockFrequency: 100.000 MHz
Register Stride: 256 bytes
Instance Stride: 4 bytes
Module: WatchDog
There are 1 of WatchDog in configuration
Version: 0
Registers: 3
BaseAddress: 0C00
ClockFrequency: 100.000 MHz
Register Stride: 256 bytes
Instance Stride: 4 bytes
Module: IOPort
There are 2 of IOPort in configuration
Version: 0
Registers: 5
BaseAddress: 1000
ClockFrequency: 100.000 MHz
Register Stride: 256 bytes
Instance Stride: 4 bytes
Module: MuxedQCount
There are 6 of MuxedQCount in configuration
Version: 3
Registers: 5
BaseAddress: 3600
ClockFrequency: 100.000 MHz
Register Stride: 256 bytes
Instance Stride: 4 bytes
Module: MuxedQCountSel
There are 1 of MuxedQCountSel in configuration
Version: 0
Registers: 0
BaseAddress: 0000
ClockFrequency: 100.000 MHz
Register Stride: 256 bytes
Instance Stride: 4 bytes
Module: SSerial
There are 2 of SSerial in configuration
Version: 0
Registers: 6
BaseAddress: 5B00
ClockFrequency: 100.000 MHz
Register Stride: 256 bytes
Instance Stride: 64 bytes
Module: LED
There are 1 of LED in configuration
Version: 0
Registers: 1
BaseAddress: 0200
ClockFrequency: 100.000 MHz
Register Stride: 256 bytes
Instance Stride: 4 bytes
Configuration pin-out:
IO Connections for P2
Pin# I/O Pri. func Sec. func Chan Pin func Pin Dir
1 0 IOPort SSerial 0 TXEn3 (Out)
14 1 IOPort SSerial 0 TXData3 (Out)
2 2 IOPort SSerial 0 RXData3 (In)
15 3 IOPort SSerial 0 TXData2 (Out)
3 4 IOPort SSerial 0 RXData2 (In)
16 5 IOPort SSerial 0 TXData1 (Out)
4 6 IOPort SSerial 0 RXData1 (In)
17 7 IOPort MuxedQCountSel 0 MuxSel0 (Out)
5 8 IOPort MuxedQCount 0 MuxQ-A (In)
6 9 IOPort MuxedQCount 0 MuxQ-B (In)
7 10 IOPort MuxedQCount 0 MuxQ-IDX (In)
8 11 IOPort MuxedQCount 1 MuxQ-A (In)
9 12 IOPort MuxedQCount 1 MuxQ-B (In)
10 13 IOPort MuxedQCount 1 MuxQ-IDX (In)
11 14 IOPort MuxedQCount 2 MuxQ-A (In)
12 15 IOPort MuxedQCount 2 MuxQ-B (In)
13 16 IOPort MuxedQCount 2 MuxQ-IDX (In)
IO Connections for P1
Pin# I/O Pri. func Sec. func Chan Pin func Pin Dir
1 17 IOPort SSerial 1 RXData1 (In)
14 18 IOPort SSerial 1 RXData2 (In)
2 19 IOPort SSerial 1 RXData3 (In)
15 20 IOPort SSerial 1 RXData4 (In)
3 21 IOPort SSerial 1 TXData1 (Out)
16 22 IOPort SSerial 1 TXData2 (Out)
4 23 IOPort SSerial 1 TXData3 (Out)
17 24 IOPort SSerial 1 TXData4 (Out)
5 25 IOPort SSerial 1 RXData5 (In)
6 26 IOPort SSerial 1 RXData6 (In)
7 27 IOPort None
8 28 IOPort None
9 29 IOPort SSerial 1 TXData5 (Out)
10 30 IOPort SSerial 1 TXData6 (Out)
11 31 IOPort None
12 32 IOPort None
13 33 IOPort None
The following user(s) said Thank You: tommylight
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05 Nov 2017 15:44 #101355
by tommylight
Replied by tommylight on topic 7i92 7i77 7i74 firmware
Thank you very much Peter,
i have 2 bit files with the same exact name but with different md5sum !!!
All is working now.
Thanks.
i have 2 bit files with the same exact name but with different md5sum !!!
All is working now.
Thanks.
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05 Nov 2017 17:30 #101359
by PCW
Replied by PCW on topic 7i92 7i77 7i74 firmware
It might be that an older 7I92 distribution zip file had some bad firmware images
that one I used was the latest.
that one I used was the latest.
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