7i76e Bit File Problem

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micknucam
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25 Oct 2020 21:08 #187218 by micknucam

7i76e Bit File Problem was created by micknucam

PCW Supplied me with this bit file 7i76e_7i76x3D.bit the Pathpilot loads and runs the 7i76 part works fine have tested the encoder 0 and the 5 step gens. I then progressed to testing the encoders on the P1 and P2 Connectors.

I had a hunch they are all outputs so i tested each pin with a step gen and they work as outputs can some one check the bit file i think its not what i wanted.

[HOSTMOT2]
DRIVER=hm2_eth
BOARD=7i76e
DRIVER_PARAMS="board_ip=10.10.10.10 config=num_encoders=2 num_pwmgens=0 num_3pwmgens=0 num_stepgens=6 sserial_port_0=21xxxx"
BITFILE0=mesa/7i76e_7i76x3D.bit
DPLL_TIMER_NUMBER = 1
DPLL_TIMER_US= -100

This is what i was looking for

IO Connections for P1
Pin# I/O Pri. func Sec. func Chan Pin func Pin Dir

1 0 IOPort StepGen 0 Dir/Table2 (Out)
14 1 IOPort StepGen 0 Step/Table1 (Out)
2 2 IOPort StepGen 1 Dir/Table2 (Out)
15 3 IOPort StepGen 1 Step/Table1 (Out)
3 4 IOPort StepGen 2 Dir/Table2 (Out)
16 5 IOPort StepGen 2 Step/Table1 (Out)
4 6 IOPort StepGen 3 Dir/Table2 (Out)
17 7 IOPort StepGen 3 Step/Table1 (Out)
5 8 IOPort StepGen 4 Dir/Table2 (Out)
6 9 IOPort StepGen 4 Step/Table1 (Out)
7 10 IOPort SSerial 0 TXData1 (Out)
8 11 IOPort SSerial 0 RXData1 (In)
9 12 IOPort SSerial 0 TXData2 (Out)
10 13 IOPort SSerial 0 RXData2 (In)
11 14 IOPort QCount 0 Quad-IDX (In)
12 15 IOPort QCount 0 Quad-B (In)
13 16 IOPort QCount 0 Quad-A (In)

IO Connections for P2
Pin# I/O Pri. func Sec. func Chan Pin func Pin Dir

1 0 IOPort StepGen 0 Dir/Table2 (Out)
14 1 IOPort StepGen 0 Step/Table1 (Out)
2 2 IOPort StepGen 1 Dir/Table2 (Out)
15 3 IOPort StepGen 1 Step/Table1 (Out)
3 4 IOPort StepGen 2 Dir/Table2 (Out)
16 5 IOPort StepGen 2 Step/Table1 (Out)
4 6 IOPort StepGen 3 Dir/Table2 (Out)
17 7 IOPort StepGen 3 Step/Table1 (Out)
5 8 IOPort StepGen 4 Dir/Table2 (Out)
6 9 IOPort StepGen 4 Step/Table1 (Out)
7 10 IOPort SSerial 0 TXData1 (Out)
8 11 IOPort SSerial 0 RXData1 (In)
9 12 IOPort SSerial 0 TXData2 (Out)
10 13 IOPort SSerial 0 RXData2 (In)
11 14 IOPort QCount 0 Quad-IDX (In)
12 15 IOPort QCount 0 Quad-B (In)
13 16 IOPort QCount 0 Quad-A (In)

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PCW
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25 Oct 2020 21:24 #187223 by PCW

Replied by PCW on topic 7i76e Bit File Problem

Not sure what the issue is. This is what I get with readhmid
which looks correct to me:

mesaflash --device 7i76e --addr 10.10.10.10 --readhmid
Configuration Name: HOSTMOT2

General configuration information:

  BoardName : MESA7I76
  FPGA Size: 16 KGates
  FPGA Pins: 256
  Number of IO Ports: 3
  Width of one I/O port: 17
  Clock Low frequency: 100.0000 MHz
  Clock High frequency: 200.0000 MHz
  IDROM Type: 3
  Instance Stride 0: 4
  Instance Stride 1: 64
  Register Stride 0: 256
  Register Stride 1: 256

Modules in configuration:

  Module: DPLL
  There are 1 of DPLL in configuration
  Version: 0
  Registers: 7
  BaseAddress: 7000
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

  Module: WatchDog
  There are 1 of WatchDog in configuration
  Version: 0
  Registers: 3
  BaseAddress: 0C00
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

  Module: IOPort
  There are 3 of IOPort in configuration
  Version: 0
  Registers: 5
  BaseAddress: 1000
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

  Module: StepGen
  There are 15 of StepGen in configuration
  Version: 2
  Registers: 10
  BaseAddress: 2000
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

  Module: QCount
  There are 3 of QCount in configuration
  Version: 2
  Registers: 5
  BaseAddress: 3000
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

  Module: SSerial
  There are 1 of SSerial in configuration
  Version: 0
  Registers: 6
  BaseAddress: 5A00
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 64 bytes

  Module: LED
  There are 1 of LED in configuration
  Version: 0
  Registers: 1
  BaseAddress: 0200
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

Configuration pin-out:

IO Connections for on-card
Pin#                  I/O   Pri. func    Sec. func       Chan      Pin func        Pin Dir

TB2 4,5                 0   IOPort       StepGen          0        Dir/Table2      (Out)
TB2 2,3                 1   IOPort       StepGen          0        Step/Table1     (Out)
TB2 10,11               2   IOPort       StepGen          1        Dir/Table2      (Out)
TB2 8,9                 3   IOPort       StepGen          1        Step/Table1     (Out)
TB2 16,17               4   IOPort       StepGen          2        Dir/Table2      (Out)
TB2 14,15               5   IOPort       StepGen          2        Step/Table1     (Out)
TB2 22,23               6   IOPort       StepGen          3        Dir/Table2      (Out)
TB2 20,21               7   IOPort       StepGen          3        Step/Table1     (Out)
TB3 4,5                 8   IOPort       StepGen          4        Dir/Table2      (Out)
TB3 2,3                 9   IOPort       StepGen          4        Step/Table1     (Out)
Internal               10   IOPort       SSerial          0        TXData0         (Out)
Internal               11   IOPort       SSerial          0        RXData0         (In)
TB3 18,19              12   IOPort       SSerial          0        TXData1         (Out)
TB3 16,17              13   IOPort       SSerial          0        RXData1         (In)
TB3 13,14              14   IOPort       QCount           0        Quad-IDX        (In)
TB3 10,11              15   IOPort       QCount           0        Quad-B          (In)
TB3 7,8                16   IOPort       QCount           0        Quad-A          (In)

IO Connections for P1
Pin#                  I/O   Pri. func    Sec. func       Chan      Pin func        Pin Dir

 1                     17   IOPort       StepGen          5        Dir/Table2      (Out)
14                     18   IOPort       StepGen          5        Step/Table1     (Out)
 2                     19   IOPort       StepGen          6        Dir/Table2      (Out)
15                     20   IOPort       StepGen          6        Step/Table1     (Out)
 3                     21   IOPort       StepGen          7        Dir/Table2      (Out)
16                     22   IOPort       StepGen          7        Step/Table1     (Out)
 4                     23   IOPort       StepGen          8        Dir/Table2      (Out)
17                     24   IOPort       StepGen          8        Step/Table1     (Out)
 5                     25   IOPort       StepGen          9        Dir/Table2      (Out)
 6                     26   IOPort       StepGen          9        Step/Table1     (Out)
 7                     27   IOPort       SSerial          0        TXData2         (Out)
 8                     28   IOPort       SSerial          0        RXData2         (In)
 9                     29   IOPort       SSerial          0        TXData3         (Out)
10                     30   IOPort       SSerial          0        RXData3         (In)
11                     31   IOPort       QCount           1        Quad-IDX        (In)
12                     32   IOPort       QCount           1        Quad-B          (In)
13                     33   IOPort       QCount           1        Quad-A          (In)

IO Connections for P2
Pin#                  I/O   Pri. func    Sec. func       Chan      Pin func        Pin Dir

 1                     34   IOPort       StepGen         10        Dir/Table2      (Out)
14                     35   IOPort       StepGen         10        Step/Table1     (Out)
 2                     36   IOPort       StepGen         11        Dir/Table2      (Out)
15                     37   IOPort       StepGen         11        Step/Table1     (Out)
 3                     38   IOPort       StepGen         12        Dir/Table2      (Out)
16                     39   IOPort       StepGen         12        Step/Table1     (Out)
 4                     40   IOPort       StepGen         13        Dir/Table2      (Out)
17                     41   IOPort       StepGen         13        Step/Table1     (Out)
 5                     42   IOPort       StepGen         14        Dir/Table2      (Out)
 6                     43   IOPort       StepGen         14        Step/Table1     (Out)
 7                     44   IOPort       SSerial          0        TXData4         (Out)
 8                     45   IOPort       SSerial          0        RXData4         (In)
 9                     46   IOPort       SSerial          0        TXData5         (Out)
10                     47   IOPort       SSerial          0        RXData5         (In)
11                     48   IOPort       QCount           2        Quad-IDX        (In)
12                     49   IOPort       QCount           2        Quad-B          (In)
13                     50   IOPort       QCount           2        Quad-A          (In)

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micknucam
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25 Oct 2020 21:40 #187229 by micknucam

Replied by micknucam on topic 7i76e Bit File Problem

Hmm I’ll try that on my card I don’t know what the problem is either it when I connect a signal to the encoder pin 12 it pulls lots of current I’ve done this through a limiting resistor ! Do you think I have a jumper in the wrong place

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BeagleBrainz
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25 Oct 2020 21:49 #187232 by BeagleBrainz

Replied by BeagleBrainz on topic 7i76e Bit File Problem

Just a dumb question, but you did flash your card with the firmware.

When you run readhmid are you getting the same results as PCW ?

The following user(s) said Thank You: micknucam

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PCW
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25 Oct 2020 22:06 - 25 Oct 2020 22:22 #187235 by PCW

Replied by PCW on topic 7i76e Bit File Problem

DB25 pin 12? (This is _not_ HDR26 pin 12)

Note that bare FPGA pins are easily damaged by excess voltages and currents
( Simply shorting an I/O pin for frame ground in a system with high frequency ground
loop currents say from a VFD or step motor drive can destroy the input clamp diodes )

If you do connect external devices like encoders to the bare FPGA pins, you
should at have at the minimum, a series resistor to limit input currents (say 220 Ohm)

Last edit: 25 Oct 2020 22:22 by PCW.

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micknucam
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25 Oct 2020 22:20 #187238 by micknucam

Replied by micknucam on topic 7i76e Bit File Problem

Yes

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micknucam
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25 Oct 2020 22:28 #187241 by micknucam

Replied by micknucam on topic 7i76e Bit File Problem

Ok I have done this on a 7i76 and it’s been working fine ! I connected a 5v signal generator through a 1k resistor onto the pin I haven’t shorted anything it’s sat on my test bench no vfd or servos

Can you show me which pins the encoder is on the DB25 Connector as I copied what I have working on the 7i76 hopefully no harm done yet I have been very careful

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PCW
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25 Oct 2020 22:31 - 25 Oct 2020 22:32 #187243 by PCW

Replied by PCW on topic 7i76e Bit File Problem

The encoders are on DB25 pins 11,12,13 (HDR26 pins 21,23,25)
(mesaflash shows the DB25 pins)

Last edit: 25 Oct 2020 22:32 by PCW.

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micknucam
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25 Oct 2020 22:50 #187248 by micknucam

Replied by micknucam on topic 7i76e Bit File Problem

Thanks I’ve got it working now the 1k resistor was to high used 240 and it’s reading the pulses from my sig gen I had read a post from yourself before and have been a bit to cautious better that way than a scrap board , I mentioned the wrong PIN numbers

Thanks for your help

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7i76e Bit File Problem

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