Testing funny PWM with 7i93 + 7i52s
29 Jul 2021 05:10 #216187
by Zenduin
Testing funny PWM with 7i93 + 7i52s was created by Zenduin
I'm retrofitting a 90s era SWI TRAK CNC2 that uses a 15.5Khz PWM signal (50% = 0 drive) for servo control. I want to hook up my oscilloscope to check that PWM signal is what I'm expecting before actually hooking it up to the machine and attempting to tune everything. I have my scope connected to pin 19 for channel 1 and pin 20 for channel 2 on connector P3 (7i52s) which should be connected to pwmgen.02 for Z. I increased the Ferror variables so I wouldn't get a follow error when jogging, then jogged the Z axis, and saw no signal on the scope. I know the scope works since I just tested it earlier today. So where did I go wrong?
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29 Jul 2021 14:26 #216224
by PCW
Replied by PCW on topic Testing funny PWM with 7i93 + 7i52s
1. Do you have firmware for a 7I52S loaded in the 7I93?
2. Are the PWMgens setup and enabled? (proper scale and frequency and
offset mode enabled)
3. Note that to avoid saturation you need to bound the PID output with
the PID's maxoutput pin so you don't lose the PWM signal by allowing
the PWM value to meet or exceed the PWM scale setting
Running the command:
halcmd show all hm2_7i93.0.pwm
When linuxCNC is running, should show all the PWM settings
2. Are the PWMgens setup and enabled? (proper scale and frequency and
offset mode enabled)
3. Note that to avoid saturation you need to bound the PID output with
the PID's maxoutput pin so you don't lose the PWM signal by allowing
the PWM value to meet or exceed the PWM scale setting
Running the command:
halcmd show all hm2_7i93.0.pwm
When linuxCNC is running, should show all the PWM settings
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29 Jul 2021 15:43 - 29 Jul 2021 16:49 #216233
by Zenduin
Replied by Zenduin on topic Testing funny PWM with 7i93 + 7i52s
1. Yes, but I MAY have done something wrong in compiling it...2. PWMgen scale is 10, Offset-mode is enabled, PID MaxOutput is set to 2.5
halcmd show all hm2_7i93.pwm shows nothing, but:I tried your advice from a previous thread, also without success.
mesaflash --device 7i93 --readhmid
Configuration Name: HOSTMOT2
General configuration information:
BoardName : MESA7I93
FPGA Size: 9 KGates
FPGA Pins: 144
Number of IO Ports: 2
Width of one I/O port: 24
Clock Low frequency: 100.0000 MHz
Clock High frequency: 200.0000 MHz
IDROM Type: 3
Instance Stride 0: 4
Instance Stride 1: 64
Register Stride 0: 256
Register Stride 1: 256
Modules in configuration:
Module: DPLL
There are 1 of DPLL in configuration
Version: 0
Registers: 7
BaseAddress: 7000
ClockFrequency: 100.000 MHz
Register Stride: 256 bytes
Instance Stride: 4 bytes
Module: WatchDog
There are 1 of WatchDog in configuration
Version: 0
Registers: 3
BaseAddress: 0C00
ClockFrequency: 100.000 MHz
Register Stride: 256 bytes
Instance Stride: 4 bytes
Module: IOPort
There are 2 of IOPort in configuration
Version: 0
Registers: 5
BaseAddress: 1000
ClockFrequency: 100.000 MHz
Register Stride: 256 bytes
Instance Stride: 4 bytes
Module: MuxedQCount
There are 6 of MuxedQCount in configuration
Version: 4
Registers: 5
BaseAddress: 3600
ClockFrequency: 100.000 MHz
Register Stride: 256 bytes
Instance Stride: 4 bytes
Module: MuxedQCountSel
There are 1 of MuxedQCountSel in configuration
Version: 0
Registers: 0
BaseAddress: 0000
ClockFrequency: 100.000 MHz
Register Stride: 256 bytes
Instance Stride: 4 bytes
Module: PWM
There are 6 of PWM in configuration
Version: 0
Registers: 5
BaseAddress: 4100
ClockFrequency: 200.000 MHz
Register Stride: 256 bytes
Instance Stride: 4 bytes
Module: LED
There are 1 of LED in configuration
Version: 0
Registers: 1
BaseAddress: 0200
ClockFrequency: 100.000 MHz
Register Stride: 256 bytes
Instance Stride: 4 bytes
Configuration pin-out:
IO Connections for P2
Pin# I/O Pri. func Sec. func Chan Pin func Pin Dir
1 0 IOPort PWM 0 /Enable (Out)
3 1 IOPort MuxedQCount 0 MuxQ-A (In)
5 2 IOPort MuxedQCount 0 MuxQ-B (In)
7 3 IOPort MuxedQCount 0 MuxQ-IDX (In)
9 4 IOPort MuxedQCount 1 MuxQ-A (In)
11 5 IOPort MuxedQCount 1 MuxQ-B (In)
13 6 IOPort MuxedQCount 1 MuxQ-IDX (In)
15 7 IOPort MuxedQCount 2 MuxQ-A (In)
17 8 IOPort MuxedQCount 2 MuxQ-B (In)
19 9 IOPort MuxedQCount 2 MuxQ-IDX (In)
21 10 IOPort MuxedQCountSel 0 MuxSel0 (Out)
23 11 IOPort PWM 0 PWM (Out)
25 12 IOPort PWM 0 Dir (Out)
27 13 IOPort PWM 1 PWM (Out)
29 14 IOPort PWM 1 Dir (Out)
31 15 IOPort PWM 2 PWM (Out)
33 16 IOPort PWM 2 Dir (Out)
35 17 IOPort PWM 3 PWM (Out)
37 18 IOPort PWM 3 Dir (Out)
39 19 IOPort PWM 4 PWM (Out)
41 20 IOPort PWM 4 Dir (Out)
43 21 IOPort PWM 5 PWM (Out)
45 22 IOPort PWM 5 Dir (Out)
47 23 IOPort PWM 0 /Enable (Out)
IO Connections for P1
Pin# I/O Pri. func Sec. func Chan Pin func Pin Dir
1 24 IOPort None
3 25 IOPort None
5 26 IOPort None
7 27 IOPort None
9 28 IOPort None
11 29 IOPort None
13 30 IOPort None
15 31 IOPort None
17 32 IOPort None
19 33 IOPort None
21 34 IOPort None
23 35 IOPort None
25 36 IOPort None
27 37 IOPort None
29 38 IOPort None
31 39 IOPort None
33 40 IOPort None
35 41 IOPort None
37 42 IOPort None
39 43 IOPort None
41 44 IOPort None
43 45 IOPort None
45 46 IOPort None
47 47 IOPort None halcmd show all hm2_7i93.pwm shows nothing, but:
halcmd show all hm2_7i93
Loaded HAL Components:
ID Type Name PID State
Component Pins:
Owner Type Dir Value Name
30 float IN 100 hm2_7i93.0.dpll.01.timer-us
30 float IN 100 hm2_7i93.0.dpll.02.timer-us
30 float IN 100 hm2_7i93.0.dpll.03.timer-us
30 float IN 100 hm2_7i93.0.dpll.04.timer-us
30 float IN 1 hm2_7i93.0.dpll.base-freq-khz
30 u32 OUT 0x0000002A hm2_7i93.0.dpll.ddsize
30 float OUT 10.81137 hm2_7i93.0.dpll.phase-error-us
30 u32 IN 0x00400000 hm2_7i93.0.dpll.plimit
30 u32 OUT 0x00000018 hm2_7i93.0.dpll.prescale
30 u32 IN 0x000007D0 hm2_7i93.0.dpll.time-const
30 s32 OUT 0 hm2_7i93.0.encoder.00.count
30 s32 OUT 0 hm2_7i93.0.encoder.00.count-latched
30 bit I/O FALSE hm2_7i93.0.encoder.00.index-enable
30 bit OUT TRUE hm2_7i93.0.encoder.00.input-a
30 bit OUT TRUE hm2_7i93.0.encoder.00.input-b
30 bit OUT FALSE hm2_7i93.0.encoder.00.input-index
30 bit IN FALSE hm2_7i93.0.encoder.00.latch-enable
30 bit IN FALSE hm2_7i93.0.encoder.00.latch-polarity
30 float OUT 0 hm2_7i93.0.encoder.00.position ==> motor.00.pos-fb
30 float OUT 0 hm2_7i93.0.encoder.00.position-latched
30 bit OUT FALSE hm2_7i93.0.encoder.00.quad-error
30 bit IN FALSE hm2_7i93.0.encoder.00.quad-error-enable
30 s32 OUT 0 hm2_7i93.0.encoder.00.rawcounts
30 s32 OUT 0 hm2_7i93.0.encoder.00.rawlatch
30 bit IN FALSE hm2_7i93.0.encoder.00.reset
30 float OUT 0 hm2_7i93.0.encoder.00.velocity
30 float OUT 0 hm2_7i93.0.encoder.00.velocity-rpm
30 s32 OUT 0 hm2_7i93.0.encoder.01.count
30 s32 OUT 0 hm2_7i93.0.encoder.01.count-latched
30 bit I/O FALSE hm2_7i93.0.encoder.01.index-enable
30 bit OUT FALSE hm2_7i93.0.encoder.01.input-a
30 bit OUT FALSE hm2_7i93.0.encoder.01.input-b
30 bit OUT TRUE hm2_7i93.0.encoder.01.input-index
30 bit IN FALSE hm2_7i93.0.encoder.01.latch-enable
30 bit IN FALSE hm2_7i93.0.encoder.01.latch-polarity
30 float OUT -0 hm2_7i93.0.encoder.01.position ==> motor.01.pos-fb
30 float OUT -0 hm2_7i93.0.encoder.01.position-latched
30 bit OUT FALSE hm2_7i93.0.encoder.01.quad-error
30 bit IN FALSE hm2_7i93.0.encoder.01.quad-error-enable
30 s32 OUT 0 hm2_7i93.0.encoder.01.rawcounts
30 s32 OUT 0 hm2_7i93.0.encoder.01.rawlatch
30 bit IN FALSE hm2_7i93.0.encoder.01.reset
30 float OUT 0 hm2_7i93.0.encoder.01.velocity
30 float OUT 0 hm2_7i93.0.encoder.01.velocity-rpm
30 s32 OUT 0 hm2_7i93.0.encoder.02.count
30 s32 OUT 0 hm2_7i93.0.encoder.02.count-latched
30 bit I/O FALSE hm2_7i93.0.encoder.02.index-enable
30 bit OUT TRUE hm2_7i93.0.encoder.02.input-a
30 bit OUT TRUE hm2_7i93.0.encoder.02.input-b
30 bit OUT TRUE hm2_7i93.0.encoder.02.input-index
30 bit IN FALSE hm2_7i93.0.encoder.02.latch-enable
30 bit IN FALSE hm2_7i93.0.encoder.02.latch-polarity
30 float OUT 0 hm2_7i93.0.encoder.02.position ==> motor.02.pos-fb
30 float OUT 0 hm2_7i93.0.encoder.02.position-latched
30 bit OUT FALSE hm2_7i93.0.encoder.02.quad-error
30 bit IN FALSE hm2_7i93.0.encoder.02.quad-error-enable
30 s32 OUT 0 hm2_7i93.0.encoder.02.rawcounts
30 s32 OUT 0 hm2_7i93.0.encoder.02.rawlatch
30 bit IN FALSE hm2_7i93.0.encoder.02.reset
30 float OUT 0 hm2_7i93.0.encoder.02.velocity
30 float OUT 0 hm2_7i93.0.encoder.02.velocity-rpm
30 s32 OUT 0 hm2_7i93.0.encoder.03.count
30 s32 OUT 0 hm2_7i93.0.encoder.03.count-latched
30 bit I/O FALSE hm2_7i93.0.encoder.03.index-enable
30 bit OUT FALSE hm2_7i93.0.encoder.03.input-a
30 bit OUT FALSE hm2_7i93.0.encoder.03.input-b
30 bit OUT TRUE hm2_7i93.0.encoder.03.input-index
30 bit IN FALSE hm2_7i93.0.encoder.03.latch-enable
30 bit IN FALSE hm2_7i93.0.encoder.03.latch-polarity
30 float OUT 0 hm2_7i93.0.encoder.03.position
30 float OUT 0 hm2_7i93.0.encoder.03.position-latched
30 bit OUT FALSE hm2_7i93.0.encoder.03.quad-error
30 bit IN FALSE hm2_7i93.0.encoder.03.quad-error-enable
30 s32 OUT 0 hm2_7i93.0.encoder.03.rawcounts
30 s32 OUT 0 hm2_7i93.0.encoder.03.rawlatch
30 bit IN FALSE hm2_7i93.0.encoder.03.reset
30 float OUT 0 hm2_7i93.0.encoder.03.velocity
30 float OUT 0 hm2_7i93.0.encoder.03.velocity-rpm
30 s32 OUT 0 hm2_7i93.0.encoder.04.count
30 s32 OUT 0 hm2_7i93.0.encoder.04.count-latched
30 bit I/O FALSE hm2_7i93.0.encoder.04.index-enable
30 bit OUT TRUE hm2_7i93.0.encoder.04.input-a
30 bit OUT FALSE hm2_7i93.0.encoder.04.input-b
30 bit OUT FALSE hm2_7i93.0.encoder.04.input-index
30 bit IN FALSE hm2_7i93.0.encoder.04.latch-enable
30 bit IN FALSE hm2_7i93.0.encoder.04.latch-polarity
30 float OUT 0 hm2_7i93.0.encoder.04.position
30 float OUT 0 hm2_7i93.0.encoder.04.position-latched
30 bit OUT FALSE hm2_7i93.0.encoder.04.quad-error
30 bit IN FALSE hm2_7i93.0.encoder.04.quad-error-enable
30 s32 OUT 1 hm2_7i93.0.encoder.04.rawcounts
30 s32 OUT 1 hm2_7i93.0.encoder.04.rawlatch
30 bit IN FALSE hm2_7i93.0.encoder.04.reset
30 float OUT 0 hm2_7i93.0.encoder.04.velocity
30 float OUT 0 hm2_7i93.0.encoder.04.velocity-rpm
30 s32 OUT 0 hm2_7i93.0.encoder.05.count
30 s32 OUT 0 hm2_7i93.0.encoder.05.count-latched
30 bit I/O FALSE hm2_7i93.0.encoder.05.index-enable
30 bit OUT FALSE hm2_7i93.0.encoder.05.input-a
30 bit OUT FALSE hm2_7i93.0.encoder.05.input-b
30 bit OUT TRUE hm2_7i93.0.encoder.05.input-index
30 bit IN FALSE hm2_7i93.0.encoder.05.latch-enable
30 bit IN FALSE hm2_7i93.0.encoder.05.latch-polarity
30 float OUT 0 hm2_7i93.0.encoder.05.position
30 float OUT 0 hm2_7i93.0.encoder.05.position-latched
30 bit OUT FALSE hm2_7i93.0.encoder.05.quad-error
30 bit IN FALSE hm2_7i93.0.encoder.05.quad-error-enable
30 s32 OUT 0 hm2_7i93.0.encoder.05.rawcounts
30 s32 OUT 0 hm2_7i93.0.encoder.05.rawlatch
30 bit IN FALSE hm2_7i93.0.encoder.05.reset
30 float OUT 0 hm2_7i93.0.encoder.05.velocity
30 float OUT 0 hm2_7i93.0.encoder.05.velocity-rpm
30 bit IN FALSE hm2_7i93.0.encoder.hires-timestamp
30 u32 IN 0x007F2815 hm2_7i93.0.encoder.muxed-sample-frequency
30 u32 IN 0x00000000 hm2_7i93.0.encoder.muxed-skew
30 s32 IN -1 hm2_7i93.0.encoder.timer-number
30 bit OUT FALSE hm2_7i93.0.gpio.000.in
30 bit OUT TRUE hm2_7i93.0.gpio.000.in_not
30 bit OUT FALSE hm2_7i93.0.gpio.001.in
30 bit OUT TRUE hm2_7i93.0.gpio.001.in_not
30 bit OUT FALSE hm2_7i93.0.gpio.002.in
30 bit OUT TRUE hm2_7i93.0.gpio.002.in_not
30 bit OUT FALSE hm2_7i93.0.gpio.003.in
30 bit OUT TRUE hm2_7i93.0.gpio.003.in_not
30 bit OUT FALSE hm2_7i93.0.gpio.004.in
30 bit OUT TRUE hm2_7i93.0.gpio.004.in_not
30 bit OUT FALSE hm2_7i93.0.gpio.005.in
30 bit OUT TRUE hm2_7i93.0.gpio.005.in_not
30 bit OUT FALSE hm2_7i93.0.gpio.006.in
30 bit OUT TRUE hm2_7i93.0.gpio.006.in_not
30 bit OUT FALSE hm2_7i93.0.gpio.007.in
30 bit OUT TRUE hm2_7i93.0.gpio.007.in_not
30 bit OUT FALSE hm2_7i93.0.gpio.008.in
30 bit OUT TRUE hm2_7i93.0.gpio.008.in_not
30 bit OUT FALSE hm2_7i93.0.gpio.009.in
30 bit OUT TRUE hm2_7i93.0.gpio.009.in_not
30 bit OUT TRUE hm2_7i93.0.gpio.010.in
30 bit OUT FALSE hm2_7i93.0.gpio.010.in_not
30 bit OUT FALSE hm2_7i93.0.gpio.011.in
30 bit OUT TRUE hm2_7i93.0.gpio.011.in_not
30 bit OUT FALSE hm2_7i93.0.gpio.012.in
30 bit OUT TRUE hm2_7i93.0.gpio.012.in_not
30 bit OUT FALSE hm2_7i93.0.gpio.013.in
30 bit OUT TRUE hm2_7i93.0.gpio.013.in_not
30 bit OUT FALSE hm2_7i93.0.gpio.014.in
30 bit OUT TRUE hm2_7i93.0.gpio.014.in_not
30 bit OUT FALSE hm2_7i93.0.gpio.015.in
30 bit OUT TRUE hm2_7i93.0.gpio.015.in_not
30 bit OUT FALSE hm2_7i93.0.gpio.016.in
30 bit OUT TRUE hm2_7i93.0.gpio.016.in_not
30 bit OUT FALSE hm2_7i93.0.gpio.017.in
30 bit OUT TRUE hm2_7i93.0.gpio.017.in_not
30 bit OUT FALSE hm2_7i93.0.gpio.018.in
30 bit OUT TRUE hm2_7i93.0.gpio.018.in_not
30 bit OUT FALSE hm2_7i93.0.gpio.019.in
30 bit OUT TRUE hm2_7i93.0.gpio.019.in_not
30 bit OUT FALSE hm2_7i93.0.gpio.020.in
30 bit OUT TRUE hm2_7i93.0.gpio.020.in_not
30 bit OUT FALSE hm2_7i93.0.gpio.021.in
30 bit OUT TRUE hm2_7i93.0.gpio.021.in_not
30 bit OUT FALSE hm2_7i93.0.gpio.022.in
30 bit OUT TRUE hm2_7i93.0.gpio.022.in_not
30 bit OUT FALSE hm2_7i93.0.gpio.023.in
30 bit OUT TRUE hm2_7i93.0.gpio.023.in_not
30 bit OUT TRUE hm2_7i93.0.gpio.024.in
30 bit OUT FALSE hm2_7i93.0.gpio.024.in_not
30 bit IN FALSE hm2_7i93.0.gpio.024.out
30 bit OUT TRUE hm2_7i93.0.gpio.025.in
30 bit OUT FALSE hm2_7i93.0.gpio.025.in_not
30 bit IN FALSE hm2_7i93.0.gpio.025.out
30 bit OUT TRUE hm2_7i93.0.gpio.026.in
30 bit OUT FALSE hm2_7i93.0.gpio.026.in_not
30 bit IN FALSE hm2_7i93.0.gpio.026.out
30 bit OUT TRUE hm2_7i93.0.gpio.027.in
30 bit OUT FALSE hm2_7i93.0.gpio.027.in_not
30 bit IN FALSE hm2_7i93.0.gpio.027.out
30 bit OUT TRUE hm2_7i93.0.gpio.028.in
30 bit OUT FALSE hm2_7i93.0.gpio.028.in_not
30 bit IN FALSE hm2_7i93.0.gpio.028.out
30 bit OUT TRUE hm2_7i93.0.gpio.029.in
30 bit OUT FALSE hm2_7i93.0.gpio.029.in_not
30 bit IN FALSE hm2_7i93.0.gpio.029.out
30 bit OUT TRUE hm2_7i93.0.gpio.030.in
30 bit OUT FALSE hm2_7i93.0.gpio.030.in_not
30 bit IN FALSE hm2_7i93.0.gpio.030.out
30 bit OUT TRUE hm2_7i93.0.gpio.031.in
30 bit OUT FALSE hm2_7i93.0.gpio.031.in_not
30 bit IN FALSE hm2_7i93.0.gpio.031.out
30 bit OUT TRUE hm2_7i93.0.gpio.032.in
30 bit OUT FALSE hm2_7i93.0.gpio.032.in_not
30 bit IN FALSE hm2_7i93.0.gpio.032.out
30 bit OUT TRUE hm2_7i93.0.gpio.033.in
30 bit OUT FALSE hm2_7i93.0.gpio.033.in_not
30 bit IN FALSE hm2_7i93.0.gpio.033.out
30 bit OUT TRUE hm2_7i93.0.gpio.034.in
30 bit OUT FALSE hm2_7i93.0.gpio.034.in_not
30 bit IN FALSE hm2_7i93.0.gpio.034.out
30 bit OUT TRUE hm2_7i93.0.gpio.035.in
30 bit OUT FALSE hm2_7i93.0.gpio.035.in_not
30 bit IN FALSE hm2_7i93.0.gpio.035.out
30 bit OUT TRUE hm2_7i93.0.gpio.036.in
30 bit OUT FALSE hm2_7i93.0.gpio.036.in_not
30 bit IN FALSE hm2_7i93.0.gpio.036.out
30 bit OUT TRUE hm2_7i93.0.gpio.037.in
30 bit OUT FALSE hm2_7i93.0.gpio.037.in_not
30 bit IN FALSE hm2_7i93.0.gpio.037.out
30 bit OUT TRUE hm2_7i93.0.gpio.038.in
30 bit OUT FALSE hm2_7i93.0.gpio.038.in_not
30 bit IN FALSE hm2_7i93.0.gpio.038.out
30 bit OUT TRUE hm2_7i93.0.gpio.039.in
30 bit OUT FALSE hm2_7i93.0.gpio.039.in_not
30 bit IN FALSE hm2_7i93.0.gpio.039.out
30 bit OUT TRUE hm2_7i93.0.gpio.040.in
30 bit OUT FALSE hm2_7i93.0.gpio.040.in_not
30 bit IN FALSE hm2_7i93.0.gpio.040.out
30 bit OUT TRUE hm2_7i93.0.gpio.041.in
30 bit OUT FALSE hm2_7i93.0.gpio.041.in_not
30 bit IN FALSE hm2_7i93.0.gpio.041.out
30 bit OUT TRUE hm2_7i93.0.gpio.042.in
30 bit OUT FALSE hm2_7i93.0.gpio.042.in_not
30 bit IN FALSE hm2_7i93.0.gpio.042.out
30 bit OUT TRUE hm2_7i93.0.gpio.043.in
30 bit OUT FALSE hm2_7i93.0.gpio.043.in_not
30 bit IN FALSE hm2_7i93.0.gpio.043.out
30 bit OUT TRUE hm2_7i93.0.gpio.044.in
30 bit OUT FALSE hm2_7i93.0.gpio.044.in_not
30 bit IN FALSE hm2_7i93.0.gpio.044.out
30 bit OUT TRUE hm2_7i93.0.gpio.045.in
30 bit OUT FALSE hm2_7i93.0.gpio.045.in_not
30 bit IN FALSE hm2_7i93.0.gpio.045.out
30 bit OUT TRUE hm2_7i93.0.gpio.046.in
30 bit OUT FALSE hm2_7i93.0.gpio.046.in_not
30 bit IN FALSE hm2_7i93.0.gpio.046.out
30 bit OUT TRUE hm2_7i93.0.gpio.047.in
30 bit OUT FALSE hm2_7i93.0.gpio.047.in_not
30 bit IN FALSE hm2_7i93.0.gpio.047.out
30 bit IN FALSE hm2_7i93.0.led.CR01
30 bit IN FALSE hm2_7i93.0.led.CR02
30 bit IN FALSE hm2_7i93.0.led.CR03
30 bit IN FALSE hm2_7i93.0.led.CR04
30 bit OUT FALSE hm2_7i93.0.packet-error
30 bit OUT FALSE hm2_7i93.0.packet-error-exceeded
30 s32 OUT 0 hm2_7i93.0.packet-error-level
30 bit IN TRUE hm2_7i93.0.pwmgen.00.enable <== emcmot.00.enable
30 float IN 0 hm2_7i93.0.pwmgen.00.value <== motor.00.command
30 bit IN TRUE hm2_7i93.0.pwmgen.01.enable <== emcmot.01.enable
30 float IN 0 hm2_7i93.0.pwmgen.01.value <== motor.01.command
30 bit IN TRUE hm2_7i93.0.pwmgen.02.enable <== emcmot.02.enable
30 float IN 0 hm2_7i93.0.pwmgen.02.value <== motor.02.command
30 bit IN FALSE hm2_7i93.0.pwmgen.03.enable
30 float IN 0 hm2_7i93.0.pwmgen.03.value
30 bit IN FALSE hm2_7i93.0.pwmgen.04.enable
30 float IN 0 hm2_7i93.0.pwmgen.04.value
30 bit IN FALSE hm2_7i93.0.pwmgen.05.enable
30 float IN 0 hm2_7i93.0.pwmgen.05.value
30 s32 OUT 0 hm2_7i93.0.read-request.time
30 s32 OUT 126666 hm2_7i93.0.read.time
30 bit I/O FALSE hm2_7i93.0.watchdog.has_bit
30 s32 OUT 33148 hm2_7i93.0.write.time
Pin Aliases:
Alias Original Name
Signals:
Type Value Name (linked to)
Parameters:
Owner Type Dir Value Name
30 bit RW FALSE hm2_7i93.0.encoder.00.counter-mode
30 bit RW TRUE hm2_7i93.0.encoder.00.filter
30 bit RW FALSE hm2_7i93.0.encoder.00.index-invert
30 bit RW FALSE hm2_7i93.0.encoder.00.index-mask
30 bit RW FALSE hm2_7i93.0.encoder.00.index-mask-invert
30 float RW 81920 hm2_7i93.0.encoder.00.scale
30 bit RW FALSE hm2_7i93.0.encoder.00.sel0.invert_output
30 bit RW FALSE hm2_7i93.0.encoder.00.sel0.is_opendrain
30 float RW 0.5 hm2_7i93.0.encoder.00.vel-timeout
30 bit RW FALSE hm2_7i93.0.encoder.01.counter-mode
30 bit RW TRUE hm2_7i93.0.encoder.01.filter
30 bit RW FALSE hm2_7i93.0.encoder.01.index-invert
30 bit RW FALSE hm2_7i93.0.encoder.01.index-mask
30 bit RW FALSE hm2_7i93.0.encoder.01.index-mask-invert
30 float RW -81920 hm2_7i93.0.encoder.01.scale
30 float RW 0.5 hm2_7i93.0.encoder.01.vel-timeout
30 bit RW FALSE hm2_7i93.0.encoder.02.counter-mode
30 bit RW TRUE hm2_7i93.0.encoder.02.filter
30 bit RW FALSE hm2_7i93.0.encoder.02.index-invert
30 bit RW FALSE hm2_7i93.0.encoder.02.index-mask
30 bit RW FALSE hm2_7i93.0.encoder.02.index-mask-invert
30 float RW 81920 hm2_7i93.0.encoder.02.scale
30 float RW 0.5 hm2_7i93.0.encoder.02.vel-timeout
30 bit RW FALSE hm2_7i93.0.encoder.03.counter-mode
30 bit RW TRUE hm2_7i93.0.encoder.03.filter
30 bit RW FALSE hm2_7i93.0.encoder.03.index-invert
30 bit RW FALSE hm2_7i93.0.encoder.03.index-mask
30 bit RW FALSE hm2_7i93.0.encoder.03.index-mask-invert
30 float RW 1 hm2_7i93.0.encoder.03.scale
30 float RW 0.5 hm2_7i93.0.encoder.03.vel-timeout
30 bit RW FALSE hm2_7i93.0.encoder.04.counter-mode
30 bit RW TRUE hm2_7i93.0.encoder.04.filter
30 bit RW FALSE hm2_7i93.0.encoder.04.index-invert
30 bit RW FALSE hm2_7i93.0.encoder.04.index-mask
30 bit RW FALSE hm2_7i93.0.encoder.04.index-mask-invert
30 float RW 1 hm2_7i93.0.encoder.04.scale
30 float RW 0.5 hm2_7i93.0.encoder.04.vel-timeout
30 bit RW FALSE hm2_7i93.0.encoder.05.counter-mode
30 bit RW TRUE hm2_7i93.0.encoder.05.filter
30 bit RW FALSE hm2_7i93.0.encoder.05.index-invert
30 bit RW FALSE hm2_7i93.0.encoder.05.index-mask
30 bit RW FALSE hm2_7i93.0.encoder.05.index-mask-invert
30 float RW 1 hm2_7i93.0.encoder.05.scale
30 float RW 0.5 hm2_7i93.0.encoder.05.vel-timeout
30 bit RW FALSE hm2_7i93.0.gpio.024.invert_output
30 bit RW FALSE hm2_7i93.0.gpio.024.is_opendrain
30 bit RW FALSE hm2_7i93.0.gpio.024.is_output
30 bit RW FALSE hm2_7i93.0.gpio.025.invert_output
30 bit RW FALSE hm2_7i93.0.gpio.025.is_opendrain
30 bit RW FALSE hm2_7i93.0.gpio.025.is_output
30 bit RW FALSE hm2_7i93.0.gpio.026.invert_output
30 bit RW FALSE hm2_7i93.0.gpio.026.is_opendrain
30 bit RW FALSE hm2_7i93.0.gpio.026.is_output
30 bit RW FALSE hm2_7i93.0.gpio.027.invert_output
30 bit RW FALSE hm2_7i93.0.gpio.027.is_opendrain
30 bit RW FALSE hm2_7i93.0.gpio.027.is_output
30 bit RW FALSE hm2_7i93.0.gpio.028.invert_output
30 bit RW FALSE hm2_7i93.0.gpio.028.is_opendrain
30 bit RW FALSE hm2_7i93.0.gpio.028.is_output
30 bit RW FALSE hm2_7i93.0.gpio.029.invert_output
30 bit RW FALSE hm2_7i93.0.gpio.029.is_opendrain
30 bit RW FALSE hm2_7i93.0.gpio.029.is_output
30 bit RW FALSE hm2_7i93.0.gpio.030.invert_output
30 bit RW FALSE hm2_7i93.0.gpio.030.is_opendrain
30 bit RW FALSE hm2_7i93.0.gpio.030.is_output
30 bit RW FALSE hm2_7i93.0.gpio.031.invert_output
30 bit RW FALSE hm2_7i93.0.gpio.031.is_opendrain
30 bit RW FALSE hm2_7i93.0.gpio.031.is_output
30 bit RW FALSE hm2_7i93.0.gpio.032.invert_output
30 bit RW FALSE hm2_7i93.0.gpio.032.is_opendrain
30 bit RW FALSE hm2_7i93.0.gpio.032.is_output
30 bit RW FALSE hm2_7i93.0.gpio.033.invert_output
30 bit RW FALSE hm2_7i93.0.gpio.033.is_opendrain
30 bit RW FALSE hm2_7i93.0.gpio.033.is_output
30 bit RW FALSE hm2_7i93.0.gpio.034.invert_output
30 bit RW FALSE hm2_7i93.0.gpio.034.is_opendrain
30 bit RW FALSE hm2_7i93.0.gpio.034.is_output
30 bit RW FALSE hm2_7i93.0.gpio.035.invert_output
30 bit RW FALSE hm2_7i93.0.gpio.035.is_opendrain
30 bit RW FALSE hm2_7i93.0.gpio.035.is_output
30 bit RW FALSE hm2_7i93.0.gpio.036.invert_output
30 bit RW FALSE hm2_7i93.0.gpio.036.is_opendrain
30 bit RW FALSE hm2_7i93.0.gpio.036.is_output
30 bit RW FALSE hm2_7i93.0.gpio.037.invert_output
30 bit RW FALSE hm2_7i93.0.gpio.037.is_opendrain
30 bit RW FALSE hm2_7i93.0.gpio.037.is_output
30 bit RW FALSE hm2_7i93.0.gpio.038.invert_output
30 bit RW FALSE hm2_7i93.0.gpio.038.is_opendrain
30 bit RW FALSE hm2_7i93.0.gpio.038.is_output
30 bit RW FALSE hm2_7i93.0.gpio.039.invert_output
30 bit RW FALSE hm2_7i93.0.gpio.039.is_opendrain
30 bit RW FALSE hm2_7i93.0.gpio.039.is_output
30 bit RW FALSE hm2_7i93.0.gpio.040.invert_output
30 bit RW FALSE hm2_7i93.0.gpio.040.is_opendrain
30 bit RW FALSE hm2_7i93.0.gpio.040.is_output
30 bit RW FALSE hm2_7i93.0.gpio.041.invert_output
30 bit RW FALSE hm2_7i93.0.gpio.041.is_opendrain
30 bit RW FALSE hm2_7i93.0.gpio.041.is_output
30 bit RW FALSE hm2_7i93.0.gpio.042.invert_output
30 bit RW FALSE hm2_7i93.0.gpio.042.is_opendrain
30 bit RW FALSE hm2_7i93.0.gpio.042.is_output
30 bit RW FALSE hm2_7i93.0.gpio.043.invert_output
30 bit RW FALSE hm2_7i93.0.gpio.043.is_opendrain
30 bit RW FALSE hm2_7i93.0.gpio.043.is_output
30 bit RW FALSE hm2_7i93.0.gpio.044.invert_output
30 bit RW FALSE hm2_7i93.0.gpio.044.is_opendrain
30 bit RW FALSE hm2_7i93.0.gpio.044.is_output
30 bit RW FALSE hm2_7i93.0.gpio.045.invert_output
30 bit RW FALSE hm2_7i93.0.gpio.045.is_opendrain
30 bit RW FALSE hm2_7i93.0.gpio.045.is_output
30 bit RW FALSE hm2_7i93.0.gpio.046.invert_output
30 bit RW FALSE hm2_7i93.0.gpio.046.is_opendrain
30 bit RW FALSE hm2_7i93.0.gpio.046.is_output
30 bit RW FALSE hm2_7i93.0.gpio.047.invert_output
30 bit RW FALSE hm2_7i93.0.gpio.047.is_opendrain
30 bit RW FALSE hm2_7i93.0.gpio.047.is_output
30 bit RW FALSE hm2_7i93.0.io_error
30 s32 RO 1 hm2_7i93.0.packet-error-decrement
30 s32 RW 2 hm2_7i93.0.packet-error-increment
30 s32 RW 10 hm2_7i93.0.packet-error-limit
30 s32 RW 80 hm2_7i93.0.packet-read-timeout
30 bit RW FALSE hm2_7i93.0.pwmgen.00.0.enable.invert_output
30 bit RW FALSE hm2_7i93.0.pwmgen.00.0.enable.is_opendrain
30 bit RW FALSE hm2_7i93.0.pwmgen.00.1.enable.invert_output
30 bit RW FALSE hm2_7i93.0.pwmgen.00.1.enable.is_opendrain
30 bit RW TRUE hm2_7i93.0.pwmgen.00.offset-mode
30 bit RW FALSE hm2_7i93.0.pwmgen.00.out0.invert_output
30 bit RW FALSE hm2_7i93.0.pwmgen.00.out0.is_opendrain
30 bit RW FALSE hm2_7i93.0.pwmgen.00.out1.invert_output
30 bit RW FALSE hm2_7i93.0.pwmgen.00.out1.is_opendrain
30 s32 RW 1 hm2_7i93.0.pwmgen.00.output-type
30 float RW 10 hm2_7i93.0.pwmgen.00.scale
30 bit RW TRUE hm2_7i93.0.pwmgen.01.offset-mode
30 bit RW FALSE hm2_7i93.0.pwmgen.01.out0.invert_output
30 bit RW FALSE hm2_7i93.0.pwmgen.01.out0.is_opendrain
30 bit RW FALSE hm2_7i93.0.pwmgen.01.out1.invert_output
30 bit RW FALSE hm2_7i93.0.pwmgen.01.out1.is_opendrain
30 s32 RW 1 hm2_7i93.0.pwmgen.01.output-type
30 float RW 10 hm2_7i93.0.pwmgen.01.scale
30 bit RW TRUE hm2_7i93.0.pwmgen.02.offset-mode
30 bit RW FALSE hm2_7i93.0.pwmgen.02.out0.invert_output
30 bit RW FALSE hm2_7i93.0.pwmgen.02.out0.is_opendrain
30 bit RW FALSE hm2_7i93.0.pwmgen.02.out1.invert_output
30 bit RW FALSE hm2_7i93.0.pwmgen.02.out1.is_opendrain
30 s32 RW 1 hm2_7i93.0.pwmgen.02.output-type
30 float RW 10 hm2_7i93.0.pwmgen.02.scale
30 bit RW FALSE hm2_7i93.0.pwmgen.03.offset-mode
30 bit RW FALSE hm2_7i93.0.pwmgen.03.out0.invert_output
30 bit RW FALSE hm2_7i93.0.pwmgen.03.out0.is_opendrain
30 bit RW FALSE hm2_7i93.0.pwmgen.03.out1.invert_output
30 bit RW FALSE hm2_7i93.0.pwmgen.03.out1.is_opendrain
30 s32 RW 1 hm2_7i93.0.pwmgen.03.output-type
30 float RW 1 hm2_7i93.0.pwmgen.03.scale
30 bit RW FALSE hm2_7i93.0.pwmgen.04.offset-mode
30 bit RW FALSE hm2_7i93.0.pwmgen.04.out0.invert_output
30 bit RW FALSE hm2_7i93.0.pwmgen.04.out0.is_opendrain
30 bit RW FALSE hm2_7i93.0.pwmgen.04.out1.invert_output
30 bit RW FALSE hm2_7i93.0.pwmgen.04.out1.is_opendrain
30 s32 RW 1 hm2_7i93.0.pwmgen.04.output-type
30 float RW 1 hm2_7i93.0.pwmgen.04.scale
30 bit RW FALSE hm2_7i93.0.pwmgen.05.offset-mode
30 bit RW FALSE hm2_7i93.0.pwmgen.05.out0.invert_output
30 bit RW FALSE hm2_7i93.0.pwmgen.05.out0.is_opendrain
30 bit RW FALSE hm2_7i93.0.pwmgen.05.out1.invert_output
30 bit RW FALSE hm2_7i93.0.pwmgen.05.out1.is_opendrain
30 s32 RW 1 hm2_7i93.0.pwmgen.05.output-type
30 float RW 1 hm2_7i93.0.pwmgen.05.scale
30 u32 RW 0x00004E20 hm2_7i93.0.pwmgen.pdm_frequency
30 u32 RW 0x00003C8C hm2_7i93.0.pwmgen.pwm_frequency
30 s32 RW 0 hm2_7i93.0.read-request.tmax
30 bit RO FALSE hm2_7i93.0.read-request.tmax-increased
30 s32 RW 625253 hm2_7i93.0.read.tmax
30 bit RO FALSE hm2_7i93.0.read.tmax-increased
30 u32 RW 0x004C4B40 hm2_7i93.0.watchdog.timeout_ns
30 s32 RW 349885 hm2_7i93.0.write.tmax
30 bit RO FALSE hm2_7i93.0.write.tmax-increased
Parameter Aliases:
Alias Original Name
hm2_7i93.0.encoder.00.sel0.invert_output hm2_7i93.0.gpio.010.invert_output
hm2_7i93.0.encoder.00.sel0.is_opendrain hm2_7i93.0.gpio.010.is_opendrain
hm2_7i93.0.pwmgen.00.0.enable.invert_output hm2_7i93.0.gpio.000.invert_output
hm2_7i93.0.pwmgen.00.0.enable.is_opendrain hm2_7i93.0.gpio.000.is_opendrain
hm2_7i93.0.pwmgen.00.1.enable.invert_output hm2_7i93.0.gpio.023.invert_output
hm2_7i93.0.pwmgen.00.1.enable.is_opendrain hm2_7i93.0.gpio.023.is_opendrain
hm2_7i93.0.pwmgen.00.out0.invert_output hm2_7i93.0.gpio.011.invert_output
hm2_7i93.0.pwmgen.00.out0.is_opendrain hm2_7i93.0.gpio.011.is_opendrain
hm2_7i93.0.pwmgen.00.out1.invert_output hm2_7i93.0.gpio.012.invert_output
hm2_7i93.0.pwmgen.00.out1.is_opendrain hm2_7i93.0.gpio.012.is_opendrain
hm2_7i93.0.pwmgen.01.out0.invert_output hm2_7i93.0.gpio.013.invert_output
hm2_7i93.0.pwmgen.01.out0.is_opendrain hm2_7i93.0.gpio.013.is_opendrain
hm2_7i93.0.pwmgen.01.out1.invert_output hm2_7i93.0.gpio.014.invert_output
hm2_7i93.0.pwmgen.01.out1.is_opendrain hm2_7i93.0.gpio.014.is_opendrain
hm2_7i93.0.pwmgen.02.out0.invert_output hm2_7i93.0.gpio.015.invert_output
hm2_7i93.0.pwmgen.02.out0.is_opendrain hm2_7i93.0.gpio.015.is_opendrain
hm2_7i93.0.pwmgen.02.out1.invert_output hm2_7i93.0.gpio.016.invert_output
hm2_7i93.0.pwmgen.02.out1.is_opendrain hm2_7i93.0.gpio.016.is_opendrain
hm2_7i93.0.pwmgen.03.out0.invert_output hm2_7i93.0.gpio.017.invert_output
hm2_7i93.0.pwmgen.03.out0.is_opendrain hm2_7i93.0.gpio.017.is_opendrain
hm2_7i93.0.pwmgen.03.out1.invert_output hm2_7i93.0.gpio.018.invert_output
hm2_7i93.0.pwmgen.03.out1.is_opendrain hm2_7i93.0.gpio.018.is_opendrain
hm2_7i93.0.pwmgen.04.out0.invert_output hm2_7i93.0.gpio.019.invert_output
hm2_7i93.0.pwmgen.04.out0.is_opendrain hm2_7i93.0.gpio.019.is_opendrain
hm2_7i93.0.pwmgen.04.out1.invert_output hm2_7i93.0.gpio.020.invert_output
hm2_7i93.0.pwmgen.04.out1.is_opendrain hm2_7i93.0.gpio.020.is_opendrain
hm2_7i93.0.pwmgen.05.out0.invert_output hm2_7i93.0.gpio.021.invert_output
hm2_7i93.0.pwmgen.05.out0.is_opendrain hm2_7i93.0.gpio.021.is_opendrain
hm2_7i93.0.pwmgen.05.out1.invert_output hm2_7i93.0.gpio.022.invert_output
hm2_7i93.0.pwmgen.05.out1.is_opendrain hm2_7i93.0.gpio.022.is_opendrain
Exported Functions:
Owner CodeAddr Arg FP Users Name
00030 b5d99dc0 01e70378 YES 1 hm2_7i93.0.read
00030 b5d99d40 01e70378 YES 0 hm2_7i93.0.read-request
00030 b5d99c04 01e70378 YES 1 hm2_7i93.0.write
Realtime Threads:
Period FP Name ( Time, Max-Time )2. As mentioned before, you need to have a 50% duty cycle offset in the PWM and bound the PWM to perhaps 10 and 90%
duty cycle, This will require using the scale component with an offset and using the PID max-output parameter to limits its range
For example set the PWM scale to 100 (so its in %)
add an offset of 50 to the PID output via the scale comp
and bound the PID output to +-40 via the maxoutput parameter
Last edit: 29 Jul 2021 16:49 by Zenduin. Reason: fixing code tags
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29 Jul 2021 16:12 - 29 Jul 2021 16:32 #216237
by PCW
Replied by PCW on topic Testing funny PWM with 7i93 + 7i52s
All the PWM values are 0 so you shoud get 15 KHz square waves
Are you sure you are not looking at a DIR signal?
(for hardware that uses offset mode, the firmware should be
built without DIR pins, they are not harmful but not useful either)
Are you sure you are not looking at a DIR signal?
(for hardware that uses offset mode, the firmware should be
built without DIR pins, they are not harmful but not useful either)
Last edit: 29 Jul 2021 16:32 by PCW.
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29 Jul 2021 18:34 #216249
by Zenduin
Replied by Zenduin on topic Testing funny PWM with 7i93 + 7i52s
Not only was it a DIR signal, it was the DIR signal for pwmgen.05!! WHOOPS =D
Fixed now:
I'm also getting a signal now! Progress is good! =)
Fixed now:
IO Connections for P2
Pin# I/O Pri. func Sec. func Chan Pin func Pin Dir
1 0 IOPort PWM 0 /Enable (Out)
3 1 IOPort MuxedQCount 0 MuxQ-A (In)
5 2 IOPort MuxedQCount 0 MuxQ-B (In)
7 3 IOPort MuxedQCount 0 MuxQ-IDX (In)
9 4 IOPort MuxedQCount 1 MuxQ-A (In)
11 5 IOPort MuxedQCount 1 MuxQ-B (In)
13 6 IOPort MuxedQCount 1 MuxQ-IDX (In)
15 7 IOPort MuxedQCount 2 MuxQ-A (In)
17 8 IOPort MuxedQCount 2 MuxQ-B (In)
19 9 IOPort MuxedQCount 2 MuxQ-IDX (In)
21 10 IOPort MuxedQCountSel 0 MuxSel0 (Out)
23 11 IOPort None
25 12 IOPort None
27 13 IOPort None
29 14 IOPort None
31 15 IOPort None
33 16 IOPort None
35 17 IOPort None
37 18 IOPort PWM 2 PWM (Out)
39 19 IOPort None
41 20 IOPort PWM 1 PWM (Out)
43 21 IOPort None
45 22 IOPort PWM 0 PWM (Out)
47 23 IOPort PWM 0 /Enable (Out)I'm also getting a signal now! Progress is good! =)
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