Good Morning!
I ve tried starting to generate a custom bitfile myself, but i have no chance to run ISE Design Suite on my PC.
Maybe the Wiki-Page for generating custom bitfiles need some attention/update. Xilinx wants me to use there newer products. So until now i dont know what to download/install exactly. Tried ISE System Edition 14.7 in a Virtual Machine (which failes on my PC).
So maybe someone could be so kind and compile a custom bitfile for me?
I have a 6i25: (currently flashed 5i25_7i77_7i85sp.bit to run my 7i77D and use a PWM-Pin from P2 with a breakout-board)
My bit-wishlist:
Code:
7i77D on P3: (no changes)
Configuration pin-out:
IO Connections for P3
Pin# I/O Pri. func Sec. func Chan Pin func Pin Dir
1 0 IOPort SSerial 0 TXEn3 (Out)
14 1 IOPort SSerial 0 TXData3 (Out)
2 2 IOPort SSerial 0 RXData3 (In)
15 3 IOPort SSerial 0 TXData2 (Out)
3 4 IOPort SSerial 0 RXData2 (In)
16 5 IOPort SSerial 0 TXData1 (Out)
4 6 IOPort SSerial 0 RXData1 (In)
17 7 IOPort MuxedQCountSel 0 MuxSel0 (Out)
5 8 IOPort MuxedQCount 0 MuxQ-A (In)
6 9 IOPort MuxedQCount 0 MuxQ-B (In)
7 10 IOPort MuxedQCount 0 MuxQ-IDX (In)
8 11 IOPort MuxedQCount 1 MuxQ-A (In)
9 12 IOPort MuxedQCount 1 MuxQ-B (In)
10 13 IOPort MuxedQCount 1 MuxQ-IDX (In)
11 14 IOPort MuxedQCount 2 MuxQ-A (In)
12 15 IOPort MuxedQCount 2 MuxQ-B (In)
13 16 IOPort MuxedQCount 2 MuxQ-IDX (In)
Breakout-Board on P2:
(Pin numbers doesnt matter, i will connect as it comes out)
- 2 sserial-channels
- 2 stepgens
- 2 pwmgens
- rest should be useable for gerneral IO. (if possible, if not: sserial)
IO Connections for P2
Pin# I/O Pri. func Sec. func
1 17 IOPort SSerial
14 18 IOPort SSerial
2 19 IOPort SSerial
15 20 IOPort SSerial
3 21 IOPort StepGen
16 22 IOPort StepGen
4 23 IOPort StepGen
17 24 IOPort StepGen
5 25 IOPort PWMGen
6 26 IOPort PWMGen
7 27 IOPort PWMGen
8 28 IOPort PWMGen
9 29 IOPort IO
10 30 IOPort IO
11 31 IOPort IO
12 32 IOPort IO
13 33 IOPort IO
Thanks!
Greets from Bavaria.