Mesaflash --dbname# <name>

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JT
Topic Author
Away
Administrator

30 Mar 2023 13:02 #267908 by JT

Mesaflash --dbname# <name> was created by JT

I have a 7i92t with a 7i76 on P2 and when I issue the following I get:

john@cave:~$ mesaflash --device 7i92t --addr 10.10.10.10 --readhmid --dbname1 7i76
Configuration Name: HOSTMOT2

General configuration information:

  BoardName : MESA7I92
  FPGA Size: 20 KGates
  FPGA Pins: 256
  Number of IO Ports: 2
  Width of one I/O port: 17
  Clock Low frequency: 100.0000 MHz
  Clock High frequency: 180.0000 MHz
  IDROM Type: 3
  Instance Stride 0: 4
  Instance Stride 1: 64
  Register Stride 0: 256
  Register Stride 1: 256

Modules in configuration:

  Module: DPLL
  There are 1 of DPLL in configuration
  Version: 0
  Registers: 7
  BaseAddress: 7000
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

  Module: WatchDog
  There are 1 of WatchDog in configuration
  Version: 0
  Registers: 3
  BaseAddress: 0C00
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

  Module: IOPort
  There are 2 of IOPort in configuration
  Version: 0
  Registers: 5
  BaseAddress: 1000
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

  Module: QCount
  There are 2 of QCount in configuration
  Version: 2
  Registers: 5
  BaseAddress: 3000
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

  Module: SSerial
  There are 1 of SSerial in configuration
  Version: 0
  Registers: 6
  BaseAddress: 5B00
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 64 bytes

  Module: StepGen
  There are 10 of StepGen in configuration
  Version: 2
  Registers: 10
  BaseAddress: 2000
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

  Module: LED
  There are 1 of LED in configuration
  Version: 0
  Registers: 1
  BaseAddress: 0200
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

Configuration pin-out:

IO Connections for P2 -> 7I76
Pin#                  I/O   Pri. func    Sec. func        Chan     Sec. Pin func   Sec. Pin Dir

TB2-4,5                 0   IOPort       StepGen          0        Dir/Table2      (Out)
TB2-2,3                 1   IOPort       StepGen          0        Step/Table1     (Out)
TB2-10,11               2   IOPort       StepGen          1        Dir/Table2      (Out)
TB2-8,9                 3   IOPort       StepGen          1        Step/Table1     (Out)
TB2-16,17               4   IOPort       StepGen          2        Dir/Table2      (Out)
TB2-14,15               5   IOPort       StepGen          2        Step/Table1     (Out)
TB2-22,23               6   IOPort       StepGen          3        Dir/Table2      (Out)
TB2-20,21               7   IOPort       StepGen          3        Step/Table1     (Out)
TB3-4,5                 8   IOPort       StepGen          4        Dir/Table2      (Out)
TB3-2,3                 9   IOPort       StepGen          4        Step/Table1     (Out)
Internal-Field-IO      10   IOPort       SSerial          0        TXData0         (Out)
Internal-Field-IO      11   IOPort       SSerial          0        RXData0         (In)
TB3-18,19              12   IOPort       SSerial          0        TXData1         (Out)
TB3-16,17              13   IOPort       SSerial          0        RXData1         (In)
TB3-13,14              14   IOPort       QCount           0        Quad-IDX        (In)
TB3-10,11              15   IOPort       QCount           0        Quad-B          (In)
TB3-7,8                16   IOPort       QCount           0        Quad-A          (In)

IO Connections for P1
DB25 pin#             I/O   Pri. func    Sec. func        Chan     Sec. Pin func   Sec. Pin Dir

 1                     17   IOPort       StepGen          5        Dir/Table2      (Out)
14                     18   IOPort       StepGen          5        Step/Table1     (Out)
 2                     19   IOPort       StepGen          6        Dir/Table2      (Out)
15                     20   IOPort       StepGen          6        Step/Table1     (Out)
 3                     21   IOPort       StepGen          7        Dir/Table2      (Out)
16                     22   IOPort       StepGen          7        Step/Table1     (Out)
 4                     23   IOPort       StepGen          8        Dir/Table2      (Out)
17                     24   IOPort       StepGen          8        Step/Table1     (Out)
 5                     25   IOPort       StepGen          9        Dir/Table2      (Out)
 6                     26   IOPort       StepGen          9        Step/Table1     (Out)
 7                     27   IOPort       SSerial          0        TXData2         (Out)
 8                     28   IOPort       SSerial          0        RXData2         (In)
 9                     29   IOPort       SSerial          0        TXData3         (Out)
10                     30   IOPort       SSerial          0        RXData3         (In)
11                     31   IOPort       QCount           1        Quad-IDX        (In)
12                     32   IOPort       QCount           1        Quad-B          (In)
13                     33   IOPort       QCount           1        Quad-A          (In)

and if I change dbname to 2 I get

john@cave:~$ mesaflash --device 7i92t --addr 10.10.10.10 --readhmid --dbname2 7i76
Configuration Name: HOSTMOT2

General configuration information:

  BoardName : MESA7I92
  FPGA Size: 20 KGates
  FPGA Pins: 256
  Number of IO Ports: 2
  Width of one I/O port: 17
  Clock Low frequency: 100.0000 MHz
  Clock High frequency: 180.0000 MHz
  IDROM Type: 3
  Instance Stride 0: 4
  Instance Stride 1: 64
  Register Stride 0: 256
  Register Stride 1: 256

Modules in configuration:

  Module: DPLL
  There are 1 of DPLL in configuration
  Version: 0
  Registers: 7
  BaseAddress: 7000
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

  Module: WatchDog
  There are 1 of WatchDog in configuration
  Version: 0
  Registers: 3
  BaseAddress: 0C00
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

  Module: IOPort
  There are 2 of IOPort in configuration
  Version: 0
  Registers: 5
  BaseAddress: 1000
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

  Module: QCount
  There are 2 of QCount in configuration
  Version: 2
  Registers: 5
  BaseAddress: 3000
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

  Module: SSerial
  There are 1 of SSerial in configuration
  Version: 0
  Registers: 6
  BaseAddress: 5B00
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 64 bytes

  Module: StepGen
  There are 10 of StepGen in configuration
  Version: 2
  Registers: 10
  BaseAddress: 2000
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

  Module: LED
  There are 1 of LED in configuration
  Version: 0
  Registers: 1
  BaseAddress: 0200
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

Configuration pin-out:

IO Connections for P2
DB25 pin#             I/O   Pri. func    Sec. func        Chan     Sec. Pin func   Sec. Pin Dir

 1                      0   IOPort       StepGen          0        Dir/Table2      (Out)
14                      1   IOPort       StepGen          0        Step/Table1     (Out)
 2                      2   IOPort       StepGen          1        Dir/Table2      (Out)
15                      3   IOPort       StepGen          1        Step/Table1     (Out)
 3                      4   IOPort       StepGen          2        Dir/Table2      (Out)
16                      5   IOPort       StepGen          2        Step/Table1     (Out)
 4                      6   IOPort       StepGen          3        Dir/Table2      (Out)
17                      7   IOPort       StepGen          3        Step/Table1     (Out)
 5                      8   IOPort       StepGen          4        Dir/Table2      (Out)
 6                      9   IOPort       StepGen          4        Step/Table1     (Out)
 7                     10   IOPort       SSerial          0        TXData0         (Out)
 8                     11   IOPort       SSerial          0        RXData0         (In)
 9                     12   IOPort       SSerial          0        TXData1         (Out)
10                     13   IOPort       SSerial          0        RXData1         (In)
11                     14   IOPort       QCount           0        Quad-IDX        (In)
12                     15   IOPort       QCount           0        Quad-B          (In)
13                     16   IOPort       QCount           0        Quad-A          (In)

IO Connections for P1 -> 7I76
Pin#                  I/O   Pri. func    Sec. func        Chan     Sec. Pin func   Sec. Pin Dir

TB2-4,5                17   IOPort       StepGen          5        Dir/Table2      (Out)
TB2-2,3                18   IOPort       StepGen          5        Step/Table1     (Out)
TB2-10,11              19   IOPort       StepGen          6        Dir/Table2      (Out)
TB2-8,9                20   IOPort       StepGen          6        Step/Table1     (Out)
TB2-16,17              21   IOPort       StepGen          7        Dir/Table2      (Out)
TB2-14,15              22   IOPort       StepGen          7        Step/Table1     (Out)
TB2-22,23              23   IOPort       StepGen          8        Dir/Table2      (Out)
TB2-20,21              24   IOPort       StepGen          8        Step/Table1     (Out)
TB3-4,5                25   IOPort       StepGen          9        Dir/Table2      (Out)
TB3-2,3                26   IOPort       StepGen          9        Step/Table1     (Out)
Internal-Field-IO      27   IOPort       SSerial          0        TXData2         (Out)
Internal-Field-IO      28   IOPort       SSerial          0        RXData2         (In)
TB3-18,19              29   IOPort       SSerial          0        TXData3         (Out)
TB3-16,17              30   IOPort       SSerial          0        RXData3         (In)
TB3-13,14              31   IOPort       QCount           1        Quad-IDX        (In)
TB3-10,11              32   IOPort       QCount           1        Quad-B          (In)
TB3-7,8                33   IOPort       QCount           1        Quad-A          (In)

I'm not sure what I'm looking at and does the daughter board need to be connected to use dbname?

JT

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JT
Topic Author
Away
Administrator

30 Mar 2023 13:05 #267909 by JT

Replied by JT on topic Mesaflash --dbname# <name>

Also from the man page

  --dbname# <name>  Set daughter board name to <name> for FPGA connector <N> 
                    Allows readhmid to include daughterboard terminal names,
                    where # can be in the range 1 to 6
                    (1 means first FPGA connector).

What is considered the first FPGA connector?

JT

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PCW
Away
Moderator

30 Mar 2023 15:11 #267915 by PCW

Replied by PCW on topic Mesaflash --dbname# <name>

The dbname connector order is in order of GPIO so dbname1 is the connector with GPIO 0..N

The following user(s) said Thank You: JT

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