Issues compiling a bitfile using MuxedSharedSDQCIdxPin
- jhandel
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05 Jul 2023 19:51 #274845
by jhandel
Issues compiling a bitfile using MuxedSharedSDQCIdxPin was created by jhandel
Howdy,
I am working on my 5 axis with encoded spindle CNC (so 6 encoded step/direction axises including the spindle) and I am trying to get index based homing working.
I keep getting an index out of bounds issue during compile:
Looking at the code it looks like the array in question gets set by
signal StepGenIndex: std_logic_vector(StepGens -1 downto 0);
which should be 6 as I have 6 stepgen's configured
any help would be awesome...
Here is my VHD
Thanks all.
I am working on my 5 axis with encoded spindle CNC (so 6 encoded step/direction axises including the spindle) and I am trying to get index based homing working.
I keep getting an index out of bounds issue during compile:
ERROR:HDLCompiler:533 - "/home/cnc/Downloads/hostmot2/hostmot2.vhd" Line 958: Index 6 is out of array constraint 5 downto 0 for target stepgenindexLooking at the code it looks like the array in question gets set by
signal StepGenIndex: std_logic_vector(StepGens -1 downto 0);
which should be 6 as I have 6 stepgen's configured
any help would be awesome...
Here is my VHD
use work.IDROMConst.all;
package PIN_7i76x1_7i89x2D_x15ABOB_51 is
constant ModuleID : ModuleIDType :=(
(HM2DPLLTag, x"00", ClockLowTag, x"01", HM2DPLLBaseRateAddr&PadT, HM2DPLLNumRegs, x"00", HM2DPLLMPBitMask),
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
(IOPortTag, x"00", ClockLowTag, x"03", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
(StepGenTag, x"C2", ClockLowTag, x"06", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
(MuxedQcountTag, MQCRev, ClockLowTag, x"0A", MuxedQcounterAddr&PadT, MuxedQCounterNumRegs,x"00", MuxedQCounterMPBitMask),
(MuxedQCountSelTag, x"00", ClockLowTag, x"01", NullAddr&PadT, x"00", x"00", x"00000000"),
(SSerialTag, x"00", ClockLowTag, x"01", SSerialCommandAddr&PadT, SSerialNumRegs, x"10", SSerialMPBitMask),
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
);
constant PinDesc : PinDescType :=(
-- Base func sec unit sec func sec pin
IOPortTag & x"00" & StepGenTag & StepGenDirPin, -- I/O 00 embedded 7I76
IOPortTag & x"00" & StepGenTag & StepGenStepPin, -- I/O 01
IOPortTag & x"01" & StepGenTag & StepGenDirPin, -- I/O 02
IOPortTag & x"01" & StepGenTag & StepGenStepPin, -- I/O 03
IOPortTag & x"02" & StepGenTag & StepGenDirPin, -- I/O 04
IOPortTag & x"02" & StepGenTag & StepGenStepPin, -- I/O 05
IOPortTag & x"03" & StepGenTag & StepGenDirPin, -- I/O 06
IOPortTag & x"03" & StepGenTag & StepGenStepPin, -- I/O 07
IOPortTag & x"04" & StepGenTag & StepGenDirPin, -- I/O 08
IOPortTag & x"04" & StepGenTag & StepGenStepPin, -- I/O 09
IOPortTag & x"00" & SSerialTag & SSerialTX0Pin, -- I/O 10
IOPortTag & x"00" & SSerialTag & SSerialRX0Pin, -- I/O 11
IOPortTag & x"00" & SSerialTag & SSerialTX1Pin, -- I/O 12
IOPortTag & x"00" & SSerialTag & SSerialRX1Pin, -- I/O 13
IOPortTag & x"04" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 14 for the pendant
IOPortTag & x"04" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 15 for the pendant
IOPortTag & x"04" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 16 for the pendant
-- P1
-- 5ABOB pinout
-- 26 HDR -- IDC DB25
IOPortTag & x"05" & StepGenTag & StepGenStepPin, -- I/O 01 PIN 1 PIN 1 Spindle Step
IOPortTag & x"00" & NullTag & NullPin, -- I/O 02 PIN 2 PIN 14 just GPIO
IOPortTag & x"05" & StepGenTag & StepGenDirPin, -- I/O 03 PIN 3 PIN 2 Spindle Direction
IOPortTag & x"00" & NullTag & NullPin, -- I/O 04 PIN 4 PIN 15 just GPIO
IOPortTag & x"00" & NullTag & NullPin, -- I/O 05 PIN 5 PIN 3 just GPIO
IOPortTag & x"00" & NullTag & NullPin, -- I/O 06 PIN 6 PIN 16 just GPIO
IOPortTag & x"00" & NullTag & NullPin, -- I/O 07 PIN 7 PIN 4 just GPIO
IOPortTag & x"00" & NullTag & NullPin, -- I/O 08 PIN 8 PIN 17 just GPIO
IOPortTag & x"00" & NullTag & NullPin, -- I/O 09 PIN 9 PIN 5 just GPIO
IOPortTag & x"00" & NullTag & NullPin, -- I/O 10 PIN 11 PIN 6 just GPIO
IOPortTag & x"00" & NullTag & NullPin, -- I/O 11 PIN 13 PIN 7 just GPIO
IOPortTag & x"00" & NullTag & NullPin, -- I/O 12 PIN 15 PIN 8 just GPIO
IOPortTag & x"00" & NullTag & NullPin, -- I/O 13 PIN 17 PIN 9 just GPIO
IOPortTag & x"00" & NullTag & NullPin, -- I/O 14 PIN 19 PIN 10 just GPIO
IOPortTag & x"00" & NullTag & NullPin, -- I/O 15 PIN 21 PIN 11 just GPIO
IOPortTag & x"00" & NullTag & NullPin, -- I/O 16 PIN 23 PIN 12 just GPIO
IOPortTag & x"00" & NullTag & NullPin, -- I/O 33 PIN 25 PIN 13 just GPIO
-- P2 HDR26 DB25
IOPortTag & x"00" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 17 PIN 1 PIN 1
IOPortTag & x"00" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 18 PIN 14 PIN 2
IOPortTag & x"00" & MuxedQCountTag & MuxedSharedSDQCIdxPin, -- I/O 19 PIN 2 PIN 3
IOPortTag & x"01" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 20 PIN 15 PIN 4
IOPortTag & x"01" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 21 PIN 3 PIN 5
IOPortTag & x"01" & MuxedQCountTag & MuxedSharedSDQCIdxPin, -- I/O 22 PIN 16 PIN 6
IOPortTag & x"02" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 23 PIN 4 PIN 7
IOPortTag & x"02" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 24 PIN 17 PIN 8
IOPortTag & x"02" & MuxedQCountTag & MuxedSharedSDQCIdxPin, -- I/O 25 PIN 5 PIN 9
IOPortTag & x"03" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 26 PIN 6 PIN 11
IOPortTag & x"03" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 27 PIN 7 PIN 13
IOPortTag & x"03" & MuxedQCountTag & MuxedSharedSDQCIdxPin, -- I/O 28 PIN 8 PIN 15
IOPortTag & x"00" & MuxedQCountSelTag & MuxedQCountSel0Pin, -- I/O 29 PIN 9 PIN 17
IOPortTag & x"00" & NullTag & NullPin, -- I/O 30 PIN 10 PIN 19 powop
IOPortTag & x"00" & SSerialTag & SSerialRX2Pin, -- I/O 31 PIN 11 PIN 21
IOPortTag & x"00" & SSerialTag & SSerialTX2Pin, -- I/O 32 PIN 12 PIN 23
IOPortTag & x"00" & SSerialTag & SSerialTXEN2Pin, -- I/O 33 PIN 13 PIN 25
LIOPortTag & x"00" & SSerialTag & SSerialNTXEn1Pin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for IDROM v3
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
end package PIN_7i76x1_7i89x2D_x15ABOB_51;Thanks all.
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05 Jul 2023 20:51 - 05 Jul 2023 20:52 #274849
by PCW
Replied by PCW on topic Issues compiling a bitfile using MuxedSharedSDQCIdxPin
You can only have 3 instances(0,1,2) of MuxedSharedSDQCIdxPin
if you only have 6 stepgens.
if you only have 6 stepgens.
Last edit: 05 Jul 2023 20:52 by PCW.
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- jhandel
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05 Jul 2023 21:07 #274850
by jhandel
Replied by jhandel on topic Issues compiling a bitfile using MuxedSharedSDQCIdxPin
oh shoot that is kind of obvious... ok its been long enough since I worked on this machine that I need to go back and trace out why I have a forth encoder on the 7i89 card as the pendant is encoded on the 7i96's encoder ports...
Thanks and sorry for the obvious mistake.
Thanks and sorry for the obvious mistake.
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05 Jul 2023 21:52 #274854
by tommylight
Replied by tommylight on topic Issues compiling a bitfile using MuxedSharedSDQCIdxPin
Does this belong in "driver boards" section?
It does not seem to belong here.
It does not seem to belong here.
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05 Jul 2023 21:53 #274855
by PCW
Replied by PCW on topic Issues compiling a bitfile using MuxedSharedSDQCIdxPin
Yeah, "Driver Boards" would be more appropriate
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05 Jul 2023 21:59 #274856
by PCW
There's not an issue with more encoders, but the number of "shared" stepgen/encoder
indexes is bound by the number of stepgens (the other encoders should just use the normal
muxed encoder index pin)
Also currently there must be a 1-1 encoder# to stepgen# mapping as the pin
assignment logic is pretty minimal
Replied by PCW on topic Issues compiling a bitfile using MuxedSharedSDQCIdxPin
Its not really obvious...oh shoot that is kind of obvious... ok its been long enough since I worked on this machine that I need to go back and trace out why I have a forth encoder on the 7i89 card as the pendant is encoded on the 7i96's encoder ports...
Thanks and sorry for the obvious mistake.
There's not an issue with more encoders, but the number of "shared" stepgen/encoder
indexes is bound by the number of stepgens (the other encoders should just use the normal
muxed encoder index pin)
Also currently there must be a 1-1 encoder# to stepgen# mapping as the pin
assignment logic is pretty minimal
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05 Jul 2023 22:08 #274858
by tommylight
Replied by tommylight on topic Issues compiling a bitfile using MuxedSharedSDQCIdxPin
Moved to "driver boards".
Thank you.
Thank you.
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05 Jul 2023 22:15 #274859
by jhandel
Replied by jhandel on topic Issues compiling a bitfile using MuxedSharedSDQCIdxPin
yah the mapping I have down.. (well I need to move the spindle from encoder 7 to 6 but otherwise..
now to hunt down what to configure in the HAL and ini.
Thanks
Josh
now to hunt down what to configure in the HAL and ini.
Thanks
Josh
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