7c81 Bitfile

What would need to be modified to the 7c81 source to run on a Spartan 6 dev board with a 100Mhz clock ? Mimas - Spartan 6 FPGA Development Board
The Clock pin is connected to IO_L36N_GCLK14_0 (is correct to assume this is a global clock pin).

I understand that I'd have to edit the pin constraints file.

The only reason I'm asking this is I've got some time on my hands, unemployment isn't fun and I need something to occupy my mind in between looking for work. Voltage translation is no issue as I have some boards left over from the BBB & MK experiment.

Cheers

If the input clock is 100 MHz you would need to adjust the 2 DCMs in TopGCSPIHostMot2:
(plus any changes needed in the .ucf file to match your dev boards pinout)

   ClockMultH : DCM
   generic map (
      CLKDV_DIVIDE => 2.0,
      CLKFX_DIVIDE => 2,  
--      CLKFX_MULTIPLY => 8,            -- 8 FOR 200 MHz       <<<<<<<<<<<<<<<<<<<<<<<
      CLKFX_MULTIPLY => 4,            -- 4 FOR 200 MHz  with 100MHz source        <<<<<<<<<<<<<<<<<<<<<<<
      CLKIN_DIVIDE_BY_2 => FALSE,  
      CLKIN_PERIOD => 20.0,           
      CLKOUT_PHASE_SHIFT => "NONE",  
      CLK_FEEDBACK => "1X",          
      DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",  
                                             
      DFS_FREQUENCY_MODE => "LOW",
      DLL_FREQUENCY_MODE => "LOW",
      DUTY_CYCLE_CORRECTION => TRUE,
      FACTORY_JF => X"C080",
      PHASE_SHIFT => 0,  
      STARTUP_WAIT => FALSE)
   port map (
 
      CLK0 => clk0_0,       --  
      CLKFB => clk0_0,      -- DCM clock feedback
      CLKFX => clkfx0,
      CLKIN => CLK,    -- Clock input (from IBUFG, BUFG or DCM)
      PSCLK => '0',       -- Dynamic phase adjust clock input
      PSEN => '0',         -- Dynamic phase adjust enable input
      PSINCDEC => '0',     -- Dynamic phase adjust increment/decrement
      RST => '0'        -- DCM asynchronous reset input
   );
   
  BUFG_inst0 : BUFG
   port map (
      O => fclk,    -- Clock buffer output
      I => clkfx0      -- Clock buffer input
   );
    
   ClockMultM : DCM
   generic map (
      CLKDV_DIVIDE => 2.0,
      CLKFX_DIVIDE => 2,  
 --     CLKFX_MULTIPLY => 4,            -- 4 FOR 100 MHz   <<<<<<<<<<<<<<<<<<<<<<
      CLKFX_MULTIPLY => 2,            -- 2 FOR 100 MHz with 100 Mhz source    <<<<<<<<<<<<<<<<<<<<<<
      CLKIN_DIVIDE_BY_2 => FALSE,  
      CLKIN_PERIOD => 20.0,           
      CLKOUT_PHASE_SHIFT => "NONE",  
      CLK_FEEDBACK => "1X",          
      DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",  
                                             
      DFS_FREQUENCY_MODE => "LOW",
      DLL_FREQUENCY_MODE => "LOW",
      DUTY_CYCLE_CORRECTION => TRUE,
      FACTORY_JF => X"C080",
      PHASE_SHIFT => 0,  
      STARTUP_WAIT => FALSE)
   port map (
 
      CLK0 => clk0_1,       --  
      CLKFB => clk0_1,      -- DCM clock feedback
      CLKFX => clkfx1,
      CLKIN => CLK,    -- Clock input (from IBUFG, BUFG or DCM)
      PSCLK => '0',       -- Dynamic phase adjust clock input
      PSEN => '0',         -- Dynamic phase adjust enable input
      PSINCDEC => '0',     -- Dynamic phase adjust increment/decrement
      RST => '0'        -- DCM asynchronous reset input
   );
   
  BUFG_inst1 : BUFG
   port map (
      O => clklow,    -- Clock buffer output
      I => clkfx1      -- Clock buffer input
   );
 
  -- End of DCM_inst instantiation

Thank you Sir you are a Gent.

Your help was great, after a bit of looking through the Xilinx docks I managed to work out the correct pin for COM_CSCLK as my board has the clk input on IO_L36N_GCLK14_0. Most of the clocking docs were a bit over my head, but I bungled my way through.

So far I can communicate with the board, via halrun.

The next query is probably above and beyond.

I would like 1 Spindle encoder, 1 MPG for each X & Z on the lathe and upto 5 simple quad encoders for Feed Override, Rapid Override, Spindle Overrride, Jog Speed & Max Velocity.

For the spindle encoder I guess quadencounter would be the best option and I was thinking of linuxcnc.org/docs/2.9/html/man/man9/host...ml#inm%20and%20inmux
for the rest.
I've had a look at this file PIN_7I85x2_34.vhd and the a pin file related to it. Looking at this snippet....

Questions are:
What is the function of this line:

And can I get away without the IDX entry for each ? Or have I got my wires crossed ? Any help is really appreciated.

I would not use a 7I85 as as example as that uses muxed encoders inputs.
I would use the inm input module for inputs/mpgs and the normal, non muxed
encoder for the spindle encoders.

You can use inmux to save interface pins but that requires external 74hct251
(or similar) muxes. inm works directly on inputs.

And no, you don't need an Idx pin on encoders unless its needed by the machine.
(typically needed for spindle synchronized moves or if you want to home to index)

For an example config that has most of this stuff, take a look at
PIN_7I96inmD_51.vhd

Thanks, works like a charm,

Is there any trickery involved in getting Smart serial to work.
When loading the hm2_rpspi driver the RX TX TXEN pins are just showing as gpio. There's no searching for any SmartSerial devices. Even when I use sserial_port_0=0x00000000

I know it work the first time I built firmware, cos when I loaded the driver it searched for Smartserial deivces.

I've attached my Pin file....maybe I just don't get it ATM
The files below are from a later firmware where the TXEN were removed.

Added some extra info

If the hostmot2 driver does not find a sserial remote device
it leave the associated pins as plain GPIO.

Thanks I might have to cobble up a RS-422 interface and try my 7i73. So at least I can confirm the Smartserial port is trying to talk to something.

Cos ATM it doesnt want to talk to the dev board with 7i90 sserial firmware.

Should I get a message from hostmot2 that it can't find anything or does it just go on it's merry way ?