7I80HDT Efinix Project File
04 Feb 2024 17:58 #292419
by fts
7I80HDT Efinix Project File was created by fts
I am cleaning up a converted HNC bar chucker that previously had a 5I23 driving a 7I42TA unbuffered I/O card and the special version of the 7I49 with the high voltage resolver customization. After trying a few different board combinations, I settled on moving all the control and signaling into one cabinet with a 7I80 driving the 7I49 and two 7I37TAs. I was trying yesterday to sort out the firmware, and it appears that there is not one for the Efinix silicon that supports the resolver card.
I downloaded the firmware ZIP file off Mesa's site and unzipped one of the files in the archive containing the Efinix files (efinehm2.zip). The Efinity software takes XML project files, and I am not seeing one.
If there is a project file for this silicon, would someone mind pointing me in the right direction? I have written a great deal of RTL for Altera, Xilinx, and Lattice devices, but this is sort of new territory to me as I have been able to use the "stock" firmware in every other LinuxCNC/Mesa application.
I downloaded the firmware ZIP file off Mesa's site and unzipped one of the files in the archive containing the Efinix files (efinehm2.zip). The Efinity software takes XML project files, and I am not seeing one.
DEBUGSET.ASM DELAYMS.ASM efinehm2.zip ETHEREEP.ASM ETHERFLS.ASM ETHERHM2.ASM ETHERHM2.EQU ETHERHM2.INC ETHERINI.ASM GLOBAL.EQU LBPPARSE.ASM STATIC16.MAC STEPSET.ASM TASMD16.TABIf there is a project file for this silicon, would someone mind pointing me in the right direction? I have written a great deal of RTL for Altera, Xilinx, and Lattice devices, but this is sort of new territory to me as I have been able to use the "stock" firmware in every other LinuxCNC/Mesa application.
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04 Feb 2024 18:19 - 04 Feb 2024 18:21 #292422
by PCW
Replied by PCW on topic 7I80HDT Efinix Project File
efinehm2.zip is the source for the embedded processor ROM that runs the
Ethernet --> hostmot2 code
(not needed unless you want to change the Ethernet interface)
The VHDL source and Efinity project files are in 7i80hdt-hm2-zip or 7i80hdt25-hm2.zip
(7i80hdt25-hm2.zip is for larger projects so has more relaxed timings)
Ethernet --> hostmot2 code
(not needed unless you want to change the Ethernet interface)
The VHDL source and Efinity project files are in 7i80hdt-hm2-zip or 7i80hdt25-hm2.zip
(7i80hdt25-hm2.zip is for larger projects so has more relaxed timings)
Last edit: 04 Feb 2024 18:21 by PCW.
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05 Feb 2024 17:42 #292535
by fts
Replied by fts on topic 7I80HDT Efinix Project File
Thank you for the instantaneous reply, PCW. Your reputation precedes you!
I have managed to pull the project into the Efinix software and run synthesis and PAR. I noticed in another thread about the 7I92 that there was a mention of a clock bug. Compiling the project out of the box with a top-level module being pulled in as TopEthernetHostmot2, I see these exceptions during compilation.
Missing a clock can throw a wrench in the works. Is it possible to brick one of these devices to where I would have to have a JTAG programmer to write a new bitstream, or does the Micrel MCU next to the Ethernet port handle all the flashing operations? I know that the Mesa hardware is designed to be immune to bricking, but I want to check before I hammer out some bitstreams.
I have managed to pull the project into the Efinix software and run synthesis and PAR. I noticed in another thread about the 7I92 that there was a mention of a clock bug. Compiling the project out of the box with a top-level module being pulled in as TopEthernetHostmot2, I see these exceptions during compilation.
No ports matched 'hm2fastclock'
[SDC /home/fts/Downloads/7i80_firmware/7i80hdt/configs/hostmot2/source/7i80hdt-hm2/seveni80hdt.sdc:4] No valid object(s) found for ''
[SDC /home/fts/Downloads/7i80_firmware/7i80hdt/configs/hostmot2/source/7i80hdt-hm2/seveni80hdt.sdc:4] No valid pin(s) found for clock
[SDC /home/fts/Downloads/7i80_firmware/7i80hdt/configs/hostmot2/source/7i80hdt-hm2/seveni80hdt.sdc:4] Unable to run 'create_clock' constraint due to warnings found
[SDC /home/fts/Downloads/7i80_firmware/7i80hdt/configs/hostmot2/source/7i80hdt-hm2/seveni80hdt.sdc:10] No clocks matched 'hm2fastclock'
[SDC /home/fts/Downloads/7i80_firmware/7i80hdt/configs/hostmot2/source/7i80hdt-hm2/seveni80hdt.sdc:10] set_clock_groups: No valid clock(s) found for -group 'hm2fastclock'
[SDC /home/fts/Downloads/7i80_firmware/7i80hdt/configs/hostmot2/source/7i80hdt-hm2/seveni80hdt.sdc:10] set_clock_groups: No valid clock group(s) specified
[SDC /home/fts/Downloads/7i80_firmware/7i80hdt/configs/hostmot2/source/7i80hdt-hm2/seveni80hdt.sdc:10] Unable to run 'set_clock_groups' constraint due to warnings foundMissing a clock can throw a wrench in the works. Is it possible to brick one of these devices to where I would have to have a JTAG programmer to write a new bitstream, or does the Micrel MCU next to the Ethernet port handle all the flashing operations? I know that the Mesa hardware is designed to be immune to bricking, but I want to check before I hammer out some bitstreams.
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05 Feb 2024 18:10 #292541
by PCW
Replied by PCW on topic 7I80HDT Efinix Project File
The 7I49 should use the fast clock for PWM so that's not expected
You have to try pretty hard to brick a 7I80
If accidentally brick the card, you can move both IP address jumpers
to the "up" position which will force the fallback configuration to load.
In addition there are two separate EEPROMs both containing a user and fallback configuration
The PIN_SV6_7I49_72.vhd pinout builds here with no major complaints
and meets timing (though I have not tested it with a 7I49):
Maximum possible analyzed clocks frequency
Clock Name Period (ns) Frequency (MHz) Edge
procclk 9.444 105.885 (R-R)
hm2fastclock 4.672 214.037 (R-R)
Geomean max period: 6.643
Setup (Max) Clock Relationship
Launch Clock Capture Clock Constraint (ns) Slack (ns) Edge
procclk procclk 9.900 0.456 (R-R)
hm2fastclock hm2fastclock 6.100 1.428 (R-R)
Hold (Min) Clock Relationship
Launch Clock Capture Clock Constraint (ns) Slack (ns) Edge
procclk procclk 0.000 0.086 (R-R)
hm2fastclock hm2fastclock 0.000 0.307 (R-R)
You have to try pretty hard to brick a 7I80
If accidentally brick the card, you can move both IP address jumpers
to the "up" position which will force the fallback configuration to load.
In addition there are two separate EEPROMs both containing a user and fallback configuration
The PIN_SV6_7I49_72.vhd pinout builds here with no major complaints
and meets timing (though I have not tested it with a 7I49):
Maximum possible analyzed clocks frequency
Clock Name Period (ns) Frequency (MHz) Edge
procclk 9.444 105.885 (R-R)
hm2fastclock 4.672 214.037 (R-R)
Geomean max period: 6.643
Setup (Max) Clock Relationship
Launch Clock Capture Clock Constraint (ns) Slack (ns) Edge
procclk procclk 9.900 0.456 (R-R)
hm2fastclock hm2fastclock 6.100 1.428 (R-R)
Hold (Min) Clock Relationship
Launch Clock Capture Clock Constraint (ns) Slack (ns) Edge
procclk procclk 0.000 0.086 (R-R)
hm2fastclock hm2fastclock 0.000 0.307 (R-R)
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13 Mar 2024 17:34 #295840
by MaxEkb77
Replied by MaxEkb77 on topic 7I80HDT Efinix Project File
Hi PCW.
I got efinix 7i80hdt + 7i48 + 7i44 - what's firmware i can use ?
Thank You !
I got efinix 7i80hdt + 7i48 + 7i44 - what's firmware i can use ?
Thank You !
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13 Mar 2024 18:37 #295847
by PCW
Replied by PCW on topic 7I80HDT Efinix Project File
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14 Mar 2024 02:19 #295868
by MaxEkb77
Replied by MaxEkb77 on topic 7I80HDT Efinix Project File
Thank You.
Mesaflash work correct with efinix ?
Mesaflash work correct with efinix ?
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14 Mar 2024 02:36 #295869
by PCW
Replied by PCW on topic 7I80HDT Efinix Project File
The following user(s) said Thank You: MaxEkb77
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14 Mar 2024 13:02 #295896
by MaxEkb77
Replied by MaxEkb77 on topic 7I80HDT Efinix Project File
Thank You, successful flashing.
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