Trion T20 FPGA Questions
- DSS
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08 Dec 2024 06:45 #316230
by DSS
Trion T20 FPGA Questions was created by DSS
A Couple HostMot2 / Efinix Trion FPGA questions.
- Is SPI a option or only Ethernet & PCI at present? I did not see a spi _efx.vhd but I may have over looked it.
- Any reason a T20Q144C4 could not be used instead of the T20F256C4 with Hostmot2? I feel like I may be over looking something obvious for the sake of solderability while perusing the source files.
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08 Dec 2024 13:59 #316242
by PCW
Replied by PCW on topic Trion T20 FPGA Questions
SPI should work though a Efinix specific top level file would need to be
made from the Xilinx source. Efinix tools don't automatically
translate "Z" types into tristate pins so you have to export the signal
_and_ enable pins from the top level file. Note for the current SPI source
(GCSPI) The SPI clock must be routed to a FPGA clock pin.
Any package is OK
made from the Xilinx source. Efinix tools don't automatically
translate "Z" types into tristate pins so you have to export the signal
_and_ enable pins from the top level file. Note for the current SPI source
(GCSPI) The SPI clock must be routed to a FPGA clock pin.
Any package is OK
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08 Dec 2024 23:35 - 14 Dec 2024 08:02 #316289
by DSS
Replied by DSS on topic Trion T20 FPGA Questions
Thanks for the quick response, This should get me going in the right direction. Currently I have only gone so far as to generate new .bin files when required for my 7i92t/7i96s cards.SPI should work though a Efinix specific top level file would need to be
made from the Xilinx source. Efinix tools don't automatically
translate "Z" types into tristate pins so you have to export the signal
_and_ enable pins from the top level file. Note for the current SPI source
(GCSPI) The SPI clock must be routed to a FPGA clock pin.
Awesome, glad to hear it.Any package is OK
Last edit: 14 Dec 2024 08:02 by DSS.
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