Firmware Request for 7i92 – Plasma CNC Build
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18 Sep 2025 19:07 #335164
by souh-hil
Firmware Request for 7i92 – Plasma CNC Build was created by souh-hil
Hello everyone,This is my first post here on the LinuxCNC forum, and also my very first CNC build — so please forgive any mistakes or lack of experience on my part. I'm doing my best to learn as I go.I'm building a plasma CNC machine and using a Mesa 7i92 card. For my setup, I’ll be connecting two 5-axis breakout boards — one on P1 and one on P2. I’m looking for a suitable firmware that would allow me to:
- Use 4 or 5 encoder inputs (for THCAD and potentially other uses)
- Have at least 10 inputs and 5 outputs for general machine control
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18 Sep 2025 20:51 #335170
by PCW
Replied by PCW on topic Firmware Request for 7i92 – Plasma CNC Build
For a 7I92:
7i92_5ABOBx2D.bit
for a 7I92T:
7i92t_5abobx2d.bin
Would be closest If you are using the common "Mach 5 Axis" Sainsmart parallel port BOB
Note that the inputs of the common 5 Axis breakouts are not really suitable for encoder use
as they are quite slow and require 12 V signals.
7i92_5ABOBx2D.bit
for a 7I92T:
7i92t_5abobx2d.bin
Would be closest If you are using the common "Mach 5 Axis" Sainsmart parallel port BOB
Note that the inputs of the common 5 Axis breakouts are not really suitable for encoder use
as they are quite slow and require 12 V signals.
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18 Sep 2025 23:26 #335177
by souh-hil
Replied by souh-hil on topic Firmware Request for 7i92 – Plasma CNC Build
Yes, I'm using the common 5-axis BOBs from china, one on each port (P1 and P2).
That said, I don’t actually need all 10 StepGen channels. My machine only uses 4 axes, so I’m hoping to free up many of the StepGen-related I/O pins and use them as general-purpose I/Os instead.
Also, since the 7i92 headers are mirrored (P1 and P2), both BOBs give access to the same type of GPIO pins. I’m hoping to take advantage of that symmetry and assign more pins for inputs (e.g., limit switches, ArcOK, ohmic probe, thc UP /down etc.), and just a few for outputs (torch on/off, float switch reset, laser etc.).
Ideally, I'd like a bitfile that allows:
At least 10 inputs and 5 outputs for general machine control
Fewer StepGen channels (maybe 4 or 5 max)
If a bitfile like that exists — or if modifying an existing one is straightforward — I’d really appreciate the guidance.
Thanks again for your help!
Best regards,
That said, I don’t actually need all 10 StepGen channels. My machine only uses 4 axes, so I’m hoping to free up many of the StepGen-related I/O pins and use them as general-purpose I/Os instead.
Also, since the 7i92 headers are mirrored (P1 and P2), both BOBs give access to the same type of GPIO pins. I’m hoping to take advantage of that symmetry and assign more pins for inputs (e.g., limit switches, ArcOK, ohmic probe, thc UP /down etc.), and just a few for outputs (torch on/off, float switch reset, laser etc.).
Ideally, I'd like a bitfile that allows:
At least 10 inputs and 5 outputs for general machine control
Fewer StepGen channels (maybe 4 or 5 max)
If a bitfile like that exists — or if modifying an existing one is straightforward — I’d really appreciate the guidance.
Thanks again for your help!
Best regards,
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18 Sep 2025 23:37 #335178
by tommylight
Replied by tommylight on topic Firmware Request for 7i92 – Plasma CNC Build
Any stepgen or encoder that is not in use, it's pins can be used as IO, so if you just load
loadrt num_stepgens = 4
that will enable 4 stepgens on the first port (no idea exactly if P1 or P2) and the rest of the 26 pins can be used freely as inputs or as outputs.
Use
mesaflash --card_name --IP --readhmid
replace name and IP with what you have and check the resulting pin assignment so you can decide how many stepgens and encoders you need and what pins they use, from that you know what pin numbers remain for inputs and outputs.
BUT, since you are using BOB's, you will be limited to what the BOB uses as inputs ( 10 in total for encoders and switches) and 24 as outputs.
loadrt num_stepgens = 4
that will enable 4 stepgens on the first port (no idea exactly if P1 or P2) and the rest of the 26 pins can be used freely as inputs or as outputs.
Use
mesaflash --card_name --IP --readhmid
replace name and IP with what you have and check the resulting pin assignment so you can decide how many stepgens and encoders you need and what pins they use, from that you know what pin numbers remain for inputs and outputs.
BUT, since you are using BOB's, you will be limited to what the BOB uses as inputs ( 10 in total for encoders and switches) and 24 as outputs.
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19 Sep 2025 00:30 #335180
by PCW
Replied by PCW on topic Firmware Request for 7i92 – Plasma CNC Build
A picture or link to the actual breakout board you have would be helpful.
As tommylight noted, the common "5 Axis CNC" breakout has 12 outputs
and 5 inputs and this is fixed by the breakout board hardware.
As tommylight noted, the common "5 Axis CNC" breakout has 12 outputs
and 5 inputs and this is fixed by the breakout board hardware.
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19 Sep 2025 13:50 #335191
by souh-hil
Replied by souh-hil on topic Firmware Request for 7i92 – Plasma CNC Build
Hi all,Thanks in advance to everyone who responds!I’m using the following HostMot2 bitfile for my Mesa 7i92:
BoardName : MESA7I92
FPGA Size: 9 KGates
FPGA Pins: 144
Number of IO Ports: 2
Width of one I/O port: 17
Clock Low frequency: 100.0000 MHz
Clock High frequency: 200.0000 MHz
IDROM Type: 3
Instance Stride 0: 4
Instance Stride 1: 64
Register Stride 0: 256
Register Stride 1: 256
Modules in configuration:
Module: DPLL
There are 1 of DPLL in configuration
Version: 0
Registers: 7
BaseAddress: 7000
ClockFrequency: 100.000 MHz
Register Stride: 256 bytes
Instance Stride: 4 bytes
Module: WatchDog
There are 1 of WatchDog in configuration
Version: 0
Registers: 3
BaseAddress: 0C00
ClockFrequency: 100.000 MHz
Register Stride: 256 bytes
Instance Stride: 4 bytes
Module: IOPort
There are 2 of IOPort in configuration
Version: 0
Registers: 5
BaseAddress: 1000
ClockFrequency: 100.000 MHz
Register Stride: 256 bytes
Instance Stride: 4 bytes
Module: QCount
There are 6 of QCount in configuration
Version: 2
Registers: 5
BaseAddress: 3000
ClockFrequency: 100.000 MHz
Register Stride: 256 bytes
Instance Stride: 4 bytes
Module: StepGen
There are 5 of StepGen in configuration
Version: 2
Registers: 10
BaseAddress: 2000
ClockFrequency: 100.000 MHz
Register Stride: 256 bytes
Instance Stride: 4 bytes
Module: PWM
There are 1 of PWM in configuration
Version: 0
Registers: 5
BaseAddress: 4100
ClockFrequency: 200.000 MHz
Register Stride: 256 bytes
Instance Stride: 4 bytes
Module: LED
There are 1 of LED in configuration
Version: 0
Registers: 1
BaseAddress: 0200
ClockFrequency: 100.000 MHz
Register Stride: 256 bytes
Instance Stride: 4 bytes
Configuration pin-out:
IO Connections for P2
Pin# I/O Pri. func Sec. func Chan Pin func Pin Dir
1 0 IOPort PWM 0 PWM (Out)
14 1 IOPort None
2 2 IOPort StepGen 0 Step/Table1 (Out)
15 3 IOPort None
3 4 IOPort StepGen 0 Dir/Table2 (Out)
16 5 IOPort StepGen 4 Step/Table1 (Out)
4 6 IOPort StepGen 1 Step/Table1 (Out)
17 7 IOPort StepGen 4 Dir/Table2 (Out)
5 8 IOPort StepGen 1 Dir/Table2 (Out)
6 9 IOPort StepGen 2 Step/Table1 (Out)
7 10 IOPort StepGen 2 Dir/Table2 (Out)
8 11 IOPort StepGen 3 Step/Table1 (Out)
9 12 IOPort StepGen 3 Dir/Table2 (Out)
10 13 IOPort None
11 14 IOPort QCount 0 Quad-A (In)
12 15 IOPort QCount 0 Quad-B (In)
13 16 IOPort QCount 0 Quad-IDX (In)
IO Connections for P1
Pin# I/O Pri. func Sec. func Chan Pin func Pin Dir
1 17 IOPort QCount 1 Quad-A (In)
14 18 IOPort QCount 1 Quad-B (In)
2 19 IOPort QCount 1 Quad-IDX (In)
15 20 IOPort QCount 2 Quad-A (In)
3 21 IOPort QCount 2 Quad-B (In)
16 22 IOPort QCount 2 Quad-IDX (In)
4 23 IOPort QCount 3 Quad-A (In)
17 24 IOPort QCount 3 Quad-B (In)
5 25 IOPort QCount 3 Quad-IDX (In)
6 26 IOPort QCount 4 Quad-A (In)
7 27 IOPort QCount 4 Quad-B (In)
8 28 IOPort QCount 4 Quad-IDX (In)
9 29 IOPort QCount 5 Quad-A (In)
10 30 IOPort QCount 5 Quad-B (In)
11 31 IOPort QCount 5 Quad-IDX (In)
12 32 IOPort None
13 33 IOPort None
BoardName : MESA7I92
FPGA Size: 9 KGates
FPGA Pins: 144
Number of IO Ports: 2
Width of one I/O port: 17
Clock Low frequency: 100.0000 MHz
Clock High frequency: 200.0000 MHz
IDROM Type: 3
Instance Stride 0: 4
Instance Stride 1: 64
Register Stride 0: 256
Register Stride 1: 256
Modules in configuration:
Module: DPLL
There are 1 of DPLL in configuration
Version: 0
Registers: 7
BaseAddress: 7000
ClockFrequency: 100.000 MHz
Register Stride: 256 bytes
Instance Stride: 4 bytes
Module: WatchDog
There are 1 of WatchDog in configuration
Version: 0
Registers: 3
BaseAddress: 0C00
ClockFrequency: 100.000 MHz
Register Stride: 256 bytes
Instance Stride: 4 bytes
Module: IOPort
There are 2 of IOPort in configuration
Version: 0
Registers: 5
BaseAddress: 1000
ClockFrequency: 100.000 MHz
Register Stride: 256 bytes
Instance Stride: 4 bytes
Module: QCount
There are 6 of QCount in configuration
Version: 2
Registers: 5
BaseAddress: 3000
ClockFrequency: 100.000 MHz
Register Stride: 256 bytes
Instance Stride: 4 bytes
Module: StepGen
There are 5 of StepGen in configuration
Version: 2
Registers: 10
BaseAddress: 2000
ClockFrequency: 100.000 MHz
Register Stride: 256 bytes
Instance Stride: 4 bytes
Module: PWM
There are 1 of PWM in configuration
Version: 0
Registers: 5
BaseAddress: 4100
ClockFrequency: 200.000 MHz
Register Stride: 256 bytes
Instance Stride: 4 bytes
Module: LED
There are 1 of LED in configuration
Version: 0
Registers: 1
BaseAddress: 0200
ClockFrequency: 100.000 MHz
Register Stride: 256 bytes
Instance Stride: 4 bytes
Configuration pin-out:
IO Connections for P2
Pin# I/O Pri. func Sec. func Chan Pin func Pin Dir
1 0 IOPort PWM 0 PWM (Out)
14 1 IOPort None
2 2 IOPort StepGen 0 Step/Table1 (Out)
15 3 IOPort None
3 4 IOPort StepGen 0 Dir/Table2 (Out)
16 5 IOPort StepGen 4 Step/Table1 (Out)
4 6 IOPort StepGen 1 Step/Table1 (Out)
17 7 IOPort StepGen 4 Dir/Table2 (Out)
5 8 IOPort StepGen 1 Dir/Table2 (Out)
6 9 IOPort StepGen 2 Step/Table1 (Out)
7 10 IOPort StepGen 2 Dir/Table2 (Out)
8 11 IOPort StepGen 3 Step/Table1 (Out)
9 12 IOPort StepGen 3 Dir/Table2 (Out)
10 13 IOPort None
11 14 IOPort QCount 0 Quad-A (In)
12 15 IOPort QCount 0 Quad-B (In)
13 16 IOPort QCount 0 Quad-IDX (In)
IO Connections for P1
Pin# I/O Pri. func Sec. func Chan Pin func Pin Dir
1 17 IOPort QCount 1 Quad-A (In)
14 18 IOPort QCount 1 Quad-B (In)
2 19 IOPort QCount 1 Quad-IDX (In)
15 20 IOPort QCount 2 Quad-A (In)
3 21 IOPort QCount 2 Quad-B (In)
16 22 IOPort QCount 2 Quad-IDX (In)
4 23 IOPort QCount 3 Quad-A (In)
17 24 IOPort QCount 3 Quad-B (In)
5 25 IOPort QCount 3 Quad-IDX (In)
6 26 IOPort QCount 4 Quad-A (In)
7 27 IOPort QCount 4 Quad-B (In)
8 28 IOPort QCount 4 Quad-IDX (In)
9 29 IOPort QCount 5 Quad-A (In)
10 30 IOPort QCount 5 Quad-B (In)
11 31 IOPort QCount 5 Quad-IDX (In)
12 32 IOPort None
13 33 IOPort None
- I only need 4 axes (X, Y1, Y2, Z). Can I use the last StepGen for torch on and laser pointer outputs?
- I do not need encoders. Can I use the QCount pins as general-purpose inputs?
- Can I use the pins labeled “None” or “unassigned” in the bitfile as inputs or outputs, depending on their pin direction?For example, pins 10 and 15 as inputs, and pin 14 as output?
- Are pins 13 and 15 on P2 free to use as I/O?
- My breakout board has 5 inputs labeled P10, P11, P12, P13, and P15. Can I use all of them as inputs
Attachments:
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19 Sep 2025 13:57 #335192
by tommylight
Replied by tommylight on topic Firmware Request for 7i92 – Plasma CNC Build
1 Yes
2 Yes
3 Yes
4 Yes, if you do not use any encoders
5 Yes
2 Yes
3 Yes
4 Yes, if you do not use any encoders
5 Yes
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26 Sep 2025 09:57 #335448
by souh-hil
Replied by souh-hil on topic Firmware Request for 7i92 – Plasma CNC Build
Hello again everyone,First, I apologize for the late reply — I’ve been working on revising my plan and wiring, and it took longer than expected.I’ve updated my wiring/architecture plan (see attached diagram), and here’s where I’m at:
- Mesa 7i92 over Ethernet
- Two 5-axis breakout boards (5ABOB ×2)
- DM556 drivers for NEMA34 motors (3.5 Nm, 3 A/phase)
- THC Proma 150 for torche height control (Arc OK, Up, Down signals)
- Relays for torch, laser, pump, etc.
- E-stop, limits, probe via optoisolators
- Power supplies: 5 V/8 A, 24 V/3 A, 36 V/12 A
- With that setup (7i92 + 2 × 5ABOB), is the wiring architecture I’m proposing feasible?
- I was thinking of starting with the G540 HAL/INI config in pncconf as a base, then editing it . Is that a sensible approach, or is there a better workflow to generate a clean HAL/INI for this sort of layout?
Attachments:
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26 Sep 2025 12:42 #335453
by tommylight
Replied by tommylight on topic Firmware Request for 7i92 – Plasma CNC Build
1. yes
2. yes
2. yes
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