Following errors at fairly low speeds with mesa 5i25? Also bad latency (120k)

Do you have time to help me with firmware generation PCW? I installed a fresh SSD drive in my computer and put the latest 2.7 Wheezy ISO on it. I've got a config generated with PID control from pncconf now, but I think I flashed a random new firmware by accident in the process and now LinuxCNC is giving me HAL errors for just about every line of the firmware. I still haven't got my hands on that old laptop with my source from 6 years ago, might be another few weeks before I can get it shipped cross country.

I have the Xilinx toolchain latest 13.x version installed but when I try to run make in the hostmot2-firmware git folder I get `IOError: [Errno 2] No such file or directory: 'work.bit'`

Maybe because I used a webpack license instead of the 30 day free trial? My laptop uses a dongle Ethernet adapter and they seemed to not like that as a NIC when I tried to get a 30 day license. Which, fair. One dongle a month would be way cheaper than their license I'm guessing.

I'm using the free webpack version 14.7 on Linux and don't have any serious issues
What pinout do you need?

I just need the same one from the end of the previous page, but with DPLL enabled!

The only weird part is that each stepgen needs four outputs because I'm using table mode. I can rewire things on my breadboard if this exact pinout is hard with DPLL for some reason, really I just need 3 stepgens with my weird table mode pins, 1 pwm gen, and DPLL. There's a quadrature counter enabled in the pins below just because whatever firmware I modified back in the day had it. It'd be nice to keep that because I might want to put an encoder on my spindle, but it totally doesn't matter.

Thanks so much for all your help!

1 0 IOPort None
14 1 IOPort PWM 0 PWM (Out)
2 2 IOPort StepGen 0 Step/Table1 (Out)
15 3 IOPort None
3 4 IOPort StepGen 0 Dir/Table2 (Out)
16 5 IOPort PWM 0 Dir (Out)
4 6 IOPort StepGen 0 Table3 (Out)
17 7 IOPort None
5 8 IOPort StepGen 0 Table4 (Out)
6 9 IOPort StepGen 1 Step/Table1 (Out)
7 10 IOPort StepGen 1 Dir/Table2 (Out)
8 11 IOPort StepGen 1 Table3 (Out)
9 12 IOPort StepGen 1 Table4 (Out)
10 13 IOPort StepGen 2 Step/Table1 (Out)
11 14 IOPort StepGen 2 Dir/Table2 (Out)
12 15 IOPort StepGen 2 Table3 (Out)
13 16 IOPort StepGen 2 Table4 (Out)

IO Connections for P2
Pin# I/O Pri. func Sec. func Chan Pin func Pin Dir

1 17 IOPort None
14 18 IOPort PWM 1 PWM (Out)
2 19 IOPort StepGen 3 Step/Table1 (Out)
15 20 IOPort None
3 21 IOPort StepGen 3 Dir/Table2 (Out)
16 22 IOPort PWM 1 Dir (Out)
4 23 IOPort StepGen 4 Step/Table1 (Out)
17 24 IOPort None
5 25 IOPort StepGen 4 Dir/Table2 (Out)
6 26 IOPort StepGen 5 Step/Table1 (Out)
7 27 IOPort StepGen 5 Dir/Table2 (Out)
8 28 IOPort StepGen 6 Step/Table1 (Out)
9 29 IOPort StepGen 6 Dir/Table2 (Out)
10 30 IOPort None
11 31 IOPort QCount 0 Quad-A (In)
12 32 IOPort QCount 0 Quad-B (In)
13 33 IOPort QCount 0 Quad-IDX (In)

here's a shot at it:

Thanks a bunch!

Latest issue: The apt repositories for Wheezy haven't got libpci-dev and I can't seem to find one online because it's so old.

I built and installed from the source [0] and that all worked without errors but the Mesaflash build still can't find pci/pci.h

I have to step away until this evening, but do you know how to fix this? Thanks again!

[0]: github.com/pciutils/pciutils

Nevermind I was being silly, this image has mesaflash built in!

I think I succeeded in flashing your new bitfile, mesaflash now thinks my 6i25 is a 5i25 and --readhmid gives me the expected pinout, however dmesg still has a different pinout with no table3, table4 pins, and when I try running my old config on the machine now the motors just jitter, which is expected behavior if only 2/4 phase pins are being driven.

This behavior didn't change after a full shut down and restart, which I did because mesaflash --reload was saying the firmware was too old to support reload. It now reloads successfully, which is more evidence I've succeeded at flashing.

what does

sudo mesaflash --device 5i25 --readhmid

report?

stepgen_width=4 is all that was missing from my HAL!

I've got it working as-before on your bitfile now. I haven't hooked DPLL up to the stepgens or switched to PID control mode yet, but I think that should all go smoothly now that I'm on an up to date ish system. Thank you again! I'll report back with the final performance, hopefully it can get all the way up to 100 IPM

Oops just saw your latest reply! --readmid was reporting your new pinout IE table mode pins were present, but dmesg wasn't because stepgen_width was defaulting to 2 and the table pins were being marked as GPIOs

Yeah, the stepgen width thing was a relatively recent addition