Mesa 7I43-4 first tests but no sucess
- Mike_Eitel
- Topic Author
- Offline
- Platinum Member
Less
More
- Posts: 1150
- Thank you received: 184
19 Aug 2012 19:27 #23403
by Mike_Eitel
Replied by Mike_Eitel on topic Re:hm2/7i43-Re:Mesa 7I43-4 first tests but no sucess
Hi PCW
I know.. On other places in manual you write that pull-up can be switched on and of by SW.
I'm talking only of input-mode.
1K is not enough to get low signal.
There is an resting "offset" of 1.49 V. Means in my eyes that ca 1.5mA are driven by the board.
So pull up seems to be also in the range of 1K.
I want to use Input with floating pins.
How can I get that by hostmot2 ?
Mike
I know.. On other places in manual you write that pull-up can be switched on and of by SW.
I'm talking only of input-mode.
1K is not enough to get low signal.
There is an resting "offset" of 1.49 V. Means in my eyes that ca 1.5mA are driven by the board.
So pull up seems to be also in the range of 1K.
I want to use Input with floating pins.
How can I get that by hostmot2 ?
Mike
Please Log in or Create an account to join the conversation.
19 Aug 2012 19:32 - 19 Aug 2012 20:50 #23404
by PCW
Replied by PCW on topic Re:hm2/7i43-Re:Mesa 7I43-4 first tests but no sucess
By removing the pull down resistors and following the high=inactive standard
That is to say the 7I43 (and all of our FPGA cards) are designed for
active low inputs and outputs, for output safety, OPTO22 compatibility and
compatibility with the FPGAs HotSwap/ preconfiguration mode.
This means its much easier to use active low I/O and use the built in pullups
Note that this same situation applies to parallel port inputs, they normally have built in
pullup resistors (the original IBM design has 4.7K pullups to 5V on the input pins)
which means pulldowns (unless they are very stiff) will lead to marginal I/O voltages
That is to say the 7I43 (and all of our FPGA cards) are designed for
active low inputs and outputs, for output safety, OPTO22 compatibility and
compatibility with the FPGAs HotSwap/ preconfiguration mode.
This means its much easier to use active low I/O and use the built in pullups
Note that this same situation applies to parallel port inputs, they normally have built in
pullup resistors (the original IBM design has 4.7K pullups to 5V on the input pins)
which means pulldowns (unless they are very stiff) will lead to marginal I/O voltages
Last edit: 19 Aug 2012 20:50 by PCW.
Please Log in or Create an account to join the conversation.
Moderators: cmorley
Time to create page: 0.479 seconds