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PnCConf -- Inverting Step Gen / Dir Gen signals
09 Feb 2016 20:54 - 09 Feb 2016 20:57 #69883
by Amedee
PnCConf -- Inverting Step Gen / Dir Gen signals was created by Amedee
I am new to LinuxCNC, and I am trying to configure all the electronics step by step.
I have a 6i25/7i76 combo connected to Leadshine DM556 drivers in 'differential mode' (Step +/- to Pulse +/-)
It all works well (using the 'Test/Tune Axis' tool), but I was trying to understand if I was triggering on the right edge (step pulse and space have the same duration on these drivers, so either way would probably work).
I started changing the 'Inv' checkbox for Step Gen / Dir Gen; but I could not see any difference -- also measuring the voltage on the board did not show any difference.
When I looked at 'hm2_5i25.0.gpio.000.invert_output'/'hm2_5i25.0.gpio.001.invert_output'' with Hal Meter they were always 'FALSE' regardless of the 'inv' checkbox status
Now when entering the 'Test/Tune Axis' tool, I could see on the console
A quick look at the source showed that we were missing a '\n':
With this quick fix I now have the correct flag in Hal Meter, but I still can't see a real difference in my tests (nor in the board voltages)
Am I doing something wrong here, or is there a better way to test?
(Running LinuxCNC 2.7.3 / Linux 3.16.0-9-rtai-686-pae)
Edit: don't know what's happening, but my posts always end up in the wrong section -- maybe because I navigate in another browser tab... Anyway, if this could be moved in the PnCConf section...
I have a 6i25/7i76 combo connected to Leadshine DM556 drivers in 'differential mode' (Step +/- to Pulse +/-)
It all works well (using the 'Test/Tune Axis' tool), but I was trying to understand if I was triggering on the right edge (step pulse and space have the same duration on these drivers, so either way would probably work).
I started changing the 'Inv' checkbox for Step Gen / Dir Gen; but I could not see any difference -- also measuring the voltage on the board did not show any difference.
When I looked at 'hm2_5i25.0.gpio.000.invert_output'/'hm2_5i25.0.gpio.001.invert_output'' with Hal Meter they were always 'FALSE' regardless of the 'inv' checkbox status
Now when entering the 'Test/Tune Axis' tool, I could see on the console
<stdin>:40: setp requires 2 arguments, 4 given
A quick look at the source showed that we were missing a '\n':
--- tests.py.orig 2016-02-09 21:26:03.385859170 +0100
+++ tests.py 2016-02-09 21:42:46.501248302 +0100
@@ -676,7 +676,7 @@
self.scale = get_value(w[axis + "stepscale"]) * 1
stepinvertlist = self.a.stepgen_invert_pins(step_sig)
for i in stepinvertlist:
- halrun.write("setp "+i+".invert_output true")
+ halrun.write("setp "+i+".invert_output true\n")
halrun.write("setp %s.step_type 0 \n"% (self.step_signalname))
halrun.write("setp %s.control-type 1 \n"% (self.step_signalname))
halrun.write("setp %s.position-scale %f \n"% (self.step_signalname,self.scale))
With this quick fix I now have the correct flag in Hal Meter, but I still can't see a real difference in my tests (nor in the board voltages)
Am I doing something wrong here, or is there a better way to test?
(Running LinuxCNC 2.7.3 / Linux 3.16.0-9-rtai-686-pae)
Edit: don't know what's happening, but my posts always end up in the wrong section -- maybe because I navigate in another browser tab... Anyway, if this could be moved in the PnCConf section...
Last edit: 09 Feb 2016 20:57 by Amedee. Reason: Wrong section
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09 Feb 2016 21:39 #69884
by PCW
Replied by PCW on topic PnCConf -- Inverting Step Gen / Dir Gen signals
Its important to get the step polarity correct because the direction change setup and
hold times are measured from the leading edge of the step pulse
( though if you set these much longer than the step pulse and dont violate minimum step and idle times,
the step pulse polarity doesn't matter )
hold times are measured from the leading edge of the step pulse
( though if you set these much longer than the step pulse and dont violate minimum step and idle times,
the step pulse polarity doesn't matter )
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10 Feb 2016 01:40 #69898
by cmorley
Replied by cmorley on topic PnCConf -- Inverting Step Gen / Dir Gen signals
I appreciate the bug report especially with bug fixes included!
I will push this one too.
Chris M
I will push this one too.
Chris M
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10 Feb 2016 20:30 #69959
by Amedee
Replied by Amedee on topic PnCConf -- Inverting Step Gen / Dir Gen signals
Thank you Chris!
However, I am still a bit confused, and I tested again this evening, re-measuring the voltages on the board.
I do see a change now when I invert, but they invert the wrong signal!
That is: Inverting 'Step Gen' will invert the Dir signal, and the opposite!
When you invert 'Step Gen', you generate 'setp hm2_5i25.0.gpio.000.invert_output true'
When you invert 'Dir Gen', you generate 'setp hm2_5i25.0.gpio.001.invert_output true'
It makes sense at first, but when I look at the 7i76 manual (Page 10) it seems that Dir is mapped on GPIO 0 and Step on GPIO 1
Don't we have the GPIO pin mapping wrong?
However, I am still a bit confused, and I tested again this evening, re-measuring the voltages on the board.
I do see a change now when I invert, but they invert the wrong signal!
That is: Inverting 'Step Gen' will invert the Dir signal, and the opposite!
When you invert 'Step Gen', you generate 'setp hm2_5i25.0.gpio.000.invert_output true'
When you invert 'Dir Gen', you generate 'setp hm2_5i25.0.gpio.001.invert_output true'
It makes sense at first, but when I look at the 7i76 manual (Page 10) it seems that Dir is mapped on GPIO 0 and Step on GPIO 1
Don't we have the GPIO pin mapping wrong?
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11 Feb 2016 06:39 #69976
by cmorley
Replied by cmorley on topic PnCConf -- Inverting Step Gen / Dir Gen signals
I will have to check on this later in the week ![:( :(](/media/kunena/emoticons/sad.png)
Chris M
![:( :(](/media/kunena/emoticons/sad.png)
Chris M
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11 Feb 2016 14:47 #69993
by Amedee
Replied by Amedee on topic PnCConf -- Inverting Step Gen / Dir Gen signals
Thank you
FYI, here is what dmesg says:
This confirms that Dir is on GPIO pin 0 and Step on pin 1
An easy fix could be to swap STEPA/STEPB in private_data.py where they are 'assigned' to the board:But that might look a bit strange as it would show 'B' before 'A' in the UI:
We can't just rename the pins ans say 'Dir Gen - A' / 'Step Gen - B', as other part of the code rely on the fact that STEPA is the step gen...
FYI, here is what dmesg says:
[ 5094.308716] hm2: loading Mesa HostMot2 driver version 0.15
[ 5094.330362] hm2_pci: loading Mesa AnyIO HostMot2 driver version 0.7
[ 5094.330756] ACPI: PCI Interrupt Link [APC2] enabled at IRQ 17
[ 5094.330777] hm2_pci: discovered 5i25 at 0000:03:00.0
[ 5094.331046] hm2/hm2_5i25.0: Smart Serial Firmware Version 43
[ 5094.388117] hm2/hm2_5i25.0: 34 I/O Pins used:
[ 5094.388127] hm2/hm2_5i25.0: IO Pin 000 (P3-01): StepGen #0, pin Direction (Output)
[ 5094.388130] hm2/hm2_5i25.0: IO Pin 001 (P3-14): StepGen #0, pin Step (Output)
[ 5094.388133] hm2/hm2_5i25.0: IO Pin 002 (P3-02): StepGen #1, pin Direction (Output)
[ 5094.388136] hm2/hm2_5i25.0: IO Pin 003 (P3-15): StepGen #1, pin Step (Output)
[ 5094.388139] hm2/hm2_5i25.0: IO Pin 004 (P3-03): StepGen #2, pin Direction (Output)
[ 5094.388142] hm2/hm2_5i25.0: IO Pin 005 (P3-16): StepGen #2, pin Step (Output)
[ 5094.388144] hm2/hm2_5i25.0: IO Pin 006 (P3-04): StepGen #3, pin Direction (Output)
[ 5094.388147] hm2/hm2_5i25.0: IO Pin 007 (P3-17): StepGen #3, pin Step (Output)
[ 5094.388150] hm2/hm2_5i25.0: IO Pin 008 (P3-05): StepGen #4, pin Direction (Output)
[ 5094.388153] hm2/hm2_5i25.0: IO Pin 009 (P3-06): StepGen #4, pin Step (Output)
This confirms that Dir is on GPIO pin 0 and Step on pin 1
An easy fix could be to swap STEPA/STEPB in private_data.py where they are 'assigned' to the board:
424 ['5i25-Internal Data', '5i25', '7i76x2 -With One 7i76', '5i25', 'hm2_pci', 1,3, 0,0, 0,3, 0,0, 5,2, 1,2, 0,0,0,0,0,0,0,0, 1, 34, 33, 200, [3, 2],
425 # TAB 3
426 [S.STEPA,0],[S.STEPB,0],[S.STEPA,1],[S.STEPB,1],[S.STEPA,2],[S.STEPB,2],[S.STEPA,3],[S.STEPB,3],[S.STEPA,4],[S.STEPB,4],
427 [S.SS7I76M0,0],[S.RXDATA0,0],[S.TXDATA1,0],[S.RXDATA1,0],[S.ENCI,0],[S.ENCB,0],[S.ENCA,0],
428 [S.NUSED,0],[S.NUSED,0],[S.NUSED,0],[S.NUSED,0],[S.NUSED,0],[S.NUSED,0],[S.NUSED,0],
We can't just rename the pins ans say 'Dir Gen - A' / 'Step Gen - B', as other part of the code rely on the fact that STEPA is the step gen...
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14 Feb 2016 23:59 #70136
by cmorley
Replied by cmorley on topic PnCConf -- Inverting Step Gen / Dir Gen signals
I did in fact just swap the names in the firmware array.
I also took the chance to change the 7i76e firmware - I'm pretty sure it's the same.
Thanks again.
Chris M
I also took the chance to change the 7i76e firmware - I'm pretty sure it's the same.
Thanks again.
Chris M
The following user(s) said Thank You: Amedee
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15 Feb 2016 08:16 #70153
by Amedee
Replied by Amedee on topic PnCConf -- Inverting Step Gen / Dir Gen signals
Thank you!
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