MESA 7i96s + 7i77 how to get file .bit for flash

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29 Aug 2023 11:00 #279272 by abdulasis12
Hi
I have 2 board  7i96s and 7i77
I need connect 7i77 via P1 port.
I read found 
forum.linuxcnc.org/39-pncconf/37890-mesa...work-together#151351
I go to D/L from mesanet I got file but inside folder 7i96s.zip\7i96s\configs\hostmot2 is  2type  = .bin and .pin  not have .bit file

I go try to D/L of 7i92 and 7i76E inside folder have .bit ​​​​​​​
how to  flash for 7i96s ?

 

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29 Aug 2023 11:17 #279273 by PCW
7i96s_7i77d.bin is the proper firmware file for a 7I96S + 7I77
 
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29 Aug 2023 12:02 #279274 by abdulasis12

7i96s_7i77d.bin is the proper firmware file for a 7I96S + 7I77

 

Thank you for reply MR.PCW

After I flash this is result
asis@192:~$ sudo mesaflash --device 7i96s --addr 10.10.10.10 --readhmid
Configuration Name: HOSTMOT2

General configuration information:

  BoardName : MESA7I96
  FPGA Size: 20 KGates
  FPGA Pins: 256
  Number of IO Ports: 3
  Width of one I/O port: 17
  Clock Low frequency: 100.0000 MHz
  Clock High frequency: 200.0000 MHz
  IDROM Type: 3
  Instance Stride 0: 4
  Instance Stride 1: 64
  Register Stride 0: 256
  Register Stride 1: 256

Modules in configuration:

  Module: DPLL
  There are 1 of DPLL in configuration
  Version: 0
  Registers: 7
  BaseAddress: 7000
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

  Module: WatchDog
  There are 1 of WatchDog in configuration
  Version: 0
  Registers: 3
  BaseAddress: 0C00
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

  Module: IOPort
  There are 3 of IOPort in configuration
  Version: 0
  Registers: 5
  BaseAddress: 1000
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

  Module: OutM
  There are 1 of OutM in configuration
  Version: 0
  Registers: 1
  BaseAddress: B000
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

  Module: PWM
  There are 1 of PWM in configuration
  Version: 0
  Registers: 5
  BaseAddress: 4100
  ClockFrequency: 200.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

  Module: StepGen
  There are 5 of StepGen in configuration
  Version: 2
  Registers: 10
  BaseAddress: 2000
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

  Module: MuxedQCount
  There are 8 of MuxedQCount in configuration
  Version: 4
  Registers: 5
  BaseAddress: 3600
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

  Module: MuxedQCountSel
  There are 1 of MuxedQCountSel in configuration
  Version: 0
  Registers: 0
  BaseAddress: 0000
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

  Module: SSerial
  There are 1 of SSerial in configuration
  Version: 0
  Registers: 6
  BaseAddress: 5B00
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 64 bytes

  Module: SSR
  There are 1 of SSR in configuration
  Version: 0
  Registers: 2
  BaseAddress: 7D00
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

  Module: InM
  There are 1 of InM in configuration
  Version: 0
  Registers: 5
  BaseAddress: 8500
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

  Module: LED
  There are 1 of LED in configuration
  Version: 0
  Registers: 1
  BaseAddress: 0200
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

Configuration pin-out:

IO Connections for TB3 -> 7I96_0
Pin#                  I/O   Pri. func    Sec. func        Chan     Sec. Pin func   Sec. Pin Dir

TB3-1                   0   IOPort       InM              0        Input0          (In)
TB3-2                   1   IOPort       InM              0        Input1          (In)
TB3-3                   2   IOPort       InM              0        Input2          (In)
TB3-4                   3   IOPort       InM              0        Input3          (In)
TB3-5                   4   IOPort       InM              0        Input4          (In)
TB3-6                   5   IOPort       InM              0        Input5          (In)
TB3-7                   6   IOPort       InM              0        Input6          (In)
TB3-8                   7   IOPort       InM              0        Input7          (In)
TB3-9                   8   IOPort       InM              0        Input8          (In)
TB3-10                  9   IOPort       InM              0        Input9          (In)
TB3-11                 10   IOPort       InM              0        Input10         (In)
TB3-13,14              11   IOPort       SSR              0        Out-00          (Out)
TB3-15,16              12   IOPort       SSR              0        Out-01          (Out)
TB3-17,18              13   IOPort       SSR              0        Out-02          (Out)
TB3-19,20              14   IOPort       SSR              0        Out-03          (Out)
TB3-21,22              15   IOPort       OutM             0        Output4         (Out)
TB3-23,24              16   IOPort       OutM             0        Output5         (Out)

IO Connections for TB1/TB2 -> 7I96_1
Pin#                  I/O   Pri. func    Sec. func        Chan     Sec. Pin func   Sec. Pin Dir

TB1-2,3                17   IOPort       StepGen          0        Step/Table1     (Out)
TB1-4,5                18   IOPort       StepGen          0        Dir/Table2      (Out)
TB1-8,9                19   IOPort       StepGen          1        Step/Table1     (Out)
TB1-10,11              20   IOPort       StepGen          1        Dir/Table2      (Out)
TB1-14,15              21   IOPort       StepGen          2        Step/Table1     (Out)
TB1-16,17              22   IOPort       StepGen          2        Dir/Table2      (Out)
TB1-20,21              23   IOPort       StepGen          3        Step/Table1     (Out)
TB1-22,23              24   IOPort       StepGen          3        Dir/Table2      (Out)
TB2-2,3                25   IOPort       StepGen          4        Step/Table1     (Out)
TB2-4,5                26   IOPort       StepGen          4        Dir/Table2      (Out)
TB2-7,8                27   IOPort       MuxedQCount      3        MuxQ-A          (In)
TB2-10,11              28   IOPort       MuxedQCount      3        MuxQ-B          (In)
TB2-13,14              29   IOPort       MuxedQCount      3        MuxQ-IDX        (In)
TB2-16,17              30   IOPort       SSerial          0        RXData3         (In)
TB2-18,19              31   IOPort       SSerial          0        TXData3         (Out)
Internal-TXEn          32   IOPort       SSerial          0        TXEn3           (Out)
Internal               33   IOPort       SSR              0        AC Ref          (Out)

IO Connections for P1 -> 7I96_2
Pin#                  I/O   Pri. func    Sec. func        Chan     Sec. Pin func   Sec. Pin Dir

P1-01/DB25-01          34   IOPort       SSerial          0        TXEn2           (Out)
P1-02/DB25-14          35   IOPort       SSerial          0        TXData2         (Out)
P1-03/DB25-02          36   IOPort       SSerial          0        RXData2         (In)
P1-04/DB25-15          37   IOPort       SSerial          0        TXData1         (Out)
P1-05/DB25-03          38   IOPort       SSerial          0        RXData1         (In)
P1-06/DB25-16          39   IOPort       SSerial          0        TXData0         (Out)
P1-07/DB25-04          40   IOPort       SSerial          0        RXData0         (In)
P1-08/DB25-17          41   IOPort       MuxedQCountSel   0        MuxSel0         (Out)
P1-09/DB25-05          42   IOPort       MuxedQCount      0        MuxQ-A          (In)
P1-11/DB25-06          43   IOPort       MuxedQCount      0        MuxQ-B          (In)
P1-13/DB25-07          44   IOPort       MuxedQCount      0        MuxQ-IDX        (In)
P1-15/DB25-08          45   IOPort       MuxedQCount      1        MuxQ-A          (In)
P1-17/DB25-09          46   IOPort       MuxedQCount      1        MuxQ-B          (In)
P1-19/DB25-10          47   IOPort       MuxedQCount      1        MuxQ-IDX        (In)
P1-21/DB25-11          48   IOPort       MuxedQCount      2        MuxQ-A          (In)
P1-23/DB25-12          49   IOPort       MuxedQCount      2        MuxQ-B          (In)
P1-25/DB25-13          50   IOPort       MuxedQCount      2        MuxQ-IDX        (In)

asis@192:~$ 

this now it's work ?
I have 1 more question.
How I can check for now it's can operate or can use input on 7i77 ?
Thank you

Asis,

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29 Aug 2023 12:17 - 29 Aug 2023 12:18 #279276 by PCW
That pinout is correct for a 7I77

To test you need to make sure the 5V supply jumpers match on the 7I96S and 7I77

Either:
7I77 W5 LEFT
7I96S W6 UP
(7I96S supplies 7I77 5V)

Or:
7I77 W5 RIGHT
7I96S W6 DOWN
(7I77 Gets 5V from TB1)

Then connect the 7I77 to the 7I96S P1 with a DB25M/IDC26 cable
supply field power to the 7I77 and start LinuxCNC
Last edit: 29 Aug 2023 12:18 by PCW.
The following user(s) said Thank You: abdulasis12

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06 Sep 2023 08:26 - 06 Sep 2023 12:52 #280071 by abdulasis12

That pinout is correct for a 7I77

To test you need to make sure the 5V supply jumpers match on the 7I96S and 7I77

Either:
7I77 W5 LEFT
7I96S W6 UP
(7I96S supplies 7I77 5V)

Or:
7I77 W5 RIGHT
7I96S W6 DOWN
(7I77 Gets 5V from TB1)

Then connect the 7I77 to the 7I96S P1 with a DB25M/IDC26 cable
supply field power to the 7I77 and start LinuxCNC

 

Hi
I have question
When open PNCCONF  on page config MESA CARD 0 
I choose Board : 7i96s internal Data
but Firmware not have 7i96s_7i77   , it's have 7i96s_7i74, 7i96s_d , 7i96s_dpl  only.
How I get Firmware for 7i96s_7i77 ?

 
 
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Last edit: 06 Sep 2023 12:52 by abdulasis12.

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06 Sep 2023 15:11 #280111 by PCW
I would create a configuration for a 7I92+7I77
and then change the card name in the .ini file from 7i92 to 7i96s

That should create a working 7I96S + 7I77 configuration
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13 Sep 2023 16:31 #280646 by abdulasis12

I would create a configuration for a 7I92+7I77
and then change the card name in the .ini file from 7i92 to 7i96s

That should create a working 7I96S + 7I77 configuration

It's work with your guide , Thank you  MR.PCW

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